From nobody Wed Nov 5 07:32:43 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linux.intel.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1533817050996494.7881777640996; Thu, 9 Aug 2018 05:17:30 -0700 (PDT) Received: from localhost ([::1]:50177 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fnjsf-0006yr-K4 for importer@patchew.org; Thu, 09 Aug 2018 08:17:29 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58024) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fnjVZ-0001bY-UT for qemu-devel@nongnu.org; Thu, 09 Aug 2018 07:53:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fnjVY-0001yq-7H for qemu-devel@nongnu.org; Thu, 09 Aug 2018 07:53:37 -0400 Received: from mga02.intel.com ([134.134.136.20]:34246) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fnjVX-0001xT-Om for qemu-devel@nongnu.org; Thu, 09 Aug 2018 07:53:36 -0400 Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 09 Aug 2018 04:53:35 -0700 Received: from sqa-gate.sh.intel.com (HELO robert-ivt.tsp.org) ([10.239.48.212]) by orsmga005.jf.intel.com with ESMTP; 09 Aug 2018 04:53:33 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.53,215,1531810800"; d="scan'208";a="247452656" From: Robert Hoo To: qemu-devel@nongnu.org, pbonzini@redhat.com, rth@twiddle.net, ehabkost@redhat.com, thomas.lendacky@amd.com Date: Thu, 9 Aug 2018 19:53:27 +0800 Message-Id: <1533815609-37245-2-git-send-email-robert.hu@linux.intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1533815609-37245-1-git-send-email-robert.hu@linux.intel.com> References: <1533815609-37245-1-git-send-email-robert.hu@linux.intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 134.134.136.20 Subject: [Qemu-devel] [PATCH v2 1/3] x86: Data structure changes to support MSR based features X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: robert.hu@intel.com, Robert Hoo , jingqi.liu@intel.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Define FeatureWordType. Expand FeatureWordInfo to support both CPUID type feature word as well as MSR type's. Change feature_word_info[] accordingly. Signed-off-by: Robert Hoo --- target/i386/cpu.c | 133 ++++++++++++++++++++++++++++++++++++++------------= ---- target/i386/cpu.h | 5 ++ 2 files changed, 99 insertions(+), 39 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index ba7abe5..77e1859 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -770,17 +770,36 @@ static void x86_cpu_vendor_words2str(char *dst, uint3= 2_t vendor1, /* missing: CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */ =20 +typedef enum FeatureWordType { + CPUID_FEATURE_WORD, + MSR_FEATURE_WORD, +} FeatureWordType; + typedef struct FeatureWordInfo { - /* feature flags names are taken from "Intel Processor Identification = and + FeatureWordType type; + /* feature flags names are taken from "Intel Processor Identification a= nd * the CPUID Instruction" and AMD's "CPUID Specification". * In cases of disagreement between feature naming conventions, * aliases may be added. */ const char *feat_names[32]; - uint32_t cpuid_eax; /* Input EAX for CPUID */ - bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */ - uint32_t cpuid_ecx; /* Input ECX value for CPUID */ - int cpuid_reg; /* output register (R_* constant) */ + union { + /* If type=3D=3DCPUID_FEATURE_WORD */ + struct { + uint32_t eax; /* Input EAX for CPUID */ + bool needs_ecx; /* CPUID instruction uses ECX as input */ + uint32_t ecx; /* Input ECX value for CPUID */ + int reg; /* output register (R_* constant) */ + } cpuid; + /* If type=3D=3DMSR_FEATURE_WORD */ + struct { + uint32_t index; + struct { /*CPUID that enumerate this MSR*/ + FeatureWord cpuid_class; + uint32_t cpuid_flag; + } cpuid_dep; + } msr; + }; uint32_t tcg_features; /* Feature flags supported by TCG */ uint32_t unmigratable_flags; /* Feature flags known to be unmigratable= */ uint32_t migratable_flags; /* Feature flags known to be migratable */ @@ -790,6 +809,7 @@ typedef struct FeatureWordInfo { =20 static FeatureWordInfo feature_word_info[FEATURE_WORDS] =3D { [FEAT_1_EDX] =3D { + .type =3D CPUID_FEATURE_WORD, .feat_names =3D { "fpu", "vme", "de", "pse", "tsc", "msr", "pae", "mce", @@ -800,10 +820,11 @@ static FeatureWordInfo feature_word_info[FEATURE_WORD= S] =3D { "fxsr", "sse", "sse2", "ss", "ht" /* Intel htt */, "tm", "ia64", "pbe", }, - .cpuid_eax =3D 1, .cpuid_reg =3D R_EDX, + .cpuid =3D {.eax =3D 1, .reg =3D R_EDX, }, .tcg_features =3D TCG_FEATURES, }, [FEAT_1_ECX] =3D { + .type =3D CPUID_FEATURE_WORD, .feat_names =3D { "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor", "ds-cpl", "vmx", "smx", "est", @@ -814,7 +835,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS]= =3D { "tsc-deadline", "aes", "xsave", NULL /* osxsave */, "avx", "f16c", "rdrand", "hypervisor", }, - .cpuid_eax =3D 1, .cpuid_reg =3D R_ECX, + .cpuid =3D { .eax =3D 1, .reg =3D R_ECX, }, .tcg_features =3D TCG_EXT_FEATURES, }, /* Feature names that are already defined on feature_name[] but @@ -823,6 +844,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS]= =3D { * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD. */ [FEAT_8000_0001_EDX] =3D { + .type =3D CPUID_FEATURE_WORD, .feat_names =3D { NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */, NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */, @@ -833,10 +855,11 @@ static FeatureWordInfo feature_word_info[FEATURE_WORD= S] =3D { NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp", NULL, "lm", "3dnowext", "3dnow", }, - .cpuid_eax =3D 0x80000001, .cpuid_reg =3D R_EDX, + .cpuid =3D { .eax =3D 0x80000001, .reg =3D R_EDX, }, .tcg_features =3D TCG_EXT2_FEATURES, }, [FEAT_8000_0001_ECX] =3D { + .type =3D CPUID_FEATURE_WORD, .feat_names =3D { "lahf-lm", "cmp-legacy", "svm", "extapic", "cr8legacy", "abm", "sse4a", "misalignsse", @@ -847,10 +870,11 @@ static FeatureWordInfo feature_word_info[FEATURE_WORD= S] =3D { "perfctr-nb", NULL, NULL, NULL, NULL, NULL, NULL, NULL, }, - .cpuid_eax =3D 0x80000001, .cpuid_reg =3D R_ECX, + .cpuid =3D { .eax =3D 0x80000001, .reg =3D R_ECX, }, .tcg_features =3D TCG_EXT3_FEATURES, }, [FEAT_C000_0001_EDX] =3D { + .type =3D CPUID_FEATURE_WORD, .feat_names =3D { NULL, NULL, "xstore", "xstore-en", NULL, NULL, "xcrypt", "xcrypt-en", @@ -861,10 +885,11 @@ static FeatureWordInfo feature_word_info[FEATURE_WORD= S] =3D { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, }, - .cpuid_eax =3D 0xC0000001, .cpuid_reg =3D R_EDX, + .cpuid =3D { .eax =3D 0xC0000001, .reg =3D R_EDX, }, .tcg_features =3D TCG_EXT4_FEATURES, }, [FEAT_KVM] =3D { + .type =3D CPUID_FEATURE_WORD, .feat_names =3D { "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock", "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt", @@ -875,10 +900,11 @@ static FeatureWordInfo feature_word_info[FEATURE_WORD= S] =3D { "kvmclock-stable-bit", NULL, NULL, NULL, NULL, NULL, NULL, NULL, }, - .cpuid_eax =3D KVM_CPUID_FEATURES, .cpuid_reg =3D R_EAX, + .cpuid =3D { .eax =3D KVM_CPUID_FEATURES, .reg =3D R_EAX, }, .tcg_features =3D TCG_KVM_FEATURES, }, [FEAT_KVM_HINTS] =3D { + .type =3D CPUID_FEATURE_WORD, .feat_names =3D { "kvm-hint-dedicated", NULL, NULL, NULL, NULL, NULL, NULL, NULL, @@ -889,7 +915,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS]= =3D { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, }, - .cpuid_eax =3D KVM_CPUID_FEATURES, .cpuid_reg =3D R_EDX, + .cpuid =3D { .eax =3D KVM_CPUID_FEATURES, .reg =3D R_EDX, }, .tcg_features =3D TCG_KVM_FEATURES, /* * KVM hints aren't auto-enabled by -cpu host, they need to be @@ -898,6 +924,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS]= =3D { .no_autoenable_flags =3D ~0U, }, [FEAT_HYPERV_EAX] =3D { + .type =3D CPUID_FEATURE_WORD, .feat_names =3D { NULL /* hv_msr_vp_runtime_access */, NULL /* hv_msr_time_refco= unt_access */, NULL /* hv_msr_synic_access */, NULL /* hv_msr_stimer_access *= /, @@ -912,9 +939,10 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS= ] =3D { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, }, - .cpuid_eax =3D 0x40000003, .cpuid_reg =3D R_EAX, + .cpuid =3D { .eax =3D 0x40000003, .reg =3D R_EAX, }, }, [FEAT_HYPERV_EBX] =3D { + .type =3D CPUID_FEATURE_WORD, .feat_names =3D { NULL /* hv_create_partitions */, NULL /* hv_access_partition_i= d */, NULL /* hv_access_memory_pool */, NULL /* hv_adjust_message_bu= ffers */, @@ -928,9 +956,10 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS= ] =3D { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, }, - .cpuid_eax =3D 0x40000003, .cpuid_reg =3D R_EBX, + .cpuid =3D { .eax =3D 0x40000003, .reg =3D R_EBX, }, }, [FEAT_HYPERV_EDX] =3D { + .type =3D CPUID_FEATURE_WORD, .feat_names =3D { NULL /* hv_mwait */, NULL /* hv_guest_debugging */, NULL /* hv_perf_monitor */, NULL /* hv_cpu_dynamic_part */, @@ -943,9 +972,10 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS= ] =3D { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, }, - .cpuid_eax =3D 0x40000003, .cpuid_reg =3D R_EDX, + .cpuid =3D { .eax =3D 0x40000003, .reg =3D R_EDX, }, }, [FEAT_SVM] =3D { + .type =3D CPUID_FEATURE_WORD, .feat_names =3D { "npt", "lbrv", "svm-lock", "nrip-save", "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists", @@ -956,10 +986,11 @@ static FeatureWordInfo feature_word_info[FEATURE_WORD= S] =3D { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, }, - .cpuid_eax =3D 0x8000000A, .cpuid_reg =3D R_EDX, + .cpuid =3D { .eax =3D 0x8000000A, .reg =3D R_EDX, }, .tcg_features =3D TCG_SVM_FEATURES, }, [FEAT_7_0_EBX] =3D { + .type =3D CPUID_FEATURE_WORD, .feat_names =3D { "fsgsbase", "tsc-adjust", NULL, "bmi1", "hle", "avx2", NULL, "smep", @@ -970,12 +1001,13 @@ static FeatureWordInfo feature_word_info[FEATURE_WOR= DS] =3D { "clwb", "intel-pt", "avx512pf", "avx512er", "avx512cd", "sha-ni", "avx512bw", "avx512vl", }, - .cpuid_eax =3D 7, - .cpuid_needs_ecx =3D true, .cpuid_ecx =3D 0, - .cpuid_reg =3D R_EBX, + .cpuid =3D { .eax =3D 7, + .needs_ecx =3D true, .ecx =3D 0, + .reg =3D R_EBX, }, .tcg_features =3D TCG_7_0_EBX_FEATURES, }, [FEAT_7_0_ECX] =3D { + .type =3D CPUID_FEATURE_WORD, .feat_names =3D { NULL, "avx512vbmi", "umip", "pku", NULL /* ospke */, NULL, "avx512vbmi2", NULL, @@ -986,12 +1018,13 @@ static FeatureWordInfo feature_word_info[FEATURE_WOR= DS] =3D { NULL, "cldemote", NULL, NULL, NULL, NULL, NULL, NULL, }, - .cpuid_eax =3D 7, - .cpuid_needs_ecx =3D true, .cpuid_ecx =3D 0, - .cpuid_reg =3D R_ECX, + .cpuid =3D { .eax =3D 7, + .needs_ecx =3D true, .ecx =3D 0, + .reg =3D R_ECX, }, .tcg_features =3D TCG_7_0_ECX_FEATURES, }, [FEAT_7_0_EDX] =3D { + .type =3D CPUID_FEATURE_WORD, .feat_names =3D { NULL, NULL, "avx512-4vnniw", "avx512-4fmaps", NULL, NULL, NULL, NULL, @@ -1002,13 +1035,14 @@ static FeatureWordInfo feature_word_info[FEATURE_WO= RDS] =3D { NULL, NULL, "spec-ctrl", NULL, NULL, "arch-capabilities", NULL, "ssbd", }, - .cpuid_eax =3D 7, - .cpuid_needs_ecx =3D true, .cpuid_ecx =3D 0, - .cpuid_reg =3D R_EDX, + .cpuid =3D { .eax =3D 7, + .needs_ecx =3D true, .ecx =3D 0, + .reg =3D R_EDX, }, .tcg_features =3D TCG_7_0_EDX_FEATURES, .unmigratable_flags =3D CPUID_7_0_EDX_ARCH_CAPABILITIES, }, [FEAT_8000_0007_EDX] =3D { + .type =3D CPUID_FEATURE_WORD, .feat_names =3D { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, @@ -1019,12 +1053,12 @@ static FeatureWordInfo feature_word_info[FEATURE_WO= RDS] =3D { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, }, - .cpuid_eax =3D 0x80000007, - .cpuid_reg =3D R_EDX, + .cpuid =3D { .eax =3D 0x80000007, .reg =3D R_EDX, }, .tcg_features =3D TCG_APM_FEATURES, .unmigratable_flags =3D CPUID_APM_INVTSC, }, [FEAT_8000_0008_EBX] =3D { + .type =3D CPUID_FEATURE_WORD, .feat_names =3D { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, @@ -1035,12 +1069,12 @@ static FeatureWordInfo feature_word_info[FEATURE_WO= RDS] =3D { "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL, NULL, NULL, NULL, NULL, }, - .cpuid_eax =3D 0x80000008, - .cpuid_reg =3D R_EBX, + .cpuid =3D { .eax =3D 0x80000008, .reg =3D R_EBX, }, .tcg_features =3D 0, .unmigratable_flags =3D 0, }, [FEAT_XSAVE] =3D { + .type =3D CPUID_FEATURE_WORD, .feat_names =3D { "xsaveopt", "xsavec", "xgetbv1", "xsaves", NULL, NULL, NULL, NULL, @@ -1051,12 +1085,13 @@ static FeatureWordInfo feature_word_info[FEATURE_WO= RDS] =3D { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, }, - .cpuid_eax =3D 0xd, - .cpuid_needs_ecx =3D true, .cpuid_ecx =3D 1, - .cpuid_reg =3D R_EAX, + .cpuid =3D { .eax =3D 0xd, + .needs_ecx =3D true, .ecx =3D 1, + .reg =3D R_EAX, }, .tcg_features =3D TCG_XSAVE_FEATURES, }, [FEAT_6_EAX] =3D { + .type =3D CPUID_FEATURE_WORD, .feat_names =3D { NULL, NULL, "arat", NULL, NULL, NULL, NULL, NULL, @@ -1067,13 +1102,14 @@ static FeatureWordInfo feature_word_info[FEATURE_WO= RDS] =3D { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, }, - .cpuid_eax =3D 6, .cpuid_reg =3D R_EAX, + .cpuid =3D { .eax =3D 6, .reg =3D R_EAX, }, .tcg_features =3D TCG_6_EAX_FEATURES, }, [FEAT_XSAVE_COMP_LO] =3D { - .cpuid_eax =3D 0xD, - .cpuid_needs_ecx =3D true, .cpuid_ecx =3D 0, - .cpuid_reg =3D R_EAX, + .type =3D CPUID_FEATURE_WORD, + .cpuid =3D { .eax =3D 0xD, + .needs_ecx =3D true, .ecx =3D 0, + .reg =3D R_EAX, }, .tcg_features =3D ~0U, .migratable_flags =3D XSTATE_FP_MASK | XSTATE_SSE_MASK | XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK | @@ -1081,11 +1117,30 @@ static FeatureWordInfo feature_word_info[FEATURE_WO= RDS] =3D { XSTATE_PKRU_MASK, }, [FEAT_XSAVE_COMP_HI] =3D { - .cpuid_eax =3D 0xD, - .cpuid_needs_ecx =3D true, .cpuid_ecx =3D 0, - .cpuid_reg =3D R_EDX, + .type =3D CPUID_FEATURE_WORD, + .cpuid =3D { .eax =3D 0xD, + .needs_ecx =3D true, .ecx =3D 0, + .reg =3D R_EDX, }, .tcg_features =3D ~0U, }, + /*Below are MSR exposed features*/ + [FEATURE_WORDS_ARCH_CAPABILITIES] =3D { + .type =3D MSR_FEATURE_WORD, + .feat_names =3D { + "rdctl-no", "ibrs-all", "rsba", NULL, + "ssb-no", NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + }, + .msr =3D { .index =3D MSR_IA32_ARCH_CAPABILITIES, + .cpuid_dep =3D { FEAT_7_0_EDX, + CPUID_7_0_EDX_ARCH_CAPABILITIES } + }, + }, }; =20 typedef struct X86RegisterInfo32 { diff --git a/target/i386/cpu.h b/target/i386/cpu.h index cddf9d9..9e8879e 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -502,9 +502,14 @@ typedef enum FeatureWord { FEAT_6_EAX, /* CPUID[6].EAX */ FEAT_XSAVE_COMP_LO, /* CPUID[EAX=3D0xd,ECX=3D0].EAX */ FEAT_XSAVE_COMP_HI, /* CPUID[EAX=3D0xd,ECX=3D0].EDX */ + FEATURE_WORDS_NUM_CPUID, + FEATURE_WORDS_FIRST_MSR =3D FEATURE_WORDS_NUM_CPUID, + FEATURE_WORDS_ARCH_CAPABILITIES =3D FEATURE_WORDS_FIRST_MSR, FEATURE_WORDS, } FeatureWord; =20 +#define FEATURE_WORDS_NUM_MSRS (FEATURE_WORDS - FEATURE_WORDS_FIRST_MSR) + typedef uint32_t FeatureWordArray[FEATURE_WORDS]; =20 /* cpuid_features bits */ --=20 1.8.3.1 From nobody Wed Nov 5 07:32:43 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linux.intel.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1533816795154787.0186594878817; Thu, 9 Aug 2018 05:13:15 -0700 (PDT) Received: from localhost ([::1]:50155 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fnjoX-0003Ry-VL for importer@patchew.org; Thu, 09 Aug 2018 08:13:14 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58032) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fnjVa-0001c6-JS for qemu-devel@nongnu.org; Thu, 09 Aug 2018 07:53:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fnjVZ-0001zZ-IK for qemu-devel@nongnu.org; Thu, 09 Aug 2018 07:53:38 -0400 Received: from mga02.intel.com ([134.134.136.20]:34246) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fnjVZ-0001xT-56 for qemu-devel@nongnu.org; Thu, 09 Aug 2018 07:53:37 -0400 Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 09 Aug 2018 04:53:36 -0700 Received: from sqa-gate.sh.intel.com (HELO robert-ivt.tsp.org) ([10.239.48.212]) by orsmga005.jf.intel.com with ESMTP; 09 Aug 2018 04:53:35 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.53,215,1531810800"; d="scan'208";a="247452661" From: Robert Hoo To: qemu-devel@nongnu.org, pbonzini@redhat.com, rth@twiddle.net, ehabkost@redhat.com, thomas.lendacky@amd.com Date: Thu, 9 Aug 2018 19:53:28 +0800 Message-Id: <1533815609-37245-3-git-send-email-robert.hu@linux.intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1533815609-37245-1-git-send-email-robert.hu@linux.intel.com> References: <1533815609-37245-1-git-send-email-robert.hu@linux.intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 134.134.136.20 Subject: [Qemu-devel] [PATCH v2 2/3] kvm: Add support to KVM_GET_MSR_FEATURE_INDEX_LIST and KVM_GET_MSRS system ioctl X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: robert.hu@intel.com, Robert Hoo , jingqi.liu@intel.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add kvm_get_supported_feature_msrs() to get supported MSR feature index lis= t. Add kvm_arch_get_supported_msr_feature() to get each MSR features value. kvm_get_supported_feature_msrs() is called in kvm_arch_init(). kvm_arch_get_supported_msr_feature() is called by x86_cpu_get_supported_feature_word(). Signed-off-by: Robert Hoo --- include/sysemu/kvm.h | 2 ++ target/i386/kvm.c | 78 ++++++++++++++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 80 insertions(+) diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h index 0b64b8e..0cf792f 100644 --- a/include/sysemu/kvm.h +++ b/include/sysemu/kvm.h @@ -463,6 +463,8 @@ int kvm_vm_check_extension(KVMState *s, unsigned int ex= tension); =20 uint32_t kvm_arch_get_supported_cpuid(KVMState *env, uint32_t function, uint32_t index, int reg); +uint32_t kvm_arch_get_supported_msr_feature(KVMState *s, uint32_t index); + =20 void kvm_set_sigmask_len(KVMState *s, unsigned int sigmask_len); =20 diff --git a/target/i386/kvm.c b/target/i386/kvm.c index 9313602..7268ab7 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -107,6 +107,7 @@ static int has_pit_state2; static bool has_msr_mcg_ext_ctl; =20 static struct kvm_cpuid2 *cpuid_cache; +static struct kvm_msr_list *kvm_feature_msrs; =20 int kvm_has_pit_state2(void) { @@ -420,6 +421,41 @@ uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uin= t32_t function, return ret; } =20 +uint32_t kvm_arch_get_supported_msr_feature(KVMState *s, uint32_t index) +{ + struct { + struct kvm_msrs info; + struct kvm_msr_entry entries[1]; + } msr_data; + uint32_t ret; + + /*Check if the requested feature MSR is supported*/ + int i; + for (i =3D 0; i < kvm_feature_msrs->nmsrs; i++) { + if (index =3D=3D kvm_feature_msrs->indices[i]) { + break; + } + } + if (i >=3D kvm_feature_msrs->nmsrs) { + fprintf(stderr, "Requested MSR (index=3D %d) is not supported.\n",= index); + return 0; + } + + msr_data.info.nmsrs =3D 1; + msr_data.entries[0].index =3D index; + + ret =3D kvm_ioctl(s, KVM_GET_MSRS, &msr_data); + + if (ret !=3D 1) { + fprintf(stderr, "KVM get MSR (index=3D0x%x) feature failed, %s\n", + index, strerror(-ret)); + exit(1); + } + + return msr_data.entries[0].data; +} + + typedef struct HWPoisonPage { ram_addr_t ram_addr; QLIST_ENTRY(HWPoisonPage) list; @@ -1238,7 +1274,44 @@ void kvm_arch_do_init_vcpu(X86CPU *cpu) env->mp_state =3D KVM_MP_STATE_INIT_RECEIVED; } } +static int kvm_get_supported_feature_msrs(KVMState *s) +{ + static int kvm_supported_feature_msrs; + int ret =3D 0; + + if (kvm_supported_feature_msrs =3D=3D 0) { + struct kvm_msr_list msr_list; + + kvm_supported_feature_msrs++; + + msr_list.nmsrs =3D 0; + ret =3D kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, &msr_list); + if (ret < 0 && ret !=3D -E2BIG) { + return ret; + } + + assert(msr_list.nmsrs > 0); + kvm_feature_msrs =3D (struct kvm_msr_list *) \ + g_malloc0(sizeof(msr_list) + + msr_list.nmsrs * sizeof(msr_list.indices[0])); + if (kvm_feature_msrs =3D=3D NULL) { + fprintf(stderr, "Failed to allocate space for KVM Feature MSRs" + "which has %d MSRs\n", msr_list.nmsrs); + return -1; + } + + kvm_feature_msrs->nmsrs =3D msr_list.nmsrs; + ret =3D kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, kvm_feature_m= srs); =20 + if (ret < 0) { /*ioctl failure*/ + fprintf(stderr, "Fetch KVM feature MSRs failed: %s\n", + strerror(-ret)); + g_free(kvm_feature_msrs); + return ret; + } + } + + return 0; +} static int kvm_get_supported_msrs(KVMState *s) { static int kvm_supported_msrs; @@ -1400,6 +1473,11 @@ int kvm_arch_init(MachineState *ms, KVMState *s) return ret; } =20 + ret =3D kvm_get_supported_feature_msrs(s); + if (ret < 0) { + return ret; + } + uname(&utsname); lm_capable_kernel =3D strcmp(utsname.machine, "x86_64") =3D=3D 0; =20 --=20 1.8.3.1 From nobody Wed Nov 5 07:32:43 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linux.intel.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1533816971932195.7714182337362; Thu, 9 Aug 2018 05:16:11 -0700 (PDT) Received: from localhost ([::1]:50174 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fnjrK-00060c-99 for importer@patchew.org; Thu, 09 Aug 2018 08:16:06 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58048) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fnjVd-0001cT-2q for qemu-devel@nongnu.org; Thu, 09 Aug 2018 07:53:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fnjVb-00020W-4L for qemu-devel@nongnu.org; Thu, 09 Aug 2018 07:53:40 -0400 Received: from mga02.intel.com ([134.134.136.20]:34246) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fnjVa-0001xT-Ol for qemu-devel@nongnu.org; Thu, 09 Aug 2018 07:53:39 -0400 Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 09 Aug 2018 04:53:38 -0700 Received: from sqa-gate.sh.intel.com (HELO robert-ivt.tsp.org) ([10.239.48.212]) by orsmga005.jf.intel.com with ESMTP; 09 Aug 2018 04:53:36 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.53,215,1531810800"; d="scan'208";a="247452665" From: Robert Hoo To: qemu-devel@nongnu.org, pbonzini@redhat.com, rth@twiddle.net, ehabkost@redhat.com, thomas.lendacky@amd.com Date: Thu, 9 Aug 2018 19:53:29 +0800 Message-Id: <1533815609-37245-4-git-send-email-robert.hu@linux.intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1533815609-37245-1-git-send-email-robert.hu@linux.intel.com> References: <1533815609-37245-1-git-send-email-robert.hu@linux.intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 134.134.136.20 Subject: [Qemu-devel] [PATCH v2 3/3] Change other funcitons referring to feature_word_info[] X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: robert.hu@intel.com, Robert Hoo , jingqi.liu@intel.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add an util function feature_word_description(), which help construct the s= tring describing the feature word (both CPUID and MSR types). report_unavailable_features(): add MSR_FEATURE_WORD type support. x86_cpu_get_feature_words(): limit to CPUID_FEATURE_WORD only. x86_cpu_get_supported_feature_word(): add MSR_FEATURE_WORD type support. x86_cpu_adjust_feat_level(): assert the requested feature must be CPUID_FEATURE_WORD type. Signed-off-by: Robert Hoo --- target/i386/cpu.c | 76 +++++++++++++++++++++++++++++++++++++++++----------= ---- 1 file changed, 57 insertions(+), 19 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 77e1859..51989e5 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -3024,21 +3024,50 @@ static const TypeInfo host_x86_cpu_type_info =3D { =20 #endif =20 +/* +*caller should have input str no less than 64 byte length. +*/ +#define FEATURE_WORD_DESCPTION_LEN 64 +static int feature_word_description(char str[], FeatureWordInfo *f, + uint32_t bit) +{ + int ret; + + assert(f->type =3D=3D CPUID_FEATURE_WORD || + f->type =3D=3D MSR_FEATURE_WORD); + switch (f->type) { + case CPUID_FEATURE_WORD: + { + const char *reg =3D get_register_name_32(f->cpuid.reg); + assert(reg); + ret =3D snprintf(str, FEATURE_WORD_DESCPTION_LEN, + "CPUID.%02XH:%s%s%s [bit %d]", + f->cpuid.eax, reg, + f->feat_names[bit] ? "." : "", + f->feat_names[bit] ? f->feat_names[bit] : "", bit); + break; + } + case MSR_FEATURE_WORD: + ret =3D snprintf(str, FEATURE_WORD_DESCPTION_LEN, + "MSR(%xH).%s [bit %d]", + f->msr.index, + f->feat_names[bit] ? f->feat_names[bit] : "", bit); + break; + } + return ret > 0; +} + static void report_unavailable_features(FeatureWord w, uint32_t mask) { FeatureWordInfo *f =3D &feature_word_info[w]; int i; + char feat_word_dscrp_str[FEATURE_WORD_DESCPTION_LEN]; =20 for (i =3D 0; i < 32; ++i) { if ((1UL << i) & mask) { - const char *reg =3D get_register_name_32(f->cpuid_reg); - assert(reg); - warn_report("%s doesn't support requested feature: " - "CPUID.%02XH:%s%s%s [bit %d]", + feature_word_description(feat_word_dscrp_str, f, i); + warn_report("%s doesn't support requested feature: %s", accel_uses_host_cpuid() ? "host" : "TCG", - f->cpuid_eax, reg, - f->feat_names[i] ? "." : "", - f->feat_names[i] ? f->feat_names[i] : "", i); + feat_word_dscrp_str); } } } @@ -3276,17 +3305,17 @@ static void x86_cpu_get_feature_words(Object *obj, = Visitor *v, { uint32_t *array =3D (uint32_t *)opaque; FeatureWord w; - X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] =3D { }; - X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] =3D { }; + X86CPUFeatureWordInfo word_infos[FEATURE_WORDS_NUM_CPUID] =3D { }; + X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS_NUM_CPUID] =3D { = }; X86CPUFeatureWordInfoList *list =3D NULL; =20 - for (w =3D 0; w < FEATURE_WORDS; w++) { + for (w =3D 0; w < FEATURE_WORDS_NUM_CPUID; w++) { FeatureWordInfo *wi =3D &feature_word_info[w]; X86CPUFeatureWordInfo *qwi =3D &word_infos[w]; - qwi->cpuid_input_eax =3D wi->cpuid_eax; - qwi->has_cpuid_input_ecx =3D wi->cpuid_needs_ecx; - qwi->cpuid_input_ecx =3D wi->cpuid_ecx; - qwi->cpuid_register =3D x86_reg_info_32[wi->cpuid_reg].qapi_enum; + qwi->cpuid_input_eax =3D wi->cpuid.eax; + qwi->has_cpuid_input_ecx =3D wi->cpuid.needs_ecx; + qwi->cpuid_input_ecx =3D wi->cpuid.ecx; + qwi->cpuid_register =3D x86_reg_info_32[wi->cpuid.reg].qapi_enum; qwi->features =3D array[w]; =20 /* List will be in reverse order, but order shouldn't matter */ @@ -3659,12 +3688,20 @@ static uint32_t x86_cpu_get_supported_feature_word(= FeatureWord w, bool migratable_only) { FeatureWordInfo *wi =3D &feature_word_info[w]; - uint32_t r; + uint32_t r =3D 0; =20 if (kvm_enabled()) { - r =3D kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid_eax, - wi->cpuid_ecx, - wi->cpuid_reg); + switch (wi->type) { + case CPUID_FEATURE_WORD: + r =3D kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax, + wi->cpuid.ecx, + wi->cpuid.reg); + break; + case MSR_FEATURE_WORD: + r =3D kvm_arch_get_supported_msr_feature(kvm_state, + wi->msr.index); + break; + } } else if (hvf_enabled()) { r =3D hvf_get_supported_cpuid(wi->cpuid_eax, wi->cpuid_ecx, @@ -4732,9 +4769,10 @@ static void x86_cpu_adjust_feat_level(X86CPU *cpu, F= eatureWord w) { CPUX86State *env =3D &cpu->env; FeatureWordInfo *fi =3D &feature_word_info[w]; - uint32_t eax =3D fi->cpuid_eax; + uint32_t eax =3D fi->cpuid.eax; uint32_t region =3D eax & 0xF0000000; =20 + assert(feature_word_info[w].type =3D=3D CPUID_FEATURE_WORD); if (!env->features[w]) { return; } --=20 1.8.3.1