From nobody Tue Feb 10 11:12:34 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=oracle.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1533816536298974.0238989761065; Thu, 9 Aug 2018 05:08:56 -0700 (PDT) Received: from localhost ([::1]:50128 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fnjkM-0007sc-Qo for importer@patchew.org; Thu, 09 Aug 2018 08:08:54 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56418) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fnjPt-0005C8-3G for qemu-devel@nongnu.org; Thu, 09 Aug 2018 07:47:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fnjPq-0007Ot-Er for qemu-devel@nongnu.org; Thu, 09 Aug 2018 07:47:45 -0400 Received: from userp2130.oracle.com ([156.151.31.86]:34316) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fnjPq-0007Nx-58 for qemu-devel@nongnu.org; Thu, 09 Aug 2018 07:47:42 -0400 Received: from pps.filterd (userp2130.oracle.com [127.0.0.1]) by userp2130.oracle.com (8.16.0.22/8.16.0.22) with SMTP id w79BiKiu145690; Thu, 9 Aug 2018 11:47:41 GMT Received: from userv0021.oracle.com (userv0021.oracle.com [156.151.31.71]) by userp2130.oracle.com with ESMTP id 2kn3jtav6e-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 09 Aug 2018 11:47:41 +0000 Received: from aserv0122.oracle.com (aserv0122.oracle.com [141.146.126.236]) by userv0021.oracle.com (8.14.4/8.14.4) with ESMTP id w79BleGQ012232 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 9 Aug 2018 11:47:40 GMT Received: from abhmp0014.oracle.com (abhmp0014.oracle.com [141.146.116.20]) by aserv0122.oracle.com (8.14.4/8.14.4) with ESMTP id w79Ble1w031258; Thu, 9 Aug 2018 11:47:40 GMT Received: from liran-pc.ravello.local (/213.57.127.2) by default (Oracle Beehive Gateway v4.0) with ESMTP ; Thu, 09 Aug 2018 04:47:39 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oracle.com; h=from : to : cc : subject : date : message-id : in-reply-to : references; s=corp-2018-07-02; bh=cYHYk4Hf6M72ZUOS/Ddiab6WOYLRTB7AHXFvWVIHouo=; b=wkFXd9jYHdKM2/PxnJq/6eiGsgm8z4xKXs2G6RiKIg3jk+W5qc7jZQmu61Fdcm1n3pxj I5lv/ylqzMqLIvybPdmFoftkKFq6VkEemp0ON+hvb8i+yuezodOW99555ew//geP/Isk jnMkEmWXm1U2X89K264TmX+hZ+j/LspxqJEAcvcH8hEH1IQkwz82aLwgklLrkJ5EvTVb +OdLz56cqs8pW258a2KYyiwKiQKJtPoaK4ioz2nzJmseyIBk6we+tT237xt9zo32c8mp vTjyUgFmPLVg+quAZj8KK2KEDVde7UbFlVfoP9jS995oRJ9PZVyDypfcR8Bymz0N4BPa ww== From: Liran Alon To: qemu-devel@nongnu.org Date: Thu, 9 Aug 2018 14:46:28 +0300 Message-Id: <1533815202-11967-16-git-send-email-liran.alon@oracle.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1533815202-11967-1-git-send-email-liran.alon@oracle.com> References: <1533815202-11967-1-git-send-email-liran.alon@oracle.com> X-Proofpoint-Virus-Version: vendor=nai engine=5900 definitions=8979 signatures=668707 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 suspectscore=1 malwarescore=0 phishscore=0 bulkscore=0 spamscore=0 mlxscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1807170000 definitions=main-1808090123 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 156.151.31.86 Subject: [Qemu-devel] [PATCH 15/29] vmsvga: Add interrupt mask and status registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: habkost@redhat.com, mtosatti@redhat.com, Liran Alon , kraxel@redhat.com, pbonzini@redhat.com, rth@twiddle.net, Leonid Shatz Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Leonid Shatz Add missing functionality of interrupt mask and status registers. Writing to interrupt status register clears interrupt request. Signed-off-by: Leonid Shatz Reviewed-by: Darren Kenny Signed-off-by: Liran Alon --- hw/display/vmware_vga.c | 52 +++++++++++++++++++++++++++++++++++++++++++++= +++- 1 file changed, 51 insertions(+), 1 deletion(-) diff --git a/hw/display/vmware_vga.c b/hw/display/vmware_vga.c index eae3f1455445..4e4f6f8eec42 100644 --- a/hw/display/vmware_vga.c +++ b/hw/display/vmware_vga.c @@ -78,6 +78,8 @@ struct vmsvga_state_s { int redraw_fifo_first, redraw_fifo_last; =20 uint32_t num_fifo_regs; + uint32_t irq_mask; + uint32_t irq_status; }; =20 #define TYPE_VMWARE_SVGA "vmware-svga" @@ -104,6 +106,7 @@ struct pci_vmsvga_state_s { #define SVGA_INDEX_PORT 0x0 #define SVGA_VALUE_PORT 0x1 #define SVGA_BIOS_PORT 0x2 +#define SVGA_IRQSTATUS_PORT 0x8 =20 #define SVGA_VERSION_2 =20 @@ -158,6 +161,7 @@ enum { SVGA_REG_MEM_REGS =3D 30, /* Number of FIFO registers */ SVGA_REG_NUM_DISPLAYS =3D 31, /* Number of guest displays */ SVGA_REG_PITCHLOCK =3D 32, /* Fixed pitch for all modes */ + SVGA_REG_IRQMASK =3D 33, /* Interrupt mask */ =20 SVGA_PALETTE_BASE =3D 1024, /* Base of SVGA color map */ SVGA_PALETTE_END =3D SVGA_PALETTE_BASE + 767, @@ -183,6 +187,7 @@ enum { #define SVGA_CAP_EXTENDED_FIFO (1 << 15) #define SVGA_CAP_MULTIMON (1 << 16) #define SVGA_CAP_PITCHLOCK (1 << 17) +#define SVGA_CAP_IRQMASK (1 << 18) =20 /* * FIFO offsets (seen as an array of 32-bit words) @@ -1034,6 +1039,7 @@ static uint32_t vmsvga_value_read(void *opaque, uint3= 2_t address) } #endif caps |=3D SVGA_CAP_EXTENDED_FIFO; + caps |=3D SVGA_CAP_IRQMASK; ret =3D caps; break; =20 @@ -1091,6 +1097,10 @@ static uint32_t vmsvga_value_read(void *opaque, uint= 32_t address) ret =3D 0; break; =20 + case SVGA_REG_IRQMASK: + ret =3D s->irq_mask; + break; + default: if (s->index >=3D SVGA_SCRATCH_BASE && s->index < SVGA_SCRATCH_BASE + s->scratch_size) { @@ -1221,6 +1231,10 @@ static void vmsvga_value_write(void *opaque, uint32_= t address, uint32_t value) case SVGA_PALETTE_BASE ... SVGA_PALETTE_END: break; =20 + case SVGA_REG_IRQMASK: + s->irq_mask =3D value; + break; + default: if (s->index >=3D SVGA_SCRATCH_BASE && s->index < SVGA_SCRATCH_BASE + s->scratch_size) { @@ -1231,6 +1245,28 @@ static void vmsvga_value_write(void *opaque, uint32_= t address, uint32_t value) } } =20 +static uint32_t vmsvga_irqstatus_read(void *opaque, uint32_t address) +{ + struct vmsvga_state_s *s =3D opaque; + return s->irq_status; +} + +static void vmsvga_irqstatus_write(void *opaque, uint32_t address, uint32_= t data) +{ + struct vmsvga_state_s *s =3D opaque; + struct pci_vmsvga_state_s *pci_vmsvga =3D + container_of(s, struct pci_vmsvga_state_s, chip); + PCIDevice *pci_dev =3D PCI_DEVICE(pci_vmsvga); + + /* + * Clear selected interrupt sources and lower + * interrupt request when none are left active + */ + s->irq_status &=3D ~data; + if (!s->irq_status) + pci_set_irq(pci_dev, 0); +} + static uint32_t vmsvga_bios_read(void *opaque, uint32_t address) { printf("%s: what are we supposed to return?\n", __func__); @@ -1298,6 +1334,8 @@ static void vmsvga_reset(DeviceState *dev) s->redraw_fifo_first =3D 0; s->redraw_fifo_last =3D 0; s->syncing =3D 0; + s->irq_mask =3D 0; + s->irq_status =3D 0; =20 vga_dirty_log_start(&s->vga); } @@ -1327,12 +1365,18 @@ static int vmsvga_post_load(void *opaque, int versi= on_id) struct vmsvga_state_s *s =3D opaque; =20 s->invalidated =3D 1; + + if (version_id < 1) { + s->irq_mask =3D 0; + s->irq_status =3D 0; + } + return 0; } =20 static const VMStateDescription vmstate_vmware_vga_internal =3D { .name =3D "vmware_vga_internal", - .version_id =3D 0, + .version_id =3D 1, .minimum_version_id =3D 0, .post_load =3D vmsvga_post_load, .fields =3D (VMStateField[]) { @@ -1352,6 +1396,8 @@ static const VMStateDescription vmstate_vmware_vga_in= ternal =3D { VMSTATE_UINT32(svgaid, struct vmsvga_state_s), VMSTATE_INT32(syncing, struct vmsvga_state_s), VMSTATE_UNUSED(4), /* was fb_size */ + VMSTATE_UINT32_V(irq_mask, struct vmsvga_state_s, 1), + VMSTATE_UINT32_V(irq_status, struct vmsvga_state_s, 1), VMSTATE_END_OF_LIST() } }; @@ -1404,6 +1450,7 @@ static uint64_t vmsvga_io_read(void *opaque, hwaddr a= ddr, unsigned size) case SVGA_IO_MUL * SVGA_INDEX_PORT: return vmsvga_index_read(s, addr); case SVGA_IO_MUL * SVGA_VALUE_PORT: return vmsvga_value_read(s, addr); case SVGA_IO_MUL * SVGA_BIOS_PORT: return vmsvga_bios_read(s, addr); + case SVGA_IO_MUL * SVGA_IRQSTATUS_PORT: return vmsvga_irqstatus_read(s= , addr); default: return -1u; } } @@ -1423,6 +1470,9 @@ static void vmsvga_io_write(void *opaque, hwaddr addr, case SVGA_IO_MUL * SVGA_BIOS_PORT: vmsvga_bios_write(s, addr, data); break; + case SVGA_IO_MUL * SVGA_IRQSTATUS_PORT: + vmsvga_irqstatus_write(s, addr, data); + break; } } =20 --=20 1.9.1