From nobody Tue Feb 10 21:59:30 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=oracle.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1533815992991912.7265524818716; Thu, 9 Aug 2018 04:59:52 -0700 (PDT) Received: from localhost ([::1]:50078 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fnjbb-0007Rn-R2 for importer@patchew.org; Thu, 09 Aug 2018 07:59:51 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56371) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fnjPk-000542-I4 for qemu-devel@nongnu.org; Thu, 09 Aug 2018 07:47:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fnjPh-0007FO-TY for qemu-devel@nongnu.org; Thu, 09 Aug 2018 07:47:36 -0400 Received: from userp2130.oracle.com ([156.151.31.86]:34222) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fnjPh-0007Ej-JQ for qemu-devel@nongnu.org; Thu, 09 Aug 2018 07:47:33 -0400 Received: from pps.filterd (userp2130.oracle.com [127.0.0.1]) by userp2130.oracle.com (8.16.0.22/8.16.0.22) with SMTP id w79BiQMA145707; Thu, 9 Aug 2018 11:47:32 GMT Received: from userv0021.oracle.com (userv0021.oracle.com [156.151.31.71]) by userp2130.oracle.com with ESMTP id 2kn3jtav5y-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 09 Aug 2018 11:47:32 +0000 Received: from userv0122.oracle.com (userv0122.oracle.com [156.151.31.75]) by userv0021.oracle.com (8.14.4/8.14.4) with ESMTP id w79BlWwr012024 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 9 Aug 2018 11:47:32 GMT Received: from abhmp0014.oracle.com (abhmp0014.oracle.com [141.146.116.20]) by userv0122.oracle.com (8.14.4/8.14.4) with ESMTP id w79BlVqR000325; Thu, 9 Aug 2018 11:47:31 GMT Received: from liran-pc.ravello.local (/213.57.127.2) by default (Oracle Beehive Gateway v4.0) with ESMTP ; Thu, 09 Aug 2018 04:47:31 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oracle.com; h=from : to : cc : subject : date : message-id : in-reply-to : references; s=corp-2018-07-02; bh=iTd362jt7egGZjlgzXCppOrgG4Hnoom22JQGmAl9Dcg=; b=a5O7n3+bUf9f07rc+HphDnvxBD56YUMEHKkYw+mrjq7q5q3Dq4sjasEPQ0twAz3uPzae 151SWIYeDV0lR8WQIYP5LElk9PoEKEP43RGli8KmYGx9o8sdE+SDm/COhkebIvVoLQzR DymB9TcO9hHmoEp9TI1WZbkrK5zC9BWJOAdrtiex6pVOKsIlfaQm5L4n6TKBDpfC3ZcL js7PunKXYtSz/tdhoIXi0nCbAWKSF3VF8SnGwCGLmQZgPNC3cYTUOE14/nxDipJ4ZWKJ /BFH5yGPErv4nPHHMJZcWB0PYWyKymEeZrMklaOsko94ou5cvss3Sd7xOmDEkpNqvVCu cw== From: Liran Alon To: qemu-devel@nongnu.org Date: Thu, 9 Aug 2018 14:46:25 +0300 Message-Id: <1533815202-11967-13-git-send-email-liran.alon@oracle.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1533815202-11967-1-git-send-email-liran.alon@oracle.com> References: <1533815202-11967-1-git-send-email-liran.alon@oracle.com> X-Proofpoint-Virus-Version: vendor=nai engine=5900 definitions=8979 signatures=668707 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 suspectscore=1 malwarescore=0 phishscore=0 bulkscore=0 spamscore=0 mlxscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1807170000 definitions=main-1808090123 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 156.151.31.86 Subject: [Qemu-devel] [PATCH 12/29] vmsvga: Add definitions of FIFO registers and report their number X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: habkost@redhat.com, mtosatti@redhat.com, Liran Alon , kraxel@redhat.com, pbonzini@redhat.com, rth@twiddle.net, Leonid Shatz Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Leonid Shatz Import FIFO register definitions from VMware SVGA Device Developer Kit. Report number of available registers so that guest device driver can reserve enough space for registers before command FIFO. Signed-off-by: Leonid Shatz Reviewed-by: Darren Kenny Signed-off-by: Liran Alon --- hw/display/vmware_vga.c | 126 ++++++++++++++++++++++++++++++++++++++++++++= ++-- 1 file changed, 121 insertions(+), 5 deletions(-) diff --git a/hw/display/vmware_vga.c b/hw/display/vmware_vga.c index f0e6b4bc74ba..8eeb0efc9cab 100644 --- a/hw/display/vmware_vga.c +++ b/hw/display/vmware_vga.c @@ -76,6 +76,8 @@ struct vmsvga_state_s { int x, y, w, h; } redraw_fifo[REDRAW_FIFO_LEN]; int redraw_fifo_first, redraw_fifo_last; + + uint32_t num_fifo_regs; }; =20 #define TYPE_VMWARE_SVGA "vmware-svga" @@ -194,14 +196,124 @@ enum { SVGA_FIFO_NEXT, SVGA_FIFO_STOP, =20 - /* - * Additional offsets added as of SVGA_CAP_EXTENDED_FIFO - */ + /* + * Block 2 (extended registers): Mandatory registers for the extended + * FIFO. These exist if the SVGA caps register includes + * SVGA_CAP_EXTENDED_FIFO; some of them are valid only if their + * associated capability bit is enabled. + * + * Note that when originally defined, SVGA_CAP_EXTENDED_FIFO implied + * support only for (FIFO registers) CAPABILITIES, FLAGS, and FENCE. + * This means that the guest has to test individually (in most cases + * using FIFO caps) for the presence of registers after this; the VMX + * can define "extended FIFO" to mean whatever it wants, and currently + * won't enable it unless there's room for that set and much more. + */ + SVGA_FIFO_CAPABILITIES =3D 4, SVGA_FIFO_FLAGS, SVGA_FIFO_FENCE, - SVGA_FIFO_3D_HWVERSION, - SVGA_FIFO_PITCHLOCK, + + /* + * Block 3a (optional extended registers): Additional registers for the + * extended FIFO, whose presence isn't actually implied by + * SVGA_CAP_EXTENDED_FIFO; these exist if SVGA_FIFO_MIN is high enough = to + * leave room for them. + * + * These in block 3a, the VMX currently considers mandatory for the + * extended FIFO. + */ + + /* Valid if exists (i.e. if extended FIFO enabled): */ + SVGA_FIFO_3D_HWVERSION, /* See SVGA3dHardwareVersion in svga3d_re= g.h */ + /* Valid with SVGA_FIFO_CAP_PITCHLOCK: */ + SVGA_FIFO_PITCHLOCK, + + /* Valid with SVGA_FIFO_CAP_CURSOR_BYPASS_3: */ + SVGA_FIFO_CURSOR_ON, /* Cursor bypass 3 show/hide register */ + SVGA_FIFO_CURSOR_X, /* Cursor bypass 3 x register */ + SVGA_FIFO_CURSOR_Y, /* Cursor bypass 3 y register */ + SVGA_FIFO_CURSOR_COUNT, /* Incremented when any of the other 3 ch= ange */ + SVGA_FIFO_CURSOR_LAST_UPDATED,/* Last time the host updated the cursor = */ + + /* Valid with SVGA_FIFO_CAP_RESERVE: */ + SVGA_FIFO_RESERVED, /* Bytes past NEXT_CMD with real contents= */ + + /* + * Valid with SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJEC= T_2: + * + * By default this is SVGA_ID_INVALID, to indicate that the cursor + * coordinates are specified relative to the virtual root. If this + * is set to a specific screen ID, cursor position is reinterpreted + * as a signed offset relative to that screen's origin. + */ + SVGA_FIFO_CURSOR_SCREEN_ID, + + /* + * Valid with SVGA_FIFO_CAP_DEAD + * + * An arbitrary value written by the host, drivers should not use it. + */ + SVGA_FIFO_DEAD, + + /* + * Valid with SVGA_FIFO_CAP_3D_HWVERSION_REVISED: + * + * Contains 3D HWVERSION (see SVGA3dHardwareVersion in svga3d_reg.h) + * on platforms that can enforce graphics resource limits. + */ + SVGA_FIFO_3D_HWVERSION_REVISED, + + /* + * XXX: The gap here, up until SVGA_FIFO_3D_CAPS, can be used for new + * registers, but this must be done carefully and with judicious use of + * capability bits, since comparisons based on SVGA_FIFO_MIN aren't + * enough to tell you whether the register exists: we've shipped drivers + * and products that used SVGA_FIFO_3D_CAPS but didn't know about some = of + * the earlier ones. The actual order of introduction was: + * - PITCHLOCK + * - 3D_CAPS + * - CURSOR_* (cursor bypass 3) + * - RESERVED + * So, code that wants to know whether it can use any of the + * aforementioned registers, or anything else added after PITCHLOCK and + * before 3D_CAPS, needs to reason about something other than + * SVGA_FIFO_MIN. + */ + + /* + * 3D caps block space; valid with 3D hardware version >=3D + * SVGA3D_HWVERSION_WS6_B1. + */ + SVGA_FIFO_3D_CAPS =3D 32, + SVGA_FIFO_3D_CAPS_LAST =3D 32 + 255, + + /* + * End of VMX's current definition of "extended-FIFO registers". + * Registers before here are always enabled/disabled as a block; either + * the extended FIFO is enabled and includes all preceding registers, or + * it's disabled entirely. + * + * Block 3b (truly optional extended registers): Additional registers f= or + * the extended FIFO, which the VMX already knows how to enable and + * disable with correct granularity. + * + * Registers after here exist if and only if the guest SVGA driver + * sets SVGA_FIFO_MIN high enough to leave room for them. + */ + + /* Valid if register exists: */ + SVGA_FIFO_GUEST_3D_HWVERSION, /* Guest driver's 3D version */ + SVGA_FIFO_FENCE_GOAL, /* Matching target for SVGA_IRQFLAG_FENCE= _GOAL */ + SVGA_FIFO_BUSY, /* See "FIFO Synchronization Registers" */ + + /* + * Always keep this last. This defines the maximum number of + * registers we know about. At power-on, this value is placed in + * the SVGA_REG_MEM_REGS register, and we expect the guest driver + * to allocate this much space in FIFO memory for registers. + */ + SVGA_FIFO_NUM_REGS }; =20 #define SVGA_FIFO_CAP_NONE 0 @@ -969,6 +1081,9 @@ static uint32_t vmsvga_value_read(void *opaque, uint32= _t address) break; =20 case SVGA_REG_MEM_REGS: + ret =3D s->num_fifo_regs; + break; + case SVGA_REG_NUM_DISPLAYS: case SVGA_REG_PITCHLOCK: case SVGA_PALETTE_BASE ... SVGA_PALETTE_END: @@ -1268,6 +1383,7 @@ static void vmsvga_init(DeviceState *dev, struct vmsv= ga_state_s *s, memory_region_init_ram(&s->fifo_ram, NULL, "vmsvga.fifo", s->fifo_size, &error_fatal); s->fifo =3D (uint32_t *)memory_region_get_ram_ptr(&s->fifo_ram); + s->num_fifo_regs =3D SVGA_FIFO_NUM_REGS; =20 vga_common_init(&s->vga, OBJECT(dev)); vga_init(&s->vga, OBJECT(dev), address_space, io, true); --=20 1.9.1