From nobody Wed Nov 5 10:41:21 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linux.intel.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1533814670293548.0519562534578; Thu, 9 Aug 2018 04:37:50 -0700 (PDT) Received: from localhost ([::1]:49961 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fnjGH-0007SG-50 for importer@patchew.org; Thu, 09 Aug 2018 07:37:49 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52875) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fnjBJ-0003NG-NM for qemu-devel@nongnu.org; Thu, 09 Aug 2018 07:32:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fnjBI-0000xK-O2 for qemu-devel@nongnu.org; Thu, 09 Aug 2018 07:32:41 -0400 Received: from mga03.intel.com ([134.134.136.65]:42140) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fnjBI-0000wd-B5 for qemu-devel@nongnu.org; Thu, 09 Aug 2018 07:32:40 -0400 Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 09 Aug 2018 04:32:40 -0700 Received: from sqa-gate.sh.intel.com (HELO robert-ivt.tsp.org) ([10.239.48.212]) by orsmga003.jf.intel.com with ESMTP; 09 Aug 2018 04:32:38 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.53,214,1531810800"; d="scan'208";a="74012458" From: Robert Hoo To: qemu-devel@nongnu.org, pbonzini@redhat.com, rth@twiddle.net, ehabkost@redhat.com, thomas.lendacky@amd.com Date: Thu, 9 Aug 2018 19:32:29 +0800 Message-Id: <1533814349-34727-4-git-send-email-robert.hu@linux.intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1533814349-34727-1-git-send-email-robert.hu@linux.intel.com> References: <1533814349-34727-1-git-send-email-robert.hu@linux.intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 134.134.136.65 Subject: [Qemu-devel] [PATCH v1 3/3] Change other funcitons referring to feature_word_info[] X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: robert.hu@intel.com, Robert Hoo , jingqi.liu@intel.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add an util function feature_word_description(), which help construct the s= tring describing the feature word (both CPUID and MSR types). report_unavailable_features(): add MSR_FEATURE_WORD type support. x86_cpu_get_feature_words(): limit to CPUID_FEATURE_WORD only. x86_cpu_get_supported_feature_word(): add MSR_FEATURE_WORD type support. x86_cpu_adjust_feat_level(): assert the requested feature must be CPUID_FEATURE_WORD type. Signed-off-by: Robert Hoo --- target/i386/cpu.c | 76 +++++++++++++++++++++++++++++++++++++++++----------= ---- 1 file changed, 57 insertions(+), 19 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 77e1859..51989e5 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -3024,21 +3024,50 @@ static const TypeInfo host_x86_cpu_type_info =3D { =20 #endif =20 +/* +*caller should have input str no less than 64 byte length. +*/ +#define FEATURE_WORD_DESCPTION_LEN 64 +static int feature_word_description(char str[], FeatureWordInfo *f, uint32= _t bit) +{ + int ret; + + assert(f->type =3D=3D CPUID_FEATURE_WORD || + f->type =3D=3D MSR_FEATURE_WORD); + switch (f->type) { + case CPUID_FEATURE_WORD: + { + const char *reg =3D get_register_name_32(f->cpuid.reg); + assert(reg); + ret =3D snprintf(str, FEATURE_WORD_DESCPTION_LEN, + "CPUID.%02XH:%s%s%s [bit %d]", + f->cpuid.eax, reg, + f->feat_names[bit] ? "." : "", + f->feat_names[bit] ? f->feat_names[bit] : "", bit); + break; + } + case MSR_FEATURE_WORD: + ret =3D snprintf(str, FEATURE_WORD_DESCPTION_LEN, + "MSR(%xH).%s [bit %d]", + f->msr.index, + f->feat_names[bit] ? f->feat_names[bit] : "", bit); + break; + } + return ret > 0; +} + static void report_unavailable_features(FeatureWord w, uint32_t mask) { FeatureWordInfo *f =3D &feature_word_info[w]; int i; + char feat_word_dscrp_str[FEATURE_WORD_DESCPTION_LEN]; =20 for (i =3D 0; i < 32; ++i) { if ((1UL << i) & mask) { - const char *reg =3D get_register_name_32(f->cpuid_reg); - assert(reg); - warn_report("%s doesn't support requested feature: " - "CPUID.%02XH:%s%s%s [bit %d]", + feature_word_description(feat_word_dscrp_str, f, i); + warn_report("%s doesn't support requested feature: %s", accel_uses_host_cpuid() ? "host" : "TCG", - f->cpuid_eax, reg, - f->feat_names[i] ? "." : "", - f->feat_names[i] ? f->feat_names[i] : "", i); + feat_word_dscrp_str); } } } @@ -3276,17 +3305,17 @@ static void x86_cpu_get_feature_words(Object *obj, = Visitor *v, { uint32_t *array =3D (uint32_t *)opaque; FeatureWord w; - X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] =3D { }; - X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] =3D { }; + X86CPUFeatureWordInfo word_infos[FEATURE_WORDS_NUM_CPUID] =3D { }; + X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS_NUM_CPUID] =3D { = }; X86CPUFeatureWordInfoList *list =3D NULL; =20 - for (w =3D 0; w < FEATURE_WORDS; w++) { + for (w =3D 0; w < FEATURE_WORDS_NUM_CPUID; w++) { FeatureWordInfo *wi =3D &feature_word_info[w]; X86CPUFeatureWordInfo *qwi =3D &word_infos[w]; - qwi->cpuid_input_eax =3D wi->cpuid_eax; - qwi->has_cpuid_input_ecx =3D wi->cpuid_needs_ecx; - qwi->cpuid_input_ecx =3D wi->cpuid_ecx; - qwi->cpuid_register =3D x86_reg_info_32[wi->cpuid_reg].qapi_enum; + qwi->cpuid_input_eax =3D wi->cpuid.eax; + qwi->has_cpuid_input_ecx =3D wi->cpuid.needs_ecx; + qwi->cpuid_input_ecx =3D wi->cpuid.ecx; + qwi->cpuid_register =3D x86_reg_info_32[wi->cpuid.reg].qapi_enum; qwi->features =3D array[w]; =20 /* List will be in reverse order, but order shouldn't matter */ @@ -3659,12 +3688,20 @@ static uint32_t x86_cpu_get_supported_feature_word(= FeatureWord w, bool migratable_only) { FeatureWordInfo *wi =3D &feature_word_info[w]; - uint32_t r; + uint32_t r =3D 0; =20 if (kvm_enabled()) { - r =3D kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid_eax, - wi->cpuid_ecx, - wi->cpuid_reg); + switch (wi->type) { + case CPUID_FEATURE_WORD: + r =3D kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.ea= x, + wi->cpuid.ecx, + wi->cpuid.reg); + break; + case MSR_FEATURE_WORD: + r =3D kvm_arch_get_supported_msr_feature(kvm_state, + wi->msr.index); + break; + } } else if (hvf_enabled()) { r =3D hvf_get_supported_cpuid(wi->cpuid_eax, wi->cpuid_ecx, @@ -4732,9 +4769,10 @@ static void x86_cpu_adjust_feat_level(X86CPU *cpu, F= eatureWord w) { CPUX86State *env =3D &cpu->env; FeatureWordInfo *fi =3D &feature_word_info[w]; - uint32_t eax =3D fi->cpuid_eax; + uint32_t eax =3D fi->cpuid.eax; uint32_t region =3D eax & 0xF0000000; =20 + assert(feature_word_info[w].type =3D=3D CPUID_FEATURE_WORD); if (!env->features[w]) { return; } --=20 1.8.3.1