From nobody Wed Nov 5 05:19:03 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linux.intel.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1533625317193357.217814806507; Tue, 7 Aug 2018 00:01:57 -0700 (PDT) Received: from localhost ([::1]:37639 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fmw0A-0002d9-Cy for importer@patchew.org; Tue, 07 Aug 2018 03:01:54 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49032) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fmvz8-0002HV-D0 for qemu-devel@nongnu.org; Tue, 07 Aug 2018 03:00:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fmvz5-0000EI-64 for qemu-devel@nongnu.org; Tue, 07 Aug 2018 03:00:50 -0400 Received: from mga06.intel.com ([134.134.136.31]:27906) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fmvz4-0000Di-S4 for qemu-devel@nongnu.org; Tue, 07 Aug 2018 03:00:47 -0400 Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Aug 2018 00:00:44 -0700 Received: from liujing-dell.bj.intel.com ([10.238.145.49]) by fmsmga005.fm.intel.com with ESMTP; 07 Aug 2018 00:00:42 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.51,454,1526367600"; d="scan'208";a="251937155" From: Jing Liu To: qemu-devel@nongnu.org Date: Tue, 7 Aug 2018 15:04:09 +0800 Message-Id: <1533625449-14989-1-git-send-email-jing2.liu@linux.intel.com> X-Mailer: git-send-email 1.8.3.1 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 134.134.136.31 Subject: [Qemu-devel] [PATCH] hw/pci: add pci capability to pci-pci bridge X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mst@redhat.com, jing2.liu@linux.intel.com, anthony.xu@intel.com, pbonzini@redhat.com, lersek@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add hint to firmware (e.g. SeaBIOS) to reserve addtional IO/MEM/PREF spaces for legacy pci-pci bridge, to enable some pci devices hotplugging whose IO/MEM/PREF spaces requests are larger than the ones in pci-pci bridge set by firmware. Signed-off-by: Jing Liu --- hw/pci-bridge/pci_bridge_dev.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/hw/pci-bridge/pci_bridge_dev.c b/hw/pci-bridge/pci_bridge_dev.c index b2d861d..8e9afbd 100644 --- a/hw/pci-bridge/pci_bridge_dev.c +++ b/hw/pci-bridge/pci_bridge_dev.c @@ -46,6 +46,12 @@ struct PCIBridgeDev { uint32_t flags; =20 OnOffAuto msi; + + /* additional resources to reserve on firmware init */ + uint64_t io_reserve; + uint64_t mem_reserve; + uint64_t pref32_reserve; + uint64_t pref64_reserve; }; typedef struct PCIBridgeDev PCIBridgeDev; =20 @@ -95,6 +101,13 @@ static void pci_bridge_dev_realize(PCIDevice *dev, Erro= r **errp) error_free(local_err); } =20 + err =3D pci_bridge_qemu_reserve_cap_init(dev, 0, 0, + bridge_dev->io_reserve, bridge_dev->mem_reserve, + bridge_dev->pref32_reserve, bridge_dev->pref64_reserve, errp); + if (err) { + goto cap_error; + } + if (shpc_present(dev)) { /* TODO: spec recommends using 64 bit prefetcheable BAR. * Check whether that works well. */ @@ -103,6 +116,8 @@ static void pci_bridge_dev_realize(PCIDevice *dev, Erro= r **errp) } return; =20 +cap_error: + msi_uninit(dev); msi_error: slotid_cap_cleanup(dev); slotid_error: @@ -162,6 +177,11 @@ static Property pci_bridge_dev_properties[] =3D { ON_OFF_AUTO_AUTO), DEFINE_PROP_BIT(PCI_BRIDGE_DEV_PROP_SHPC, PCIBridgeDev, flags, PCI_BRIDGE_DEV_F_SHPC_REQ, true), + DEFINE_PROP_SIZE("io-reserve", PCIBridgeDev, io_reserve, -1), + DEFINE_PROP_SIZE("mem-reserve", PCIBridgeDev, mem_reserve, -1), + DEFINE_PROP_SIZE("pref32-reserve", PCIBridgeDev, pref32_reserve, -1), + DEFINE_PROP_SIZE("pref64-reserve", PCIBridgeDev, pref64_reserve, -1), + DEFINE_PROP_END_OF_LIST(), }; =20 --=20 1.8.3.1