From nobody Wed Nov 5 08:12:26 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1533587041617690.8572150779308; Mon, 6 Aug 2018 13:24:01 -0700 (PDT) Received: from localhost ([::1]:36140 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fmm2q-0004pt-Cm for importer@patchew.org; Mon, 06 Aug 2018 16:24:00 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58486) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fmlub-0006SX-Tg for qemu-devel@nongnu.org; Mon, 06 Aug 2018 16:15:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fmlua-0006uJ-NG for qemu-devel@nongnu.org; Mon, 06 Aug 2018 16:15:29 -0400 Received: from mx3-rdu2.redhat.com ([66.187.233.73]:40544 helo=mx1.redhat.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fmluW-0006nR-Kp; Mon, 06 Aug 2018 16:15:24 -0400 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.rdu2.redhat.com [10.11.54.6]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 2627040241C4; Mon, 6 Aug 2018 20:15:24 +0000 (UTC) Received: from localhost.localdomain.com (ovpn-116-58.ams2.redhat.com [10.36.116.58]) by smtp.corp.redhat.com (Postfix) with ESMTP id 62BD62156711; Mon, 6 Aug 2018 20:15:21 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, alex.williamson@redhat.com, mst@redhat.com, jean-philippe.brucker@arm.com Date: Mon, 6 Aug 2018 22:14:38 +0200 Message-Id: <1533586484-5737-11-git-send-email-eric.auger@redhat.com> In-Reply-To: <1533586484-5737-1-git-send-email-eric.auger@redhat.com> References: <1533586484-5737-1-git-send-email-eric.auger@redhat.com> X-Scanned-By: MIMEDefang 2.78 on 10.11.54.6 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.7]); Mon, 06 Aug 2018 20:15:24 +0000 (UTC) X-Greylist: inspected by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.7]); Mon, 06 Aug 2018 20:15:24 +0000 (UTC) for IP:'10.11.54.6' DOMAIN:'int-mx06.intmail.prod.int.rdu2.redhat.com' HELO:'smtp.corp.redhat.com' FROM:'eric.auger@redhat.com' RCPT:'' X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.187.233.73 Subject: [Qemu-devel] [RFC v7 10/16] virtio-iommu: Add an msi_bypass property X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wei@redhat.com, kevin.tian@intel.com, tn@semihalf.com, will.deacon@arm.com, drjones@redhat.com, peterx@redhat.com, linuc.decode@gmail.com, bharat.bhushan@nxp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" In case the msi_bypass property is set, it means we need to register the IOAPIC MSI window as a reserved region: 0xFEE00000 - 0xFEEFFFFF. Signed-off-by: Eric Auger --- --- hw/virtio/virtio-iommu.c | 52 ++++++++++++++++++++++++++++++++++++= ++++ include/hw/virtio/virtio-iommu.h | 1 + 2 files changed, 53 insertions(+) diff --git a/hw/virtio/virtio-iommu.c b/hw/virtio/virtio-iommu.c index 0291a04..ec0cf1e 100644 --- a/hw/virtio/virtio-iommu.c +++ b/hw/virtio/virtio-iommu.c @@ -42,6 +42,9 @@ #define VIOMMU_DEFAULT_QUEUE_SIZE 256 #define VIOMMU_PROBE_SIZE 512 =20 +#define IOAPIC_RANGE_START (0xfee00000) +#define IOAPIC_RANGE_SIZE (0x100000) + #define SUPPORTED_PROBE_PROPERTIES (\ VIRTIO_IOMMU_PROBE_T_NONE | \ VIRTIO_IOMMU_PROBE_T_RESV_MEM) @@ -104,6 +107,25 @@ static void virtio_iommu_detach_endpoint_from_domain(v= iommu_endpoint *ep) ep->domain =3D NULL; } =20 +static void virtio_iommu_register_resv_region(viommu_endpoint *ep, + uint8_t subtype, + uint64_t start, uint64_t end) +{ + viommu_interval *interval; + struct virtio_iommu_probe_resv_mem *reg; + + interval =3D g_malloc0(sizeof(*interval)); + interval->low =3D start; + interval->high =3D end; + + reg =3D g_malloc0(sizeof(*reg)); + reg->subtype =3D subtype; + reg->start =3D cpu_to_le64(start); + reg->end =3D cpu_to_le64(end); + + g_tree_insert(ep->reserved_regions, interval, reg); +} + static viommu_endpoint *virtio_iommu_get_endpoint(VirtIOIOMMU *s, uint32_t ep_id) { @@ -121,6 +143,12 @@ static viommu_endpoint *virtio_iommu_get_endpoint(Virt= IOIOMMU *s, ep->reserved_regions =3D g_tree_new_full((GCompareDataFunc)interval_cm= p, NULL, (GDestroyNotify)g_free, (GDestroyNotify)g_free); + if (s->msi_bypass) { + virtio_iommu_register_resv_region(ep, VIRTIO_IOMMU_RESV_MEM_T_MSI, + IOAPIC_RANGE_START, + IOAPIC_RANGE_SIZE); + } + return ep; } =20 @@ -841,8 +869,32 @@ static void virtio_iommu_set_status(VirtIODevice *vdev= , uint8_t status) trace_virtio_iommu_device_status(status); } =20 +static bool virtio_iommu_get_msi_bypass(Object *obj, Error **errp) +{ + VirtIOIOMMU *s =3D VIRTIO_IOMMU(obj); + + return s->msi_bypass; +} + +static void virtio_iommu_set_msi_bypass(Object *obj, bool value, Error **e= rrp) +{ + VirtIOIOMMU *s =3D VIRTIO_IOMMU(obj); + + s->msi_bypass =3D value; +} + static void virtio_iommu_instance_init(Object *obj) { + VirtIOIOMMU *s =3D VIRTIO_IOMMU(obj); + + object_property_add_bool(obj, "msi_bypass", virtio_iommu_get_msi_bypas= s, + virtio_iommu_set_msi_bypass, NULL); + object_property_set_description(obj, "msi_bypass", + "Indicates whether msis are bypassed b= y " + "the IOMMU. Default is YES", + NULL); + + s->msi_bypass =3D true; } =20 static const VMStateDescription vmstate_virtio_iommu =3D { diff --git a/include/hw/virtio/virtio-iommu.h b/include/hw/virtio/virtio-io= mmu.h index 913e96b..aa20ba4 100644 --- a/include/hw/virtio/virtio-iommu.h +++ b/include/hw/virtio/virtio-iommu.h @@ -58,6 +58,7 @@ typedef struct VirtIOIOMMU { GTree *domains; QemuMutex mutex; GTree *endpoints; + bool msi_bypass; } VirtIOIOMMU; =20 #endif --=20 2.5.5