From nobody Wed Nov 5 08:33:45 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1533575554293175.7518811027261; Mon, 6 Aug 2018 10:12:34 -0700 (PDT) Received: from localhost ([::1]:35220 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fmj3Z-0002u3-45 for importer@patchew.org; Mon, 06 Aug 2018 13:12:33 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54217) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fmiyJ-0006YT-0h for qemu-devel@nongnu.org; Mon, 06 Aug 2018 13:07:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fmiyG-0007Lv-5n for qemu-devel@nongnu.org; Mon, 06 Aug 2018 13:07:06 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:46448 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fmiyF-0007L1-KW for qemu-devel@nongnu.org; Mon, 06 Aug 2018 13:07:04 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 5770C1A209F; Mon, 6 Aug 2018 19:07:02 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 24C651A209A; Mon, 6 Aug 2018 19:07:02 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Mon, 6 Aug 2018 18:59:42 +0200 Message-Id: <1533574847-19294-16-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1533574847-19294-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1533574847-19294-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v7 15/80] target/mips: Add nanoMIPS base instruction set opcodes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, thuth@redhat.com, pburton@wavecomp.com, smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, armbru@redhat.com, arikalo@wavecomp.com, philippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Yongbok Kim Add nanoMIPS opcodes. nanoMIPS instruction are organized by so-called instruction pools. Each pool contains a set of opcodes, that in turn can be instruction opcodes or instruction pool opcodes. Reviewed-by: Richard Henderson Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic --- target/mips/translate.c | 670 ++++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 670 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index bc1f21f..bbe8b8a 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -15656,6 +15656,676 @@ static int decode_micromips_opc (CPUMIPSState *en= v, DisasContext *ctx) return 2; } =20 +/* + * + * nanoMIPS opcodes + * + */ + +/* MAJOR, P16, and P32 pools opcodes */ +enum { + NM_P_ADDIU =3D 0x00, + NM_ADDIUPC =3D 0x01, + NM_MOVE_BALC =3D 0x02, + NM_P16_MV =3D 0x04, + NM_LW16 =3D 0x05, + NM_BC16 =3D 0x06, + NM_P16_SR =3D 0x07, + + NM_POOL32A =3D 0x08, + NM_P_BAL =3D 0x0a, + NM_P16_SHIFT =3D 0x0c, + NM_LWSP16 =3D 0x0d, + NM_BALC16 =3D 0x0e, + NM_P16_4X4 =3D 0x0f, + + NM_P_GP_W =3D 0x10, + NM_P_GP_BH =3D 0x11, + NM_P_J =3D 0x12, + NM_P16C =3D 0x14, + NM_LWGP16 =3D 0x15, + NM_P16_LB =3D 0x17, + + NM_P48I =3D 0x18, + NM_P16_A1 =3D 0x1c, + NM_LW4X4 =3D 0x1d, + NM_P16_LH =3D 0x1f, + + NM_P_U12 =3D 0x20, + NM_P_LS_U12 =3D 0x21, + NM_P_BR1 =3D 0x22, + NM_P16_A2 =3D 0x24, + NM_SW16 =3D 0x25, + NM_BEQZC16 =3D 0x26, + + NM_POOL32F =3D 0x28, + NM_P_LS_S9 =3D 0x29, + NM_P_BR2 =3D 0x2a, + + NM_P16_ADDU =3D 0x2c, + NM_SWSP16 =3D 0x2d, + NM_BNEZC16 =3D 0x2e, + NM_MOVEP =3D 0x2f, + + NM_POOL32S =3D 0x30, + NM_P_BRI =3D 0x32, + NM_LI16 =3D 0x34, + NM_SWGP16 =3D 0x35, + NM_P16_BR =3D 0x36, + + NM_P_LUI =3D 0x38, + NM_ANDI16 =3D 0x3c, + NM_SW4X4 =3D 0x3d, + NM_MOVEPREV =3D 0x3f, +}; + +/* POOL32A instruction pool */ +enum { + NM_POOL32A0 =3D 0x00, + NM_SPECIAL2 =3D 0x01, + NM_COP2_1 =3D 0x02, + NM_UDI =3D 0x03, + NM_POOL32A5 =3D 0x05, + NM_POOL32A7 =3D 0x07, +}; + +/* P.GP.W instruction pool */ +enum { + NM_ADDIUGP_W =3D 0x00, + NM_LWGP =3D 0x02, + NM_SWGP =3D 0x03, +}; + +/* P48I instruction pool */ +enum { + NM_LI48 =3D 0x00, + NM_ADDIU48 =3D 0x01, + NM_ADDIUGP48 =3D 0x02, + NM_ADDIUPC48 =3D 0x03, + NM_LWPC48 =3D 0x0b, + NM_SWPC48 =3D 0x0f, +}; + +/* P.U12 instruction pool */ +enum { + NM_ORI =3D 0x00, + NM_XORI =3D 0x01, + NM_ANDI =3D 0x02, + NM_P_SR =3D 0x03, + NM_SLTI =3D 0x04, + NM_SLTIU =3D 0x05, + NM_SEQI =3D 0x06, + NM_ADDIUNEG =3D 0x08, + NM_P_SHIFT =3D 0x0c, + NM_P_ROTX =3D 0x0d, + NM_P_INS =3D 0x0e, + NM_P_EXT =3D 0x0f, +}; + +/* POOL32F instruction pool */ +enum { + NM_POOL32F_0 =3D 0x00, + NM_POOL32F_3 =3D 0x03, + NM_POOL32F_5 =3D 0x05, +}; + +/* POOL32S instruction pool */ +enum { + NM_POOL32S_0 =3D 0x00, + NM_POOL32S_4 =3D 0x04, +}; + +/* P.LUI instruction pool */ +enum { + NM_LUI =3D 0x00, + NM_ALUIPC =3D 0x01, +}; + +/* P.GP.BH instruction pool */ +enum { + NM_LBGP =3D 0x00, + NM_SBGP =3D 0x01, + NM_LBUGP =3D 0x02, + NM_ADDIUGP_B =3D 0x03, + NM_P_GP_LH =3D 0x04, + NM_P_GP_SH =3D 0x05, + NM_P_GP_CP1 =3D 0x06, +}; + +/* P.LS.U12 instruction pool */ +enum { + NM_LB =3D 0x00, + NM_SB =3D 0x01, + NM_LBU =3D 0x02, + NM_P_PREFU12 =3D 0x03, + NM_LH =3D 0x04, + NM_SH =3D 0x05, + NM_LHU =3D 0x06, + NM_LWU =3D 0x07, + NM_LW =3D 0x08, + NM_SW =3D 0x09, + NM_LWC1 =3D 0x0a, + NM_SWC1 =3D 0x0b, + NM_LDC1 =3D 0x0e, + NM_SDC1 =3D 0x0f, +}; + +/* P.LS.S9 instruction pool */ +enum { + NM_P_LS_S0 =3D 0x00, + NM_P_LS_S1 =3D 0x01, + NM_P_LS_E0 =3D 0x02, + NM_P_LS_WM =3D 0x04, + NM_P_LS_UAWM =3D 0x05, +}; + +/* P.BAL instruction pool */ +enum { + NM_BC =3D 0x00, + NM_BALC =3D 0x01, +}; + +/* P.J instruction pool */ +enum { + NM_JALRC =3D 0x00, + NM_JALRC_HB =3D 0x01, + NM_P_BALRSC =3D 0x08, +}; + +/* P.BR1 instruction pool */ +enum { + NM_BEQC =3D 0x00, + NM_P_BR3A =3D 0x01, + NM_BGEC =3D 0x02, + NM_BGEUC =3D 0x03, +}; + +/* P.BR2 instruction pool */ +enum { + NM_BNEC =3D 0x00, + NM_BLTC =3D 0x02, + NM_BLTUC =3D 0x03, +}; + +/* P.BRI instruction pool */ +enum { + NM_BEQIC =3D 0x00, + NM_BBEQZC =3D 0x01, + NM_BGEIC =3D 0x02, + NM_BGEIUC =3D 0x03, + NM_BNEIC =3D 0x04, + NM_BBNEZC =3D 0x05, + NM_BLTIC =3D 0x06, + NM_BLTIUC =3D 0x07, +}; + +/* P16.SHIFT instruction pool */ +enum { + NM_SLL16 =3D 0x00, + NM_SRL16 =3D 0x01, +}; + +/* POOL16C instruction pool */ +enum { + NM_POOL16C_0 =3D 0x00, + NM_LWXS16 =3D 0x01, +}; + +/* P16.A1 instruction pool */ +enum { + NM_ADDIUR1SP =3D 0x01, +}; + +/* P16.A2 instruction pool */ +enum { + NM_ADDIUR2 =3D 0x00, + NM_P_ADDIURS5 =3D 0x01, +}; + +/* P16.ADDU instruction pool */ +enum { + NM_ADDU16 =3D 0x00, + NM_SUBU16 =3D 0x01, +}; + +/* P16.SR instruction pool */ +enum { + NM_SAVE16 =3D 0x00, + NM_RESTORE_JRC16 =3D 0x01, +}; + +/* P16.4X4 instruction pool */ +enum { + NM_ADDU4X4 =3D 0x00, + NM_MUL4X4 =3D 0x01, +}; + +/* P16.LB instruction pool */ +enum { + NM_LB16 =3D 0x00, + NM_SB16 =3D 0x01, + NM_LBU16 =3D 0x02, +}; + +/* P16.LH instruction pool */ +enum { + NM_LH16 =3D 0x00, + NM_SH16 =3D 0x01, + NM_LHU16 =3D 0x02, +}; + +/* P.RI instruction pool */ +enum { + NM_SIGRIE =3D 0x00, + NM_P_SYSCALL =3D 0x01, + NM_BREAK =3D 0x02, + NM_SDBBP =3D 0x03, +}; + +/* POOL32A0 instruction pool */ +enum { + NM_P_TRAP =3D 0x00, + NM_SEB =3D 0x01, + NM_SLLV =3D 0x02, + NM_MUL =3D 0x03, + NM_MFC0 =3D 0x06, + NM_MFHC0 =3D 0x07, + NM_SEH =3D 0x09, + NM_SRLV =3D 0x0a, + NM_MUH =3D 0x0b, + NM_MTC0 =3D 0x0e, + NM_MTHC0 =3D 0x0f, + NM_SRAV =3D 0x12, + NM_MULU =3D 0x13, + NM_ROTRV =3D 0x1a, + NM_MUHU =3D 0x1b, + NM_ADD =3D 0x22, + NM_DIV =3D 0x23, + NM_ADDU =3D 0x2a, + NM_MOD =3D 0x2b, + NM_SUB =3D 0x32, + NM_DIVU =3D 0x33, + NM_RDHWR =3D 0x38, + NM_SUBU =3D 0x3a, + NM_MODU =3D 0x3b, + NM_P_CMOVE =3D 0x42, + NM_FORK =3D 0x45, + NM_MFTR =3D 0x46, + NM_MFHTR =3D 0x47, + NM_AND =3D 0x4a, + NM_YIELD =3D 0x4d, + NM_MTTR =3D 0x4e, + NM_MTHTR =3D 0x4f, + NM_OR =3D 0x52, + NM_D_E_MT_VPE =3D 0x56, + NM_NOR =3D 0x5a, + NM_XOR =3D 0x62, + NM_SLT =3D 0x6a, + NM_P_SLTU =3D 0x72, + NM_SOV =3D 0x7a, +}; + +/* POOL32A7 instruction pool */ +enum { + NM_P_LSX =3D 0x00, + NM_LSA =3D 0x01, + NM_EXTW =3D 0x03, + NM_POOL32AXF =3D 0x07, +}; + +/* P.SR instruction pool */ +enum { + NM_PP_SR =3D 0x00, + NM_P_SR_F =3D 0x01, +}; + +/* P.SHIFT instruction pool */ +enum { + NM_P_SLL =3D 0x00, + NM_SRL =3D 0x02, + NM_SRA =3D 0x04, + NM_ROTR =3D 0x06, +}; + +/* P.ROTX instruction pool */ +enum { + NM_ROTX =3D 0x00, +}; + +/* P.INS instruction pool */ +enum { + NM_INS =3D 0x00, +}; + +/* P.EXT instruction pool */ +enum { + NM_EXT =3D 0x00, +}; + +/* POOL32F_0 (fmt) instruction pool */ +enum { + NM_RINT_S =3D 0x04, + NM_RINT_D =3D 0x44, + NM_ADD_S =3D 0x06, + NM_SELEQZ_S =3D 0x07, + NM_SELEQZ_D =3D 0x47, + NM_CLASS_S =3D 0x0c, + NM_CLASS_D =3D 0x4c, + NM_SUB_S =3D 0x0e, + NM_SELNEZ_S =3D 0x0f, + NM_SELNEZ_D =3D 0x4f, + NM_MUL_S =3D 0x16, + NM_SEL_S =3D 0x17, + NM_SEL_D =3D 0x57, + NM_DIV_S =3D 0x1e, + NM_ADD_D =3D 0x26, + NM_SUB_D =3D 0x2e, + NM_MUL_D =3D 0x36, + NM_MADDF_S =3D 0x37, + NM_MADDF_D =3D 0x77, + NM_DIV_D =3D 0x3e, + NM_MSUBF_S =3D 0x3f, + NM_MSUBF_D =3D 0x7f, +}; + +/* POOL32F_3 instruction pool */ +enum { + NM_MIN_FMT =3D 0x00, + NM_MAX_FMT =3D 0x01, + NM_MINA_FMT =3D 0x04, + NM_MAXA_FMT =3D 0x05, + NM_POOL32FXF =3D 0x07, +}; + +/* POOL32F_5 instruction pool */ +enum { + NM_CMP_CONDN_S =3D 0x00, + NM_CMP_CONDN_D =3D 0x02, +}; + +/* P.GP.LH instruction pool */ +enum { + NM_LHGP =3D 0x00, + NM_LHUGP =3D 0x01, +}; + +/* P.GP.SH instruction pool */ +enum { + NM_SHGP =3D 0x00, +}; + +/* P.GP.CP1 instruction pool */ +enum { + NM_LWC1GP =3D 0x00, + NM_SWC1GP =3D 0x01, + NM_LDC1GP =3D 0x02, + NM_SDC1GP =3D 0x03, +}; + +/* P.LS.S0 instruction pool */ +enum { + NM_LBS9 =3D 0x00, + NM_LHS9 =3D 0x04, + NM_LWS9 =3D 0x08, + NM_LDS9 =3D 0x0c, + + NM_SBS9 =3D 0x01, + NM_SHS9 =3D 0x05, + NM_SWS9 =3D 0x09, + NM_SDS9 =3D 0x0d, + + NM_LBUS9 =3D 0x02, + NM_LHUS9 =3D 0x06, + NM_LWC1S9 =3D 0x0a, + NM_LDC1S9 =3D 0x0e, + + NM_P_PREFS9 =3D 0x03, + NM_LWUS9 =3D 0x07, + NM_SWC1S9 =3D 0x0b, + NM_SDC1S9 =3D 0x0f, +}; + +/* P.LS.S1 instruction pool */ +enum { + NM_ASET_ACLR =3D 0x02, + NM_UALH =3D 0x04, + NM_UASH =3D 0x05, + NM_CACHE =3D 0x07, + NM_P_LL =3D 0x0a, + NM_P_SC =3D 0x0b, +}; + +/* P.LS.WM instruction pool */ +enum { + NM_LWM =3D 0x00, + NM_SWM =3D 0x01, +}; + +/* P.LS.UAWM instruction pool */ +enum { + NM_UALWM =3D 0x00, + NM_UASWM =3D 0x01, +}; + +/* P.BR3A instruction pool */ +enum { + NM_BC1EQZC =3D 0x00, + NM_BC1NEZC =3D 0x01, + NM_BC2EQZC =3D 0x02, + NM_BC2NEZC =3D 0x03, + NM_BPOSGE32C =3D 0x04, +}; + +/* P16.RI instruction pool */ +enum { + NM_P16_SYSCALL =3D 0x01, + NM_BREAK16 =3D 0x02, + NM_SDBBP16 =3D 0x03, +}; + +/* POOL16C_0 instruction pool */ +enum { + NM_POOL16C_00 =3D 0x00, +}; + +/* P16.JRC instruction pool */ +enum { + NM_JRC =3D 0x00, + NM_JALRC16 =3D 0x01, +}; + +/* P.SYSCALL instruction pool */ +enum { + NM_SYSCALL =3D 0x00, + NM_HYPCALL =3D 0x01, +}; + +/* P.TRAP instruction pool */ +enum { + NM_TEQ =3D 0x00, + NM_TNE =3D 0x01, +}; + +/* P.CMOVE instruction pool */ +enum { + NM_MOVZ =3D 0x00, + NM_MOVN =3D 0x01, +}; + +/* POOL32Axf instruction pool */ +enum { + NM_POOL32AXF_4 =3D 0x04, + NM_POOL32AXF_5 =3D 0x05, +}; + +/* POOL32Axf_{4, 5} instruction pool */ +enum { + NM_CLO =3D 0x25, + NM_CLZ =3D 0x2d, + + NM_TLBP =3D 0x01, + NM_TLBR =3D 0x09, + NM_TLBWI =3D 0x11, + NM_TLBWR =3D 0x19, + NM_TLBINV =3D 0x03, + NM_TLBINVF =3D 0x0b, + NM_DI =3D 0x23, + NM_EI =3D 0x2b, + NM_RDPGPR =3D 0x70, + NM_WRPGPR =3D 0x78, + NM_WAIT =3D 0x61, + NM_DERET =3D 0x71, + NM_ERETX =3D 0x79, +}; + +/* PP.SR instruction pool */ +enum { + NM_SAVE =3D 0x00, + NM_RESTORE =3D 0x02, + NM_RESTORE_JRC =3D 0x03, +}; + +/* P.SR.F instruction pool */ +enum { + NM_SAVEF =3D 0x00, + NM_RESTOREF =3D 0x01, +}; + +/* P16.SYSCALL instruction pool */ +enum { + NM_SYSCALL16 =3D 0x00, + NM_HYPCALL16 =3D 0x01, +}; + +/* POOL16C_00 instruction pool */ +enum { + NM_NOT16 =3D 0x00, + NM_XOR16 =3D 0x01, + NM_AND16 =3D 0x02, + NM_OR16 =3D 0x03, +}; + +/* PP.LSX and PP.LSXS instruction pool */ +enum { + NM_LBX =3D 0x00, + NM_LHX =3D 0x04, + NM_LWX =3D 0x08, + NM_LDX =3D 0x0c, + + NM_SBX =3D 0x01, + NM_SHX =3D 0x05, + NM_SWX =3D 0x09, + NM_SDX =3D 0x0d, + + NM_LBUX =3D 0x02, + NM_LHUX =3D 0x06, + NM_LWC1X =3D 0x0a, + NM_LDC1X =3D 0x0e, + + NM_LWUX =3D 0x07, + NM_SWC1X =3D 0x0b, + NM_SDC1X =3D 0x0f, + + NM_LHXS =3D 0x04, + NM_LWXS =3D 0x08, + NM_LDXS =3D 0x0c, + + NM_SHXS =3D 0x05, + NM_SWXS =3D 0x09, + NM_SDXS =3D 0x0d, + + NM_LHUXS =3D 0x06, + NM_LWC1XS =3D 0x0a, + NM_LDC1XS =3D 0x0e, + + NM_LWUXS =3D 0x07, + NM_SWC1XS =3D 0x0b, + NM_SDC1XS =3D 0x0f, +}; + +/* ERETx instruction pool */ +enum { + NM_ERET =3D 0x00, + NM_ERETNC =3D 0x01, +}; + +/* POOL32FxF_{0, 1} insturction pool */ +enum { + NM_CFC1 =3D 0x40, + NM_CTC1 =3D 0x60, + NM_MFC1 =3D 0x80, + NM_MTC1 =3D 0xa0, + NM_MFHC1 =3D 0xc0, + NM_MTHC1 =3D 0xe0, + + NM_CVT_S_PL =3D 0x84, + NM_CVT_S_PU =3D 0xa4, + + NM_CVT_L_S =3D 0x004, + NM_CVT_L_D =3D 0x104, + NM_CVT_W_S =3D 0x024, + NM_CVT_W_D =3D 0x124, + + NM_RSQRT_S =3D 0x008, + NM_RSQRT_D =3D 0x108, + + NM_SQRT_S =3D 0x028, + NM_SQRT_D =3D 0x128, + + NM_RECIP_S =3D 0x048, + NM_RECIP_D =3D 0x148, + + NM_FLOOR_L_S =3D 0x00c, + NM_FLOOR_L_D =3D 0x10c, + + NM_FLOOR_W_S =3D 0x02c, + NM_FLOOR_W_D =3D 0x12c, + + NM_CEIL_L_S =3D 0x04c, + NM_CEIL_L_D =3D 0x14c, + NM_CEIL_W_S =3D 0x06c, + NM_CEIL_W_D =3D 0x16c, + NM_TRUNC_L_S =3D 0x08c, + NM_TRUNC_L_D =3D 0x18c, + NM_TRUNC_W_S =3D 0x0ac, + NM_TRUNC_W_D =3D 0x1ac, + NM_ROUND_L_S =3D 0x0cc, + NM_ROUND_L_D =3D 0x1cc, + NM_ROUND_W_S =3D 0x0ec, + NM_ROUND_W_D =3D 0x1ec, + + NM_MOV_S =3D 0x01, + NM_MOV_D =3D 0x81, + NM_ABS_S =3D 0x0d, + NM_ABS_D =3D 0x8d, + NM_NEG_S =3D 0x2d, + NM_NEG_D =3D 0xad, + NM_CVT_D_S =3D 0x04d, + NM_CVT_D_W =3D 0x0cd, + NM_CVT_D_L =3D 0x14d, + NM_CVT_S_D =3D 0x06d, + NM_CVT_S_W =3D 0x0ed, + NM_CVT_S_L =3D 0x16d, +}; + +/* P.LL instruction pool */ +enum { + NM_LL =3D 0x00, + NM_LLWP =3D 0x01, +}; + +/* P.SC instruction pool */ +enum { + NM_SC =3D 0x00, + NM_SCWP =3D 0x01, +}; + +/* P.DVP instruction pool */ +enum { + NM_DVP =3D 0x00, + NM_EVP =3D 0x01, +}; + /* SmartMIPS extension to MIPS32 */ =20 #if defined(TARGET_MIPS64) --=20 2.7.4