From nobody Wed Nov 5 08:16:05 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1533221779366872.11267764643; Thu, 2 Aug 2018 07:56:19 -0700 (PDT) Received: from localhost ([::1]:46096 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1flF1W-0008G5-5r for importer@patchew.org; Thu, 02 Aug 2018 10:56:18 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60568) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1flEh5-0006iW-VX for qemu-devel@nongnu.org; Thu, 02 Aug 2018 10:35:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1flEh3-0008Es-Cq for qemu-devel@nongnu.org; Thu, 02 Aug 2018 10:35:11 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:39177 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1flEh3-0008Dw-4t for qemu-devel@nongnu.org; Thu, 02 Aug 2018 10:35:09 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id CE8871A210E; Thu, 2 Aug 2018 16:35:07 +0200 (CEST) Received: from smarkovic.domain.local (smarkovic.domain.local [10.10.14.46]) by mail.rt-rk.com (Postfix) with ESMTPSA id 9F53A1A45C5; Thu, 2 Aug 2018 16:35:07 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Stefan Markovic To: qemu-devel@nongnu.org Date: Thu, 2 Aug 2018 16:16:31 +0200 Message-Id: <1533219424-7627-45-git-send-email-stefan.markovic@rt-rk.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1533219424-7627-1-git-send-email-stefan.markovic@rt-rk.com> References: <1533219424-7627-1-git-send-email-stefan.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v6 44/77] target/mips: Add handling of branch delay slots for nanoMIPS X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pburton@wavecomp.com, smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, arikalo@wavecomp.com, philippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Matthew Fortune ISA mode bit (LSB of address) is no longer required but is also masked to allow for tools transition. The flag has_isa_mode has the key role in the implementation. Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic --- target/mips/translate.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 7e495d2..8da3fb5 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1458,6 +1458,7 @@ typedef struct DisasContext { bool mrp; bool nan2008; bool abs2008; + bool has_isa_mode; } DisasContext; =20 #define DISAS_STOP DISAS_TARGET_0 @@ -4550,7 +4551,7 @@ static void gen_compute_branch (DisasContext *ctx, ui= nt32_t opc, =20 if (blink > 0) { int post_delay =3D insn_bytes + delayslot_size; - int lowbit =3D !!(ctx->hflags & MIPS_HFLAG_M16); + int lowbit =3D ctx->has_isa_mode && !!(ctx->hflags & MIPS_HFLAG_M1= 6); =20 tcg_gen_movi_tl(cpu_gpr[blink], ctx->base.pc_next + post_delay + lowbit); @@ -11039,7 +11040,7 @@ static void gen_compute_compact_branch(DisasContext= *ctx, uint32_t opc, int bcond_compute =3D 0; TCGv t0 =3D tcg_temp_new(); TCGv t1 =3D tcg_temp_new(); - int m16_lowbit =3D (ctx->hflags & MIPS_HFLAG_M16) !=3D 0; + int m16_lowbit =3D ctx->has_isa_mode && ((ctx->hflags & MIPS_HFLAG_M16= ) !=3D 0); =20 if (ctx->hflags & MIPS_HFLAG_BMASK) { #ifdef MIPS_DEBUG_DISAS @@ -24756,6 +24757,7 @@ static void mips_tr_init_disas_context(DisasContext= Base *dcbase, CPUState *cs) ctx->mrp =3D (env->CP0_Config5 >> CP0C5_MRP) & 1; ctx->nan2008 =3D (env->active_fpu.fcr31 >> FCR31_NAN2008) & 1; ctx->abs2008 =3D (env->active_fpu.fcr31 >> FCR31_ABS2008) & 1; + ctx->has_isa_mode =3D ((env->CP0_Config3 >> CP0C3_MMAR) & 0x7) < 3; restore_cpu_state(env, ctx); #ifdef CONFIG_USER_ONLY ctx->mem_idx =3D MIPS_HFLAG_UM; --=20 1.9.1