From nobody Wed Nov 5 08:16:06 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1533221214317137.77416374518202; Thu, 2 Aug 2018 07:46:54 -0700 (PDT) Received: from localhost ([::1]:46049 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1flEsM-0000Nr-3m for importer@patchew.org; Thu, 02 Aug 2018 10:46:50 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59825) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1flEeZ-0004g1-IE for qemu-devel@nongnu.org; Thu, 02 Aug 2018 10:32:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1flEeY-0005lF-5k for qemu-devel@nongnu.org; Thu, 02 Aug 2018 10:32:35 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:35341 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1flEeX-0005kA-Ra for qemu-devel@nongnu.org; Thu, 02 Aug 2018 10:32:34 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 17C101A1E0F; Thu, 2 Aug 2018 16:32:32 +0200 (CEST) Received: from smarkovic.domain.local (smarkovic.domain.local [10.10.14.46]) by mail.rt-rk.com (Postfix) with ESMTPSA id EDCC41A1D19; Thu, 2 Aug 2018 16:32:31 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Stefan Markovic To: qemu-devel@nongnu.org Date: Thu, 2 Aug 2018 16:16:24 +0200 Message-Id: <1533219424-7627-38-git-send-email-stefan.markovic@rt-rk.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1533219424-7627-1-git-send-email-stefan.markovic@rt-rk.com> References: <1533219424-7627-1-git-send-email-stefan.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v6 37/77] target/mips: Implement MT ASE support for nanoMIPS X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pburton@wavecomp.com, smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, arikalo@wavecomp.com, philippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Stefan Markovic Add emulation of MT ASE instructions for nanoMIPS. Reviewed-by: Richard Henderson Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic --- target/mips/translate.c | 85 +++++++++++++++++++++++++++++++++++++++++++++= ++-- 1 file changed, 83 insertions(+), 2 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index f728790..6d17b8b 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -16613,7 +16613,7 @@ static void gen_pool16c_nanomips_insn(DisasContext = *ctx) } } =20 -static void gen_pool32a0_nanomips_insn(DisasContext *ctx) +static void gen_pool32a0_nanomips_insn(CPUMIPSState *env, DisasContext *ct= x) { int rt =3D extract32(ctx->opcode, 21, 5); int rs =3D extract32(ctx->opcode, 16, 5); @@ -16781,6 +16781,87 @@ static void gen_pool32a0_nanomips_insn(DisasContex= t *ctx) tcg_temp_free(t0); } break; + case NM_D_E_MT_VPE: + { + uint8_t sc =3D extract32(ctx->opcode, 10, 1); + TCGv t0 =3D tcg_temp_new(); + + switch (sc) { + case 0: + if (rs =3D=3D 1) { + /* DMT */ + check_insn(ctx, ASE_MT); + gen_helper_dmt(t0); + gen_store_gpr(t0, rt); + } else if (rs =3D=3D 0) { + /* DVPE */ + check_insn(ctx, ASE_MT); + gen_helper_dvpe(t0, cpu_env); + gen_store_gpr(t0, rt); + } else { + generate_exception_end(ctx, EXCP_RI); + } + break; + case 1: + if (rs =3D=3D 1) { + /* EMT */ + check_insn(ctx, ASE_MT); + gen_helper_emt(t0); + gen_store_gpr(t0, rt); + } else if (rs =3D=3D 0) { + /* EVPE */ + check_insn(ctx, ASE_MT); + gen_helper_evpe(t0, cpu_env); + gen_store_gpr(t0, rt); + } else { + generate_exception_end(ctx, EXCP_RI); + } + break; + } + + tcg_temp_free(t0); + } + break; + case NM_FORK: + check_insn(ctx, ASE_MT); + { + TCGv t0 =3D tcg_temp_new(); + TCGv t1 =3D tcg_temp_new(); + + gen_load_gpr(t0, rt); + gen_load_gpr(t1, rs); + gen_helper_fork(t0, t1); + tcg_temp_free(t0); + tcg_temp_free(t1); + } + break; + case NM_MFTR: + case NM_MFHTR: + check_insn(ctx, ASE_MT); + if (rd =3D=3D 0) { + /* Treat as NOP. */ + return; + } + gen_mftr(env, ctx, rs, rt, extract32(ctx->opcode, 10, 1), + extract32(ctx->opcode, 11, 5), extract32(ctx->opcode, 3, = 1)); + break; + case NM_MTTR: + case NM_MTHTR: + check_insn(ctx, ASE_MT); + gen_mttr(env, ctx, rs, rt, extract32(ctx->opcode, 10, 1), + extract32(ctx->opcode, 11, 5), extract32(ctx->opcode, 3, = 1)); + break; + case NM_YIELD: + check_insn(ctx, ASE_MT); + { + TCGv t0 =3D tcg_temp_new(); + + gen_load_gpr(t0, rs); + gen_helper_yield(t0, cpu_env, t0); + gen_store_gpr(t0, rt); + tcg_temp_free(t0); + } + break; #endif default: generate_exception_end(ctx, EXCP_RI); @@ -17504,7 +17585,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *= env, DisasContext *ctx) case NM_POOL32A: switch (ctx->opcode & 0x07) { case NM_POOL32A0: - gen_pool32a0_nanomips_insn(ctx); + gen_pool32a0_nanomips_insn(env, ctx); break; case NM_POOL32A7: switch (extract32(ctx->opcode, 3, 3)) { --=20 1.9.1