From nobody Wed Nov 5 08:20:08 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1533221059614984.676663114319; Thu, 2 Aug 2018 07:44:19 -0700 (PDT) Received: from localhost ([::1]:46026 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1flEpu-00069I-9j for importer@patchew.org; Thu, 02 Aug 2018 10:44:18 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59595) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1flEe6-0004G0-DM for qemu-devel@nongnu.org; Thu, 02 Aug 2018 10:32:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1flEe4-0005R1-Tg for qemu-devel@nongnu.org; Thu, 02 Aug 2018 10:32:06 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:34793 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1flEe4-0005Ps-H0 for qemu-devel@nongnu.org; Thu, 02 Aug 2018 10:32:04 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 51B5A1A202A; Thu, 2 Aug 2018 16:32:03 +0200 (CEST) Received: from smarkovic.domain.local (smarkovic.domain.local [10.10.14.46]) by mail.rt-rk.com (Postfix) with ESMTPSA id 327271A1E0F; Thu, 2 Aug 2018 16:32:03 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Stefan Markovic To: qemu-devel@nongnu.org Date: Thu, 2 Aug 2018 16:16:23 +0200 Message-Id: <1533219424-7627-37-git-send-email-stefan.markovic@rt-rk.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1533219424-7627-1-git-send-email-stefan.markovic@rt-rk.com> References: <1533219424-7627-1-git-send-email-stefan.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v6 36/77] target/mips: Add emulation of nanoMIPS 32-bit branch instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pburton@wavecomp.com, smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, arikalo@wavecomp.com, philippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Yongbok Kim Add emulation of various flavors of nanoMIPS 32-bit branch instructions. Reviewed-by: Aleksandar Markovic Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic --- target/mips/translate.c | 262 ++++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 262 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index 287b7fa..f728790 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -16869,6 +16869,155 @@ static void gen_pool32axf_nanomips_insn(CPUMIPSSt= ate *env, DisasContext *ctx) } } =20 +/* Immediate Value Compact Branches */ +static void gen_compute_imm_branch(DisasContext *ctx, uint32_t opc, + int rt, int32_t imm, int32_t offset) +{ + TCGCond cond; + int bcond_compute =3D 0; + TCGv t0 =3D tcg_temp_new(); + TCGv t1 =3D tcg_temp_new(); + + if (ctx->hflags & MIPS_HFLAG_BMASK) { +#ifdef MIPS_DEBUG_DISAS + LOG_DISAS("Branch in delay / forbidden slot at PC 0x" TARGET_FMT_lx + "\n", ctx->base.pc_next); +#endif + generate_exception_end(ctx, EXCP_RI); + goto out; + } + + gen_load_gpr(t0, rt); + tcg_gen_movi_tl(t1, imm); + ctx->btarget =3D addr_add(ctx, ctx->base.pc_next + 4, offset); + + /* Load needed operands and calculate btarget */ + switch (opc) { + case NM_BEQIC: + if (rt =3D=3D 0 && imm =3D=3D 0) { + /* Unconditional branch */ + } else if (rt =3D=3D 0 && imm !=3D 0) { + /* Treat as NOP */ + goto out; + } else { + bcond_compute =3D 1; + cond =3D TCG_COND_EQ; + } + break; + case NM_BBEQZC: + case NM_BBNEZC: + if (imm >=3D 32 && !(ctx->hflags & MIPS_HFLAG_64)) { + generate_exception_end(ctx, EXCP_RI); + goto out; + } else if (rt =3D=3D 0 && opc =3D=3D NM_BBEQZC) { + /* Unconditional branch */ + } else if (rt =3D=3D 0 && opc =3D=3D NM_BBNEZC) { + /* Treat as NOP */ + goto out; + } else { + tcg_gen_shri_tl(t0, t0, imm); + tcg_gen_andi_tl(t0, t0, 1); + tcg_gen_movi_tl(t1, 0); + bcond_compute =3D 1; + if (opc =3D=3D NM_BBEQZC) { + cond =3D TCG_COND_EQ; + } else { + cond =3D TCG_COND_NE; + } + } + break; + case NM_BNEIC: + if (rt =3D=3D 0 && imm =3D=3D 0) { + /* Treat as NOP */ + goto out; + } else if (rt =3D=3D 0 && imm !=3D 0) { + /* Unconditional branch */ + } else { + bcond_compute =3D 1; + cond =3D TCG_COND_NE; + } + break; + case NM_BGEIC: + if (rt =3D=3D 0 && imm =3D=3D 0) { + /* Unconditional branch */ + } else { + bcond_compute =3D 1; + cond =3D TCG_COND_GE; + } + break; + case NM_BLTIC: + bcond_compute =3D 1; + cond =3D TCG_COND_LT; + break; + case NM_BGEIUC: + if (rt =3D=3D 0 && imm =3D=3D 0) { + /* Unconditional branch */ + } else { + bcond_compute =3D 1; + cond =3D TCG_COND_GEU; + } + break; + case NM_BLTIUC: + bcond_compute =3D 1; + cond =3D TCG_COND_LTU; + break; + default: + MIPS_INVAL("Immediate Value Compact branch"); + generate_exception_end(ctx, EXCP_RI); + goto out; + } + + if (bcond_compute =3D=3D 0) { + /* Uncoditional compact branch */ + ctx->hflags |=3D MIPS_HFLAG_B; + /* Generating branch here as compact branches don't have delay slo= t */ + gen_branch(ctx, 4); + } else { + /* Conditional compact branch */ + TCGLabel *fs =3D gen_new_label(); + save_cpu_state(ctx, 0); + + tcg_gen_brcond_tl(tcg_invert_cond(cond), t0, t1, fs); + + /* Generating branch here as compact branches don't have delay slo= t */ + gen_goto_tb(ctx, 1, ctx->btarget); + gen_set_label(fs); + + ctx->hflags |=3D MIPS_HFLAG_FBNSLOT; + } + +out: + tcg_temp_free(t0); + tcg_temp_free(t1); +} + +/* P.BALRSC type nanoMIPS R6 branches: BALRSC and BRSC */ +static void gen_compute_nanomips_pbalrsc_branch(DisasContext *ctx, int rs, + int rt) +{ + TCGv t0 =3D tcg_temp_new(); + TCGv t1 =3D tcg_temp_new(); + + /* load rs */ + gen_load_gpr(t0, rs); + + /* link */ + if (rt !=3D 0) { + tcg_gen_movi_tl(cpu_gpr[rt], ctx->base.pc_next + 4); + } + + /* calculate btarget */ + tcg_gen_shli_tl(t0, t0, 1); + tcg_gen_movi_tl(t1, ctx->base.pc_next + 4); + gen_op_addr_add(ctx, btarget, t1, t0); + + ctx->hflags |=3D MIPS_HFLAG_BR; + /* Generating branch here as compact branches don't have delay slot */ + gen_branch(ctx, 4); + + tcg_temp_free(t0); + tcg_temp_free(t1); +} =20 static void gen_p_lsx(DisasContext *ctx, int rd, int rs, int rt) { @@ -17923,16 +18072,129 @@ static int decode_nanomips_32_48_opc(CPUMIPSStat= e *env, DisasContext *ctx) } break; case NM_MOVE_BALC: + { + TCGv t0 =3D tcg_temp_new(); + int32_t s =3D sextract32(ctx->opcode, 0, 1) << 21 | + extract32(ctx->opcode, 1, 20) << 1; + rd =3D (extract32(ctx->opcode, 24, 1)) =3D=3D 0 ? 4 : 5; + rt =3D decode_gpr_gpr4_zero(extract32(ctx->opcode, 25, 1) << 3= | + extract32(ctx->opcode, 21, 3)); + gen_load_gpr(t0, rt); + tcg_gen_mov_tl(cpu_gpr[rd], t0); + gen_compute_branch(ctx, OPC_BGEZAL, 4, 0, 0, s, 0); + tcg_temp_free(t0); + } break; case NM_P_BAL: + { + int32_t s =3D sextract32(ctx->opcode, 0, 1) << 25 | + extract32(ctx->opcode, 1, 24) << 1; + + if ((extract32(ctx->opcode, 25, 1)) =3D=3D 0) { + /* BC */ + gen_compute_branch(ctx, OPC_BEQ, 4, 0, 0, s, 0); + } else { + /* BALC */ + gen_compute_branch(ctx, OPC_BGEZAL, 4, 0, 0, s, 0); + } + } break; case NM_P_J: + switch (extract32(ctx->opcode, 12, 4)) { + case NM_JALRC: + case NM_JALRC_HB: + gen_compute_branch(ctx, OPC_JALR, 4, rs, rt, 0, 0); + break; + case NM_P_BALRSC: + gen_compute_nanomips_pbalrsc_branch(ctx, rs, rt); + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } break; case NM_P_BR1: + { + int32_t s =3D sextract32(ctx->opcode, 0, 1) << 14 | + extract32(ctx->opcode, 1, 13) << 1; + switch (extract32(ctx->opcode, 14, 2)) { + case NM_BEQC: + gen_compute_branch(ctx, OPC_BEQ, 4, rs, rt, s, 0); + break; + case NM_P_BR3A: + s =3D sextract32(ctx->opcode, 0, 1) << 14 | + extract32(ctx->opcode, 1, 13) << 1; + check_cp1_enabled(ctx); + switch (extract32(ctx->opcode, 16, 5)) { + case NM_BC1EQZC: + gen_compute_branch1_r6(ctx, OPC_BC1EQZ, rt, s, 0); + break; + case NM_BC1NEZC: + gen_compute_branch1_r6(ctx, OPC_BC1NEZ, rt, s, 0); + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } + break; + case NM_BGEC: + if (rs =3D=3D rt) { + gen_compute_compact_branch(ctx, OPC_BC, rs, rt, s); + } else { + gen_compute_compact_branch(ctx, OPC_BGEC, rs, rt, s); + } + break; + case NM_BGEUC: + if (rs =3D=3D rt || rt =3D=3D 0) { + gen_compute_compact_branch(ctx, OPC_BC, 0, 0, s); + } else if (rs =3D=3D 0) { + gen_compute_compact_branch(ctx, OPC_BEQZC, rt, 0, s); + } else { + gen_compute_compact_branch(ctx, OPC_BGEUC, rs, rt, s); + } + break; + } + } break; case NM_P_BR2: + { + int32_t s =3D sextract32(ctx->opcode, 0, 1) << 14 | + extract32(ctx->opcode, 1, 13) << 1; + switch (extract32(ctx->opcode, 14, 2)) { + case NM_BNEC: + gen_compute_branch(ctx, OPC_BNE, 4, rs, rt, s, 0); + break; + case NM_BLTC: + if (rs !=3D 0 && rt !=3D 0 && rs =3D=3D rt) { + /* NOP */ + ctx->hflags |=3D MIPS_HFLAG_FBNSLOT; + } else { + gen_compute_compact_branch(ctx, OPC_BLTC, rs, rt, s); + } + break; + case NM_BLTUC: + if (rs =3D=3D 0 || rs =3D=3D rt) { + /* NOP */ + ctx->hflags |=3D MIPS_HFLAG_FBNSLOT; + } else { + gen_compute_compact_branch(ctx, OPC_BLTUC, rs, rt, s); + } + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } + } break; case NM_P_BRI: + { + int32_t s =3D sextract32(ctx->opcode, 0, 1) << 11 | + extract32(ctx->opcode, 1, 10) << 1; + uint32_t u =3D extract32(ctx->opcode, 11, 7); + + gen_compute_imm_branch(ctx, extract32(ctx->opcode, 18, 3), + rt, u, s); + } break; default: generate_exception_end(ctx, EXCP_RI); --=20 1.9.1