From nobody Wed Nov 5 08:20:06 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 153322050550317.597604978990944; Thu, 2 Aug 2018 07:35:05 -0700 (PDT) Received: from localhost ([::1]:45962 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1flEgy-00062C-8G for importer@patchew.org; Thu, 02 Aug 2018 10:35:04 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58096) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1flEaz-0001Hg-Dc for qemu-devel@nongnu.org; Thu, 02 Aug 2018 10:28:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1flEav-0003Nw-Ft for qemu-devel@nongnu.org; Thu, 02 Aug 2018 10:28:53 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:58061 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1flEav-0003NY-2A for qemu-devel@nongnu.org; Thu, 02 Aug 2018 10:28:49 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id C29F81A1FB4; Thu, 2 Aug 2018 16:28:47 +0200 (CEST) Received: from smarkovic.domain.local (smarkovic.domain.local [10.10.14.46]) by mail.rt-rk.com (Postfix) with ESMTPSA id A04841A1162; Thu, 2 Aug 2018 16:28:47 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Stefan Markovic To: qemu-devel@nongnu.org Date: Thu, 2 Aug 2018 16:16:15 +0200 Message-Id: <1533219424-7627-29-git-send-email-stefan.markovic@rt-rk.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1533219424-7627-1-git-send-email-stefan.markovic@rt-rk.com> References: <1533219424-7627-1-git-send-email-stefan.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v6 28/77] target/mips: Add emulation of nanoMIPS 48-bit instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pburton@wavecomp.com, smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, arikalo@wavecomp.com, philippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Yongbok Kim Add emulation of LI48, ADDIU48, ADDIUGP48, ADDIUPC48, LWPC48, and SWPC48 instructions. Reviewed-by: Richard Henderson Reviewed-by: Aleksandar Markovic Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic --- target/mips/translate.c | 66 +++++++++++++++++++++++++++++++++++++++++++++= +++- 1 file changed, 65 insertions(+), 1 deletion(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 65af99f..d61431f 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -16683,7 +16683,71 @@ static int decode_nanomips_32_48_opc(CPUMIPSState = *env, DisasContext *ctx) } break; case NM_P48I: - return 6; + { + insn =3D cpu_lduw_code(env, ctx->base.pc_next + 4); + target_long addr_off =3D extract32(ctx->opcode, 0, 16) | insn = << 16; + switch (extract32(ctx->opcode, 16, 5)) { + case NM_LI48: + if (rt !=3D 0) { + tcg_gen_movi_tl(cpu_gpr[rt], addr_off); + } + break; + case NM_ADDIU48: + if (rt !=3D 0) { + tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rt], addr_off); + tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]); + } + break; + case NM_ADDIUGP48: + if (rt !=3D 0) { + gen_op_addr_addi(ctx, cpu_gpr[rt], cpu_gpr[28], addr_o= ff); + } + break; + case NM_ADDIUPC48: + if (rt !=3D 0) { + target_long addr =3D addr_add(ctx, ctx->base.pc_next += 6, + addr_off); + + tcg_gen_movi_tl(cpu_gpr[rt], addr); + } + break; + case NM_LWPC48: + if (rt !=3D 0) { + TCGv t0; + t0 =3D tcg_temp_new(); + + target_long addr =3D addr_add(ctx, ctx->base.pc_next += 6, + addr_off); + + tcg_gen_movi_tl(t0, addr); + tcg_gen_qemu_ld_tl(cpu_gpr[rt], t0, ctx->mem_idx, MO_T= ESL); + tcg_temp_free(t0); + } + break; + case NM_SWPC48: + { + TCGv t0, t1; + t0 =3D tcg_temp_new(); + t1 =3D tcg_temp_new(); + + target_long addr =3D addr_add(ctx, ctx->base.pc_next += 6, + addr_off); + + tcg_gen_movi_tl(t0, addr); + gen_load_gpr(t1, rt); + + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL); + + tcg_temp_free(t0); + tcg_temp_free(t1); + } + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } + return 6; + } case NM_P_U12: switch (extract32(ctx->opcode, 12, 4)) { case NM_ORI: --=20 1.9.1