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X-Received-From: 2a00:1450:4864:20::441 Subject: [Qemu-devel] [RFC v3 3/6] i386/acpi-build: describe new pci domain in AML X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , Zihan Yang , "Michael S. Tsirkin" , Paolo Bonzini , Igor Mammedov , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Describe new pci segments of host bridges in AML as new pci devices, with _SEG and _BBN to let them be in DSDT Signed-off-by: Zihan Yang --- hw/i386/acpi-build.c | 78 +++++++++++++++++++++++++++++++++++-------------= ---- 1 file changed, 53 insertions(+), 25 deletions(-) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 30bd0d5..4b6ef78 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -1832,6 +1832,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, aml_append(dev, aml_name_decl("_UID", aml_int(1))); aml_append(dev, build_q35_osc_method()); aml_append(sb_scope, dev); + aml_append(dsdt, sb_scope); =20 build_hpet_aml(dsdt); @@ -1875,6 +1876,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, =20 crs_range_set_init(&crs_range_set); bus =3D PC_MACHINE(machine)->bus; + i =3D 1; // PCI0 is q35 host, pxb starts from 1 if (bus) { QLIST_FOREACH(bus, &bus->child, sibling) { uint8_t bus_num =3D pci_bus_num(bus); @@ -1890,10 +1892,9 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, } =20 scope =3D aml_scope("\\_SB"); - dev =3D aml_device("PC%.02X", bus_num); + dev =3D aml_device("PCI%d", i++); aml_append(dev, aml_name_decl("_UID", aml_int(bus_num))); aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); - aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num))); if (pci_bus_is_express(bus)) { aml_append(dev, build_q35_osc_method()); } @@ -2125,36 +2126,63 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, sb_scope =3D aml_scope("\\_SB"); { Object *pci_host; + QObject *o; PCIBus *bus =3D NULL; + uint32_t domain_nr; + uint8_t bus_nr; + int index =3D 0; =20 pci_host =3D acpi_get_i386_pci_host(); - if (pci_host) { + while (pci_host) { + Object *obj =3D object_property_get_link(pci_host, + PROP_PXB_PCIE_DEV, NULL); + if (!obj) { + /* we are in q35 host */ + obj =3D pci_host; + } + o =3D object_property_get_qobject(obj, PROP_PXB_PCIE_DOMAIN_NR= , NULL); + assert(o); + domain_nr =3D qnum_get_uint(qobject_to(QNum, o)); + qobject_unref(o); + + o =3D object_property_get_qobject(pci_host, "bus_nr", NULL); + if (!o) { + /* we are in q35 host */ + bus_nr =3D 0; + } else { + bus_nr =3D qnum_get_uint(qobject_to(QNum, o)); + qobject_unref(o); + } + bus =3D PCI_HOST_BRIDGE(pci_host)->bus; - } + if (bus) { + Aml *scope =3D aml_scope("PCI%d", index); + aml_append(scope, aml_name_decl("_SEG", aml_int(domain_nr)= )); + aml_append(scope, aml_name_decl("_BBN", aml_int(bus_nr))); + /* Scan all PCI buses. Generate tables to support hotplug.= */ + build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_= en); =20 - if (bus) { - Aml *scope =3D aml_scope("PCI0"); - /* Scan all PCI buses. Generate tables to support hotplug. */ - build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en); + /* Only add TPM once */ + if (index++ =3D=3D 0 && TPM_IS_TIS(tpm_find())) { + dev =3D aml_device("ISA.TPM"); + aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0= C31"))); + aml_append(dev, aml_name_decl("_STA", aml_int(0xF))); + crs =3D aml_resource_template(); + aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, + TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); + /* + FIXME: TPM_TIS_IRQ=3D5 conflicts with PNP0C0F irqs, + Rewrite to take IRQ from TPM device model and + fix default IRQ value there to use some unused IRQ + */ + /* aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); */ + aml_append(dev, aml_name_decl("_CRS", crs)); + aml_append(scope, dev); + } =20 - if (TPM_IS_TIS(tpm_find())) { - dev =3D aml_device("ISA.TPM"); - aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C31"= ))); - aml_append(dev, aml_name_decl("_STA", aml_int(0xF))); - crs =3D aml_resource_template(); - aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, - TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); - /* - FIXME: TPM_TIS_IRQ=3D5 conflicts with PNP0C0F irqs, - Rewrite to take IRQ from TPM device model and - fix default IRQ value there to use some unused IRQ - */ - /* aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); */ - aml_append(dev, aml_name_decl("_CRS", crs)); - aml_append(scope, dev); + aml_append(sb_scope, scope); } - - aml_append(sb_scope, scope); + pci_host =3D OBJECT(QTAILQ_NEXT(PCI_HOST_BRIDGE(pci_host), nex= t)); } } =20 --=20 2.7.4