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X-Received-From: 2a00:1450:4864:20::441 Subject: [Qemu-devel] [RFC v3 6/6] pci_expander_bridge: add start_bus property X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Zihan Yang Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The former bus_nr property indicates the bus number of pxb-pcie device on pcie.0 bus, not the Base Bus Number of pxb-pcie host bridge. Use start_bus property to represent this BBN when building acpi table Signed-off-by: Zihan Yang --- hw/i386/acpi-build.c | 22 +++++++++++----------- hw/pci-bridge/pci_expander_bridge.c | 25 ++++++++++++++----------- include/hw/pci-bridge/pci_expander_bridge.h | 2 +- 3 files changed, 26 insertions(+), 23 deletions(-) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 4b6ef78..874e0fa 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -91,7 +91,7 @@ typedef struct AcpiMcfgInfo { uint64_t mcfg_base; uint32_t mcfg_size; uint32_t domain_nr; - uint8_t bus_nr; // start bus number + uint8_t start_bus; // start bus number struct AcpiMcfgInfo *next; } AcpiMcfgInfo; =20 @@ -2129,7 +2129,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, QObject *o; PCIBus *bus =3D NULL; uint32_t domain_nr; - uint8_t bus_nr; + uint8_t start_bus; int index =3D 0; =20 pci_host =3D acpi_get_i386_pci_host(); @@ -2145,12 +2145,12 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, domain_nr =3D qnum_get_uint(qobject_to(QNum, o)); qobject_unref(o); =20 - o =3D object_property_get_qobject(pci_host, "bus_nr", NULL); + o =3D object_property_get_qobject(pci_host, "start_bus", NULL); if (!o) { /* we are in q35 host */ - bus_nr =3D 0; + start_bus =3D 0; } else { - bus_nr =3D qnum_get_uint(qobject_to(QNum, o)); + start_bus =3D qnum_get_uint(qobject_to(QNum, o)); qobject_unref(o); } =20 @@ -2158,7 +2158,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, if (bus) { Aml *scope =3D aml_scope("PCI%d", index); aml_append(scope, aml_name_decl("_SEG", aml_int(domain_nr)= )); - aml_append(scope, aml_name_decl("_BBN", aml_int(bus_nr))); + aml_append(scope, aml_name_decl("_BBN", aml_int(start_bus)= )); /* Scan all PCI buses. Generate tables to support hotplug.= */ build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_= en); =20 @@ -2486,8 +2486,8 @@ build_mcfg_q35(GArray *table_data, BIOSLinker *linker= , AcpiMcfgInfo *info) while (info) { mcfg[count].allocation[0].address =3D cpu_to_le64(info->mcfg_base); mcfg[count].allocation[0].pci_segment =3D cpu_to_le16(info->domain= _nr); - mcfg[count].allocation[0].start_bus_number =3D info->bus_nr; - mcfg[count++].allocation[0].end_bus_number =3D info->bus_nr + \ + mcfg[count].allocation[0].start_bus_number =3D info->start_bus; + mcfg[count++].allocation[0].end_bus_number =3D info->start_bus + \ PCIE_MMCFG_BUS(info->mcfg_size - 1); info =3D info->next; } @@ -2710,12 +2710,12 @@ static AcpiMcfgInfo *acpi_get_mcfg(void) mcfg->mcfg_size =3D qnum_get_uint(qobject_to(QNum, o)); qobject_unref(o); =20 - o =3D object_property_get_qobject(obj, PROP_PXB_BUS_NR, NULL); + o =3D object_property_get_qobject(obj, PROP_PXB_PCIE_START_BUS, NU= LL); if (!o) { /* we are in q35 host again */ - mcfg->bus_nr =3D 0; + mcfg->start_bus =3D 0; } else { - mcfg->bus_nr =3D qnum_get_uint(qobject_to(QNum, o)); + mcfg->start_bus =3D qnum_get_uint(qobject_to(QNum, o)); qobject_unref(o); } =20 diff --git a/hw/pci-bridge/pci_expander_bridge.c b/hw/pci-bridge/pci_expand= er_bridge.c index 38212db..85630ff 100644 --- a/hw/pci-bridge/pci_expander_bridge.c +++ b/hw/pci-bridge/pci_expander_bridge.c @@ -46,6 +46,7 @@ typedef struct PXBBus { #define TYPE_PXB_PCIE_DEVICE "pxb-pcie" #define PXB_PCIE_DEV(obj) OBJECT_CHECK(PXBDev, (obj), TYPE_PXB_PCIE_DEVICE) =20 +#define PROP_PXB_BUS_NR "bus_nr" #define PROP_PXB_PCIE_MAX_BUS "max_bus" #define PROP_PXB_NUMA_NODE "numa_node" =20 @@ -62,8 +63,9 @@ typedef struct PXBDev { PXBPCIEHost *pxbhost; =20 uint32_t domain_nr; /* PCI domain number, non-zero means separate doma= in */ + uint8_t start_bus; /* indicates the BBN of pxb-pcie-host bridge */ uint8_t max_bus; /* max bus number to use(including this one) */ - uint8_t bus_nr; + uint8_t bus_nr; /* bus number of pxb-pcie device on pcei.0 bus */ uint16_t numa_node; } PXBDev; =20 @@ -137,8 +139,8 @@ static void pxb_pcie_foreach(gpointer data, gpointer us= er_data) =20 if (pxb->domain_nr > 0) { /* only reserve what users ask for to reduce memory cost. Plus one - * as the interval [bus_nr, max_bus] has (max_bus-bus_nr+1) buses = */ - pxb_mcfg_hole_size +=3D ((pxb->max_bus - pxb->bus_nr + 1ULL) * MiB= ); + * as the interval [start_bus, max_bus] has (max_bus-start_bus+1) = buses */ + pxb_mcfg_hole_size +=3D ((pxb->max_bus - pxb->start_bus + 1ULL) * = MiB); } } =20 @@ -333,11 +335,11 @@ static gint pxb_compare(gconstpointer a, gconstpointe= r b) { const PXBDev *pxb_a =3D a, *pxb_b =3D b; =20 - /* check domain_nr, then bus_nr */ + /* check domain_nr, then start_bus */ return pxb_a->domain_nr < pxb_b->domain_nr ? -1 : pxb_a->domain_nr > pxb_b->domain_nr ? 1 : - pxb_a->bus_nr < pxb_b->bus_nr ? -1 : - pxb_a->bus_nr > pxb_b->bus_nr ? 1 : + pxb_a->start_bus < pxb_b->start_bus ? -1 : + pxb_a->start_bus > pxb_b->start_bus ? 1 : 0; } =20 @@ -362,7 +364,7 @@ static void pxb_dev_realize_common(PCIDevice *dev, bool= pcie, Error **errp) } =20 if (pcie) { - g_assert (pxb->max_bus >=3D pxb->bus_nr); + g_assert (pxb->max_bus >=3D pxb->start_bus); ds =3D qdev_create(NULL, TYPE_PXB_PCIE_HOST); /* attach it under /machine, so that we can resolve a valid path in * object_property_set_link below */ @@ -377,9 +379,9 @@ static void pxb_dev_realize_common(PCIDevice *dev, bool= pcie, Error **errp) /* will be overwritten by firmware, but kept for readability */ qdev_prop_set_uint64(ds, PCIE_HOST_MCFG_BASE, pxb->domain_nr ? pxb_pcie_mcfg_base : MCH_HOST_BRIDGE_PCIEXBAR= _DEFAULT); - /* +1 because [bus_nr, max_bus] has (max_bus-bus_nr+1) buses */ + /* +1 because [start_bus, max_bus] has (max_bus-start_bus+1) buses= */ qdev_prop_set_uint64(ds, PCIE_HOST_MCFG_SIZE, - pxb->domain_nr ? (pxb->max_bus - pxb->bus_nr + 1ULL) * MiB : 0= ); + pxb->domain_nr ? (pxb->max_bus - pxb->start_bus + 1ULL) * MiB = : 0); if (pxb->domain_nr) pxb_pcie_mcfg_base +=3D ((pxb->max_bus + 1ULL) * MiB); =20 @@ -389,7 +391,7 @@ static void pxb_dev_realize_common(PCIDevice *dev, bool= pcie, Error **errp) bus =3D pci_root_bus_new(ds, "pxb-internal", NULL, NULL, 0, TYPE_P= XB_BUS); bds =3D qdev_create(BUS(bus), "pci-bridge"); bds->id =3D dev_name; - qdev_prop_set_uint8(bds, PCI_BRIDGE_DEV_PROP_CHASSIS_NR, pxb->bus_= nr); + qdev_prop_set_uint8(bds, PCI_BRIDGE_DEV_PROP_CHASSIS_NR, pxb->star= t_bus); qdev_prop_set_bit(bds, PCI_BRIDGE_DEV_PROP_SHPC, false); } =20 @@ -482,7 +484,8 @@ static Property pxb_pcie_dev_properties[] =3D { DEFINE_PROP_UINT8(PROP_PXB_BUS_NR, PXBDev, bus_nr, 0), DEFINE_PROP_UINT16(PROP_PXB_NUMA_NODE, PXBDev, numa_node, NUMA_NODE_UN= ASSIGNED), DEFINE_PROP_UINT32(PROP_PXB_PCIE_DOMAIN_NR, PXBDev, domain_nr, 0), - /* set a small default value, bus interval is [bus_nr, max_bus] */ + DEFINE_PROP_UINT8(PROP_PXB_PCIE_START_BUS, PXBDev, start_bus, 0), + /* set a small default value, bus interval is [start_bus, max_bus] */ DEFINE_PROP_UINT8(PROP_PXB_PCIE_MAX_BUS, PXBDev, max_bus, 16), =20 DEFINE_PROP_END_OF_LIST(), diff --git a/include/hw/pci-bridge/pci_expander_bridge.h b/include/hw/pci-b= ridge/pci_expander_bridge.h index e6d3b67..54b050c 100644 --- a/include/hw/pci-bridge/pci_expander_bridge.h +++ b/include/hw/pci-bridge/pci_expander_bridge.h @@ -5,7 +5,7 @@ #define PROP_PXB_PCIE_HOST "x-pxb-host" =20 #define PROP_PXB_PCIE_DOMAIN_NR "domain_nr" -#define PROP_PXB_BUS_NR "bus_nr" +#define PROP_PXB_PCIE_START_BUS "start_bus" =20 #define PXB_PCIE_HOST_BRIDGE_CONFIG_ADDR_BASE 0x1000 #define PXB_PCIE_HOST_BRIDGE_CONFIG_DATA_BASE 0x1004 --=20 2.7.4