From nobody Wed Nov 5 05:11:01 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1533178088986697.5462536201613; Wed, 1 Aug 2018 19:48:08 -0700 (PDT) Received: from localhost ([::1]:43665 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fl3em-0004ex-3b for importer@patchew.org; Wed, 01 Aug 2018 22:48:04 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44353) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fl3Zu-0001Ew-Qn for qemu-devel@nongnu.org; Wed, 01 Aug 2018 22:43:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fl3Zs-00078P-Vp for qemu-devel@nongnu.org; Wed, 01 Aug 2018 22:43:02 -0400 Received: from mail-wm0-x243.google.com ([2a00:1450:400c:c09::243]:53790) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fl3Zs-00077K-H9 for qemu-devel@nongnu.org; Wed, 01 Aug 2018 22:43:00 -0400 Received: by mail-wm0-x243.google.com with SMTP id s9-v6so721706wmh.3 for ; Wed, 01 Aug 2018 19:43:00 -0700 (PDT) Received: from bloodymary.ipads-lab.se.sjtu.edu.cn ([46.243.138.172]) by smtp.gmail.com with ESMTPSA id t2-v6sm389721wrv.63.2018.08.01.19.42.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 01 Aug 2018 19:42:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Fr8xIPGMGGCrzj+Q8SvI6XBXxGnuKZcUUBjZBOZjKFk=; b=KvPUEDKKj5OAsVbAzBnJGJ3y8lsU1PhGNiko6GMG6v4eVN34F27fIt/446IFe/5aGN DDWaXLQVTZRJk6K/xrKBN1Pu9whFgIxBGU6wm45qT1Jachd/XOSZVMjiWmJcZ3God8Nn qgMX02KRIhUpZ64HtMYSxyhgwv7zceIa1jStbI22SS0UhY77zq/v7hEY+Pm3Rp5TGAbO uZ/DUCcHoyiWnqalG7jUqzZ1sPKld9bLxTcGajZbnWuqgBKgvD/39cI7v8jl9oftWt8K aCVF7POmHVyz2pkelwDJNbz2LiA5bJg+p/LUcH7JfeYdm+GZdOyBVaHwiOa7rwz6ImN5 Jqlw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Fr8xIPGMGGCrzj+Q8SvI6XBXxGnuKZcUUBjZBOZjKFk=; b=PuVCIvVFEOAj75w0TH9jUHo5Z7Le14LXhXXPEuU84X3dL3IpD+aBiJ+c4AwjQjiEk5 Nr/B77Pp8ADqsmoBiodtfK6zpsh1W7qMiKTIYJqf3F6g0jPlMh7AuZk/xL4N/+kNX06A gyYNVbhe5aLM/gPjbauYGDK2EATRsbW97xhjRoTiDOhe9d8tIBSWKqsbuT/rHdimHAz6 MEKTHxWOgdJXmyK3+W4LnHfI/OaXIY+6rh91cNuBp7U2clPtnRGCQUiEZRWihl+FPlLK ul1x0lsIF6ndszHoHfRKg4SdGtpK83mDIB0dZdIxpUjGgtiLWeNRp91aasXP82gd6s+Z KMGQ== X-Gm-Message-State: AOUpUlHEmUdJhpzW6DfWvJ9Pc/E3FbXtt1wvjqCzJig3+ohZBCzu7nyw Akbn1C0n8H+qsG69/MJscPlfThsh9K0= X-Google-Smtp-Source: AAOMgpfQ7Bc6GENPPmgaTGluXENFr7D4u3P7pAi8287SShIQk2WUJAGnv1aD+OdVpJDB0cu5ye/2dw== X-Received: by 2002:a1c:e54:: with SMTP id 81-v6mr588832wmo.84.1533177779192; Wed, 01 Aug 2018 19:42:59 -0700 (PDT) From: Zihan Yang To: qemu-devel@nongnu.org Date: Thu, 2 Aug 2018 10:42:18 +0800 Message-Id: <1533177743-20894-2-git-send-email-whois.zihan.yang@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1533177743-20894-1-git-send-email-whois.zihan.yang@gmail.com> References: <1533177743-20894-1-git-send-email-whois.zihan.yang@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::243 Subject: [Qemu-devel] [RFC v3 1/6] pci_expander_bridge: add type TYPE_PXB_PCIE_HOST X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Zihan Yang Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The inner host bridge created by pxb-pcie is TYPE_PXB_PCI_HOST by default, change it to a new type TYPE_PXB_PCIE_HOST to better utilize ECAM of PCIe Signed-off-by: Zihan Yang --- hw/pci-bridge/pci_expander_bridge.c | 127 ++++++++++++++++++++++++++++++++= ++-- 1 file changed, 122 insertions(+), 5 deletions(-) diff --git a/hw/pci-bridge/pci_expander_bridge.c b/hw/pci-bridge/pci_expand= er_bridge.c index e62de42..6dd38de 100644 --- a/hw/pci-bridge/pci_expander_bridge.c +++ b/hw/pci-bridge/pci_expander_bridge.c @@ -15,10 +15,12 @@ #include "hw/pci/pci.h" #include "hw/pci/pci_bus.h" #include "hw/pci/pci_host.h" +#include "hw/pci/pcie_host.h" #include "hw/pci/pci_bridge.h" #include "qemu/range.h" #include "qemu/error-report.h" #include "sysemu/numa.h" +#include "qapi/visitor.h" =20 #define TYPE_PXB_BUS "pxb-bus" #define PXB_BUS(obj) OBJECT_CHECK(PXBBus, (obj), TYPE_PXB_BUS) @@ -40,11 +42,20 @@ typedef struct PXBBus { #define TYPE_PXB_PCIE_DEVICE "pxb-pcie" #define PXB_PCIE_DEV(obj) OBJECT_CHECK(PXBDev, (obj), TYPE_PXB_PCIE_DEVICE) =20 +#define PROP_PXB_PCIE_DEV "pxbdev" + +#define PROP_PXB_PCIE_DOMAIN_NR "domain_nr" +#define PROP_PXB_PCIE_MAX_BUS "max_bus" +#define PROP_PXB_BUS_NR "bus_nr" +#define PROP_PXB_NUMA_NODE "numa_node" + typedef struct PXBDev { /*< private >*/ PCIDevice parent_obj; /*< public >*/ =20 + uint32_t domain_nr; /* PCI domain number, non-zero means separate doma= in */ + uint8_t max_bus; /* max bus number to use(including this one) */ uint8_t bus_nr; uint16_t numa_node; } PXBDev; @@ -58,6 +69,16 @@ static PXBDev *convert_to_pxb(PCIDevice *dev) static GList *pxb_dev_list; =20 #define TYPE_PXB_HOST "pxb-host" +#define TYPE_PXB_PCIE_HOST "pxb-pcie-host" +#define PXB_PCIE_HOST_DEVICE(obj) \ + OBJECT_CHECK(PXBPCIEHost, (obj), TYPE_PXB_PCIE_HOST) + +typedef struct PXBPCIEHost { + PCIExpressHost parent_obj; + + /* pointers to PXBDev */ + PXBDev *pxbdev; +} PXBPCIEHost; =20 static int pxb_bus_num(PCIBus *bus) { @@ -111,6 +132,35 @@ static const char *pxb_host_root_bus_path(PCIHostState= *host_bridge, return bus->bus_path; } =20 +/* Use a dedicated function for PCIe since pxb-host does + * not have a domain_nr field */ +static const char *pxb_pcie_host_root_bus_path(PCIHostState *host_bridge, + PCIBus *rootbus) +{ + if (!pci_bus_is_express(rootbus)) { + /* pxb-pcie-host cannot reside on a PCI bus */ + return NULL; + } + PXBBus *bus =3D PXB_PCIE_BUS(rootbus); + + /* get the pointer to PXBDev */ + Object *obj =3D object_property_get_link(OBJECT(host_bridge), + PROP_PXB_PCIE_DEV, NULL); + + snprintf(bus->bus_path, 8, "%04lx:%02x", + object_property_get_uint(obj, PROP_PXB_PCIE_DOMAIN_NR, NULL), + pxb_bus_num(rootbus)); + return bus->bus_path; +} + +static void pxb_pcie_host_get_mmcfg_size(Object *obj, Visitor *v, const ch= ar *name, + void *opaque, Error **errp) +{ + PCIExpressHost *e =3D PCIE_HOST_BRIDGE(obj); + + visit_type_uint64(v, name, &e->size, errp); +} + static char *pxb_host_ofw_unit_address(const SysBusDevice *dev) { const PCIHostState *pxb_host; @@ -142,6 +192,31 @@ static char *pxb_host_ofw_unit_address(const SysBusDev= ice *dev) return NULL; } =20 +static void pxb_pcie_host_initfn(Object *obj) +{ + PXBPCIEHost *s =3D PXB_PCIE_HOST_DEVICE(obj); + PCIHostState *phb =3D PCI_HOST_BRIDGE(obj); + + memory_region_init_io(&phb->conf_mem, obj, &pci_host_conf_le_ops, phb, + "pci-conf-idx", 4); + memory_region_init_io(&phb->data_mem, obj, &pci_host_data_le_ops, phb, + "pci-conf-data", 4); + + object_property_add(obj, PCIE_HOST_MCFG_SIZE, "uint64", + pxb_pcie_host_get_mmcfg_size, + NULL, NULL, NULL, NULL); + + object_property_add_link(obj, PROP_PXB_PCIE_DEV, TYPE_PXB_PCIE_DEVICE, + (Object **)&s->pxbdev, + qdev_prop_allow_set_link_before_realize, 0, NULL); +} + +static Property pxb_pcie_host_props[] =3D { + DEFINE_PROP_UINT64(PCIE_HOST_MCFG_BASE, PXBPCIEHost, parent_obj.base_a= ddr, + PCIE_BASE_ADDR_UNMAPPED), + DEFINE_PROP_END_OF_LIST(), +}; + static void pxb_host_class_init(ObjectClass *class, void *data) { DeviceClass *dc =3D DEVICE_CLASS(class); @@ -155,12 +230,34 @@ static void pxb_host_class_init(ObjectClass *class, v= oid *data) hc->root_bus_path =3D pxb_host_root_bus_path; } =20 +static void pxb_pcie_host_class_init(ObjectClass *class, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(class); + SysBusDeviceClass *sbc =3D SYS_BUS_DEVICE_CLASS(class); + PCIHostBridgeClass *hc =3D PCI_HOST_BRIDGE_CLASS(class); + + dc->fw_name =3D "pcie"; + dc->props =3D pxb_pcie_host_props; + /* Reason: Internal part of the pxb/pxb-pcie device, not usable by its= elf */ + dc->user_creatable =3D false; + sbc->explicit_ofw_unit_address =3D pxb_host_ofw_unit_address; + hc->root_bus_path =3D pxb_pcie_host_root_bus_path; +} + static const TypeInfo pxb_host_info =3D { .name =3D TYPE_PXB_HOST, .parent =3D TYPE_PCI_HOST_BRIDGE, .class_init =3D pxb_host_class_init, }; =20 +static const TypeInfo pxb_pcie_host_info =3D { + .name =3D TYPE_PXB_PCIE_HOST, + .parent =3D TYPE_PCIE_HOST_BRIDGE, + .instance_size =3D sizeof(PXBPCIEHost), + .instance_init =3D pxb_pcie_host_initfn, + .class_init =3D pxb_pcie_host_class_init, +}; + /* * Registers the PXB bus as a child of pci host root bus. */ @@ -205,7 +302,10 @@ static gint pxb_compare(gconstpointer a, gconstpointer= b) { const PXBDev *pxb_a =3D a, *pxb_b =3D b; =20 - return pxb_a->bus_nr < pxb_b->bus_nr ? -1 : + /* check domain_nr, then bus_nr */ + return pxb_a->domain_nr < pxb_b->domain_nr ? -1 : + pxb_a->domain_nr > pxb_b->domain_nr ? 1 : + pxb_a->bus_nr < pxb_b->bus_nr ? -1 : pxb_a->bus_nr > pxb_b->bus_nr ? 1 : 0; } @@ -228,10 +328,16 @@ static void pxb_dev_realize_common(PCIDevice *dev, bo= ol pcie, Error **errp) dev_name =3D dev->qdev.id; } =20 - ds =3D qdev_create(NULL, TYPE_PXB_HOST); if (pcie) { + g_assert (pxb->max_bus >=3D pxb->bus_nr); + ds =3D qdev_create(NULL, TYPE_PXB_PCIE_HOST); + + object_property_set_link(OBJECT(ds), OBJECT(pxb), + PROP_PXB_PCIE_DEV, NULL); + bus =3D pci_root_bus_new(ds, dev_name, NULL, NULL, 0, TYPE_PXB_PCI= E_BUS); } else { + ds =3D qdev_create(NULL, TYPE_PXB_HOST); bus =3D pci_root_bus_new(ds, "pxb-internal", NULL, NULL, 0, TYPE_P= XB_BUS); bds =3D qdev_create(BUS(bus), "pci-bridge"); bds->id =3D dev_name; @@ -289,8 +395,18 @@ static void pxb_dev_exitfn(PCIDevice *pci_dev) =20 static Property pxb_dev_properties[] =3D { /* Note: 0 is not a legal PXB bus number. */ - DEFINE_PROP_UINT8("bus_nr", PXBDev, bus_nr, 0), - DEFINE_PROP_UINT16("numa_node", PXBDev, numa_node, NUMA_NODE_UNASSIGNE= D), + DEFINE_PROP_UINT8(PROP_PXB_BUS_NR, PXBDev, bus_nr, 0), + DEFINE_PROP_UINT16(PROP_PXB_NUMA_NODE, PXBDev, numa_node, NUMA_NODE_UN= ASSIGNED), + DEFINE_PROP_END_OF_LIST(), +}; + +static Property pxb_pcie_dev_properties[] =3D { + DEFINE_PROP_UINT8(PROP_PXB_BUS_NR, PXBDev, bus_nr, 0), + DEFINE_PROP_UINT16(PROP_PXB_NUMA_NODE, PXBDev, numa_node, NUMA_NODE_UN= ASSIGNED), + DEFINE_PROP_UINT32(PROP_PXB_PCIE_DOMAIN_NR, PXBDev, domain_nr, 0), + /* set a small default value, bus interval is [bus_nr, max_bus] */ + DEFINE_PROP_UINT8(PROP_PXB_PCIE_MAX_BUS, PXBDev, max_bus, 16), + DEFINE_PROP_END_OF_LIST(), }; =20 @@ -344,7 +460,7 @@ static void pxb_pcie_dev_class_init(ObjectClass *klass,= void *data) k->class_id =3D PCI_CLASS_BRIDGE_HOST; =20 dc->desc =3D "PCI Express Expander Bridge"; - dc->props =3D pxb_dev_properties; + dc->props =3D pxb_pcie_dev_properties; dc->hotpluggable =3D false; set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); } @@ -365,6 +481,7 @@ static void pxb_register_types(void) type_register_static(&pxb_bus_info); type_register_static(&pxb_pcie_bus_info); type_register_static(&pxb_host_info); + type_register_static(&pxb_pcie_host_info); type_register_static(&pxb_dev_info); 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X-Received-From: 2a00:1450:400c:c09::244 Subject: [Qemu-devel] [RFC v3 2/6] acpi-build: allocate mcfg for pxb-pcie host bridges X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Zihan Yang Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Allocate new segment for pxb-pcie host bridges in MCFG table, and reserve corresponding MCFG space for them. This allows user-defined pxb-pcie host bridges to be placed in different pci domain than q35 host. The pci_host_bridges list is changed to be tail list to ensure the q35 host is always the first element when traversing the list, because q35 host is inserted beofre pxb-pcie hosts Signed-off-by: Zihan Yang --- hw/i386/acpi-build.c | 115 +++++++++++++++++++++++-= ---- hw/i386/pc.c | 14 +++- hw/pci-bridge/pci_expander_bridge.c | 57 ++++++++++---- hw/pci-host/q35.c | 2 + hw/pci/pci.c | 9 ++- include/hw/i386/pc.h | 1 + include/hw/pci-bridge/pci_expander_bridge.h | 11 +++ include/hw/pci-host/q35.h | 1 + include/hw/pci/pci_host.h | 2 +- 9 files changed, 168 insertions(+), 44 deletions(-) create mode 100644 include/hw/pci-bridge/pci_expander_bridge.h diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 9e8350c..30bd0d5 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -55,6 +55,7 @@ #include "hw/i386/ich9.h" #include "hw/pci/pci_bus.h" #include "hw/pci-host/q35.h" +#include "hw/pci-bridge/pci_expander_bridge.h" #include "hw/i386/x86-iommu.h" =20 #include "hw/acpi/aml-build.h" @@ -89,6 +90,9 @@ typedef struct AcpiMcfgInfo { uint64_t mcfg_base; uint32_t mcfg_size; + uint32_t domain_nr; + uint8_t bus_nr; // start bus number + struct AcpiMcfgInfo *next; } AcpiMcfgInfo; =20 typedef struct AcpiPmInfo { @@ -2427,14 +2431,16 @@ build_mcfg_q35(GArray *table_data, BIOSLinker *link= er, AcpiMcfgInfo *info) { AcpiTableMcfg *mcfg; const char *sig; - int len =3D sizeof(*mcfg) + 1 * sizeof(mcfg->allocation[0]); + int len, count =3D 0; + AcpiMcfgInfo *cfg =3D info; + + while (cfg) { + ++count; + cfg =3D cfg->next; + } + len =3D sizeof(*mcfg) + count * sizeof(mcfg->allocation[0]); =20 mcfg =3D acpi_data_push(table_data, len); - mcfg->allocation[0].address =3D cpu_to_le64(info->mcfg_base); - /* Only a single allocation so no need to play with segments */ - mcfg->allocation[0].pci_segment =3D cpu_to_le16(0); - mcfg->allocation[0].start_bus_number =3D 0; - mcfg->allocation[0].end_bus_number =3D PCIE_MMCFG_BUS(info->mcfg_size = - 1); =20 /* MCFG is used for ECAM which can be enabled or disabled by guest. * To avoid table size changes (which create migration issues), @@ -2448,6 +2454,16 @@ build_mcfg_q35(GArray *table_data, BIOSLinker *linke= r, AcpiMcfgInfo *info) } else { sig =3D "MCFG"; } + + while (info) { + mcfg[count].allocation[0].address =3D cpu_to_le64(info->mcfg_base); + mcfg[count].allocation[0].pci_segment =3D cpu_to_le16(info->domain= _nr); + mcfg[count].allocation[0].start_bus_number =3D info->bus_nr; + mcfg[count++].allocation[0].end_bus_number =3D info->bus_nr + \ + PCIE_MMCFG_BUS(info->mcfg_size - 1); + info =3D info->next; + } + build_header(linker, table_data, (void *)mcfg, sig, len, 1, NULL, NULL= ); } =20 @@ -2602,26 +2618,83 @@ struct AcpiBuildState { MemoryRegion *linker_mr; } AcpiBuildState; =20 -static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg) +static inline void cleanup_mcfg(AcpiMcfgInfo *mcfg) +{ + AcpiMcfgInfo *tmp; + while (mcfg) { + tmp =3D mcfg->next; + g_free(mcfg); + mcfg =3D tmp; + } +} + +static AcpiMcfgInfo *acpi_get_mcfg(void) { Object *pci_host; QObject *o; + uint32_t domain_nr; + AcpiMcfgInfo *head =3D NULL, *tail, *mcfg; =20 pci_host =3D acpi_get_i386_pci_host(); g_assert(pci_host); =20 - o =3D object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL); - if (!o) { - return false; + while (pci_host) { + /* pxb-pcie-hosts does not have domain_nr property, but a link + * to PXBDev. We first try to get pxbdev property, if NULL, + * then it is q35 host, otherwise it is pxb-pcie-host */ + Object *obj =3D object_property_get_link(pci_host, + PROP_PXB_PCIE_DEV, NULL); + if (!obj) { + /* we are in q35 host */ + obj =3D pci_host; + } + o =3D object_property_get_qobject(obj, PROP_PXB_PCIE_DOMAIN_NR, NU= LL); + assert(o); + domain_nr =3D qnum_get_uint(qobject_to(QNum, o)); + qobject_unref(o); + + /* Skip bridges that reside in the same domain with q35 host. + * Q35 always stays in pci domain 0, and is the first element + * in the pci_host_bridges list */ + if (head && domain_nr =3D=3D 0) { + pci_host =3D OBJECT(QTAILQ_NEXT(PCI_HOST_BRIDGE(pci_host), nex= t)); + continue; + } + + mcfg =3D g_new0(AcpiMcfgInfo, 1); + mcfg->next =3D NULL; + if (!head) { + tail =3D head =3D mcfg; + } else { + tail->next =3D mcfg; + tail =3D mcfg; + } + mcfg->domain_nr =3D domain_nr; + + o =3D object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, N= ULL); + assert(o); + mcfg->mcfg_base =3D qnum_get_uint(qobject_to(QNum, o)); + qobject_unref(o); + + /* firmware will overwrite it */ + o =3D object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, N= ULL); + assert(o); + mcfg->mcfg_size =3D qnum_get_uint(qobject_to(QNum, o)); + qobject_unref(o); + + o =3D object_property_get_qobject(obj, PROP_PXB_BUS_NR, NULL); + if (!o) { + /* we are in q35 host again */ + mcfg->bus_nr =3D 0; + } else { + mcfg->bus_nr =3D qnum_get_uint(qobject_to(QNum, o)); + qobject_unref(o); + } + + pci_host =3D OBJECT(QTAILQ_NEXT(PCI_HOST_BRIDGE(pci_host), next)); } - mcfg->mcfg_base =3D qnum_get_uint(qobject_to(QNum, o)); - qobject_unref(o); =20 - o =3D object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL); - assert(o); - mcfg->mcfg_size =3D qnum_get_uint(qobject_to(QNum, o)); - qobject_unref(o); - return true; + return head; } =20 static @@ -2633,7 +2706,7 @@ void acpi_build(AcpiBuildTables *tables, MachineState= *machine) unsigned facs, dsdt, rsdt, fadt; AcpiPmInfo pm; AcpiMiscInfo misc; - AcpiMcfgInfo mcfg; + AcpiMcfgInfo *mcfg; Range pci_hole, pci_hole64; uint8_t *u; size_t aml_len =3D 0; @@ -2714,10 +2787,12 @@ void acpi_build(AcpiBuildTables *tables, MachineSta= te *machine) build_slit(tables_blob, tables->linker); } } - if (acpi_get_mcfg(&mcfg)) { + if ((mcfg =3D acpi_get_mcfg()) !=3D NULL) { acpi_add_table(table_offsets, tables_blob); - build_mcfg_q35(tables_blob, tables->linker, &mcfg); + build_mcfg_q35(tables_blob, tables->linker, mcfg); } + cleanup_mcfg(mcfg); + if (x86_iommu_get_default()) { IommuType IOMMUType =3D x86_iommu_get_type(); if (IOMMUType =3D=3D TYPE_AMD) { diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 83a4444..a7e51af 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -35,6 +35,7 @@ #include "hw/ide.h" #include "hw/pci/pci.h" #include "hw/pci/pci_bus.h" +#include "hw/pci-bridge/pci_expander_bridge.h" #include "hw/nvram/fw_cfg.h" #include "hw/timer/hpet.h" #include "hw/smbios/smbios.h" @@ -1470,15 +1471,24 @@ uint64_t pc_pci_hole64_start(void) if (pcmc->has_reserved_memory && ms->device_memory->base) { hole64_start =3D ms->device_memory->base; if (!pcmc->broken_reserved_end) { - hole64_start +=3D memory_region_size(&ms->device_memory->mr); + hole64_start +=3D (memory_region_size(&ms->device_memory->mr) = + \ + pxb_pcie_mcfg_hole()); } } else { - hole64_start =3D 0x100000000ULL + pcms->above_4g_mem_size; + /* memory layout [RAM Hotplug][MCFG][..ROUND UP..][PCI HOLE] */ + hole64_start =3D pc_pci_mcfg_start() + pxb_pcie_mcfg_hole(); } =20 return ROUND_UP(hole64_start, 1 * GiB); } =20 +uint64_t pc_pci_mcfg_start(void) +{ + PCMachineState *pcms =3D PC_MACHINE(qdev_get_machine()); + + return ROUND_UP(0x100000000ULL + pcms->above_4g_mem_size, 4 * KiB); +} + qemu_irq pc_allocate_cpu_irq(void) { return qemu_allocate_irq(pic_irq_request, NULL, 0); diff --git a/hw/pci-bridge/pci_expander_bridge.c b/hw/pci-bridge/pci_expand= er_bridge.c index 6dd38de..f50938f 100644 --- a/hw/pci-bridge/pci_expander_bridge.c +++ b/hw/pci-bridge/pci_expander_bridge.c @@ -12,15 +12,19 @@ =20 #include "qemu/osdep.h" #include "qapi/error.h" +#include "hw/i386/pc.h" #include "hw/pci/pci.h" #include "hw/pci/pci_bus.h" #include "hw/pci/pci_host.h" #include "hw/pci/pcie_host.h" #include "hw/pci/pci_bridge.h" +#include "hw/pci-host/q35.h" +#include "hw/pci-bridge/pci_expander_bridge.h" #include "qemu/range.h" #include "qemu/error-report.h" #include "sysemu/numa.h" #include "qapi/visitor.h" +#include "qemu/units.h" =20 #define TYPE_PXB_BUS "pxb-bus" #define PXB_BUS(obj) OBJECT_CHECK(PXBBus, (obj), TYPE_PXB_BUS) @@ -42,11 +46,7 @@ typedef struct PXBBus { #define TYPE_PXB_PCIE_DEVICE "pxb-pcie" #define PXB_PCIE_DEV(obj) OBJECT_CHECK(PXBDev, (obj), TYPE_PXB_PCIE_DEVICE) =20 -#define PROP_PXB_PCIE_DEV "pxbdev" - -#define PROP_PXB_PCIE_DOMAIN_NR "domain_nr" #define PROP_PXB_PCIE_MAX_BUS "max_bus" -#define PROP_PXB_BUS_NR "bus_nr" #define PROP_PXB_NUMA_NODE "numa_node" =20 typedef struct PXBDev { @@ -122,6 +122,26 @@ static const TypeInfo pxb_pcie_bus_info =3D { .class_init =3D pxb_bus_class_init, }; =20 +static uint64_t pxb_mcfg_hole_size =3D 0; + +static void pxb_pcie_foreach(gpointer data, gpointer user_data) +{ + PXBDev *pxb =3D (PXBDev *)data; + + if (pxb->domain_nr > 0) { + /* only reserve what users ask for to reduce memory cost. Plus one + * as the interval [bus_nr, max_bus] has (max_bus-bus_nr+1) buses = */ + pxb_mcfg_hole_size +=3D ((pxb->max_bus - pxb->bus_nr + 1ULL) * MiB= ); + } +} + +uint64_t pxb_pcie_mcfg_hole(void) +{ + /* foreach is necessary as some pxb still reside in domain 0 */ + g_list_foreach(pxb_dev_list, pxb_pcie_foreach, NULL); + return pxb_mcfg_hole_size; +} + static const char *pxb_host_root_bus_path(PCIHostState *host_bridge, PCIBus *rootbus) { @@ -153,14 +173,6 @@ static const char *pxb_pcie_host_root_bus_path(PCIHost= State *host_bridge, return bus->bus_path; } =20 -static void pxb_pcie_host_get_mmcfg_size(Object *obj, Visitor *v, const ch= ar *name, - void *opaque, Error **errp) -{ - PCIExpressHost *e =3D PCIE_HOST_BRIDGE(obj); - - visit_type_uint64(v, name, &e->size, errp); -} - static char *pxb_host_ofw_unit_address(const SysBusDevice *dev) { const PCIHostState *pxb_host; @@ -202,10 +214,6 @@ static void pxb_pcie_host_initfn(Object *obj) memory_region_init_io(&phb->data_mem, obj, &pci_host_data_le_ops, phb, "pci-conf-data", 4); =20 - object_property_add(obj, PCIE_HOST_MCFG_SIZE, "uint64", - pxb_pcie_host_get_mmcfg_size, - NULL, NULL, NULL, NULL); - object_property_add_link(obj, PROP_PXB_PCIE_DEV, TYPE_PXB_PCIE_DEVICE, (Object **)&s->pxbdev, qdev_prop_allow_set_link_before_realize, 0, NULL); @@ -214,6 +222,7 @@ static void pxb_pcie_host_initfn(Object *obj) static Property pxb_pcie_host_props[] =3D { DEFINE_PROP_UINT64(PCIE_HOST_MCFG_BASE, PXBPCIEHost, parent_obj.base_a= ddr, PCIE_BASE_ADDR_UNMAPPED), + DEFINE_PROP_UINT64(PCIE_HOST_MCFG_SIZE, PXBPCIEHost, parent_obj.size, = 0), DEFINE_PROP_END_OF_LIST(), }; =20 @@ -310,6 +319,8 @@ static gint pxb_compare(gconstpointer a, gconstpointer = b) 0; } =20 +static uint64_t pxb_pcie_mcfg_base; + static void pxb_dev_realize_common(PCIDevice *dev, bool pcie, Error **errp) { PXBDev *pxb =3D convert_to_pxb(dev); @@ -333,7 +344,16 @@ static void pxb_dev_realize_common(PCIDevice *dev, boo= l pcie, Error **errp) ds =3D qdev_create(NULL, TYPE_PXB_PCIE_HOST); =20 object_property_set_link(OBJECT(ds), OBJECT(pxb), - PROP_PXB_PCIE_DEV, NULL); + PROP_PXB_PCIE_DEV, errp); + + /* will be overwritten by firmware, but kept for readability */ + qdev_prop_set_uint64(ds, PCIE_HOST_MCFG_BASE, + pxb->domain_nr ? pxb_pcie_mcfg_base : MCH_HOST_BRIDGE_PCIEXBAR= _DEFAULT); + /* +1 because [bus_nr, max_bus] has (max_bus-bus_nr+1) buses */ + qdev_prop_set_uint64(ds, PCIE_HOST_MCFG_SIZE, + pxb->domain_nr ? (pxb->max_bus - pxb->bus_nr + 1ULL) * MiB : 0= ); + if (pxb->domain_nr) + pxb_pcie_mcfg_base +=3D ((pxb->max_bus + 1ULL) * MiB); =20 bus =3D pci_root_bus_new(ds, dev_name, NULL, NULL, 0, TYPE_PXB_PCI= E_BUS); } else { @@ -445,6 +465,9 @@ static void pxb_pcie_dev_realize(PCIDevice *dev, Error = **errp) return; } =20 + if (0 =3D=3D pxb_pcie_mcfg_base) + pxb_pcie_mcfg_base =3D pc_pci_mcfg_start(); + pxb_dev_realize_common(dev, true, errp); } =20 diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index 02f9576..10e4801 100644 --- a/hw/pci-host/q35.c +++ b/hw/pci-host/q35.c @@ -177,6 +177,8 @@ static Property q35_host_props[] =3D { mch.below_4g_mem_size, 0), DEFINE_PROP_SIZE(PCI_HOST_ABOVE_4G_MEM_SIZE, Q35PCIHost, mch.above_4g_mem_size, 0), + /* q35 host bridge should always stay in pci domain 0 */ + DEFINE_PROP_UINT32("domain_nr", Q35PCIHost, domain_nr, 0), DEFINE_PROP_BOOL("x-pci-hole64-fix", Q35PCIHost, pci_hole64_fix, true), DEFINE_PROP_END_OF_LIST(), }; diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 80bc459..ddc27ba 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -196,7 +196,8 @@ static void pci_del_option_rom(PCIDevice *pdev); static uint16_t pci_default_sub_vendor_id =3D PCI_SUBVENDOR_ID_REDHAT_QUMR= ANET; static uint16_t pci_default_sub_device_id =3D PCI_SUBDEVICE_ID_QEMU; =20 -static QLIST_HEAD(, PCIHostState) pci_host_bridges; +static QTAILQ_HEAD(, PCIHostState) pci_host_bridges =3D + QTAILQ_HEAD_INITIALIZER(pci_host_bridges); =20 int pci_bar(PCIDevice *d, int reg) { @@ -330,7 +331,7 @@ static void pci_host_bus_register(DeviceState *host) { PCIHostState *host_bridge =3D PCI_HOST_BRIDGE(host); =20 - QLIST_INSERT_HEAD(&pci_host_bridges, host_bridge, next); + QTAILQ_INSERT_TAIL(&pci_host_bridges, host_bridge, next); } =20 PCIBus *pci_device_root_bus(const PCIDevice *d) @@ -1798,7 +1799,7 @@ PciInfoList *qmp_query_pci(Error **errp) PciInfoList *info, *head =3D NULL, *cur_item =3D NULL; PCIHostState *host_bridge; =20 - QLIST_FOREACH(host_bridge, &pci_host_bridges, next) { + QTAILQ_FOREACH(host_bridge, &pci_host_bridges, next) { info =3D g_malloc0(sizeof(*info)); info->value =3D qmp_query_pci_bus(host_bridge->bus, pci_bus_num(host_bridge->bus)); @@ -2493,7 +2494,7 @@ int pci_qdev_find_device(const char *id, PCIDevice **= pdev) PCIHostState *host_bridge; int rc =3D -ENODEV; =20 - QLIST_FOREACH(host_bridge, &pci_host_bridges, next) { + QTAILQ_FOREACH(host_bridge, &pci_host_bridges, next) { int tmp =3D pci_qdev_find_recursive(host_bridge->bus, id, pdev); if (!tmp) { rc =3D 0; diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index 6894f37..7955ef9 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -209,6 +209,7 @@ void pc_memory_init(PCMachineState *pcms, MemoryRegion *rom_memory, MemoryRegion **ram_memory); uint64_t pc_pci_hole64_start(void); +uint64_t pc_pci_mcfg_start(void); qemu_irq pc_allocate_cpu_irq(void); DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus); void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, diff --git a/include/hw/pci-bridge/pci_expander_bridge.h b/include/hw/pci-b= ridge/pci_expander_bridge.h new file mode 100644 index 0000000..870c4cd --- /dev/null +++ b/include/hw/pci-bridge/pci_expander_bridge.h @@ -0,0 +1,11 @@ +#ifndef HW_PCI_EXPANDER_H +#define HW_PCI_EXPANDER_H + +#define PROP_PXB_PCIE_DEV "pxbdev" + +#define PROP_PXB_PCIE_DOMAIN_NR "domain_nr" +#define PROP_PXB_BUS_NR "bus_nr" + +uint64_t pxb_pcie_mcfg_hole(void); + +#endif diff --git a/include/hw/pci-host/q35.h b/include/hw/pci-host/q35.h index 8f4ddde..432e569 100644 --- a/include/hw/pci-host/q35.h +++ b/include/hw/pci-host/q35.h @@ -69,6 +69,7 @@ typedef struct Q35PCIHost { /*< public >*/ =20 bool pci_hole64_fix; + uint32_t domain_nr; MCHPCIState mch; } Q35PCIHost; =20 diff --git a/include/hw/pci/pci_host.h b/include/hw/pci/pci_host.h index ba31595..a5617cf 100644 --- a/include/hw/pci/pci_host.h +++ b/include/hw/pci/pci_host.h @@ -47,7 +47,7 @@ struct PCIHostState { uint32_t config_reg; PCIBus *bus; =20 - QLIST_ENTRY(PCIHostState) next; + QTAILQ_ENTRY(PCIHostState) next; }; =20 typedef struct PCIHostBridgeClass { --=20 2.7.4 From nobody Wed Nov 5 05:11:01 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; 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X-Received-From: 2a00:1450:400c:c09::243 Subject: [Qemu-devel] [RFC v3 3/6] i386/acpi-build: describe new pci domain in AML X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Zihan Yang Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Describe new pci segments of host bridges in AML as new pci devices, with _SEG and _BBN to let them be in DSDT Signed-off-by: Zihan Yang --- hw/i386/acpi-build.c | 78 +++++++++++++++++++++++++++++++++++-------------= ---- 1 file changed, 53 insertions(+), 25 deletions(-) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 30bd0d5..4b6ef78 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -1832,6 +1832,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, aml_append(dev, aml_name_decl("_UID", aml_int(1))); aml_append(dev, build_q35_osc_method()); aml_append(sb_scope, dev); + aml_append(dsdt, sb_scope); =20 build_hpet_aml(dsdt); @@ -1875,6 +1876,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, =20 crs_range_set_init(&crs_range_set); bus =3D PC_MACHINE(machine)->bus; + i =3D 1; // PCI0 is q35 host, pxb starts from 1 if (bus) { QLIST_FOREACH(bus, &bus->child, sibling) { uint8_t bus_num =3D pci_bus_num(bus); @@ -1890,10 +1892,9 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, } =20 scope =3D aml_scope("\\_SB"); - dev =3D aml_device("PC%.02X", bus_num); + dev =3D aml_device("PCI%d", i++); aml_append(dev, aml_name_decl("_UID", aml_int(bus_num))); aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); - aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num))); if (pci_bus_is_express(bus)) { aml_append(dev, build_q35_osc_method()); } @@ -2125,36 +2126,63 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, sb_scope =3D aml_scope("\\_SB"); { Object *pci_host; + QObject *o; PCIBus *bus =3D NULL; + uint32_t domain_nr; + uint8_t bus_nr; + int index =3D 0; =20 pci_host =3D acpi_get_i386_pci_host(); - if (pci_host) { + while (pci_host) { + Object *obj =3D object_property_get_link(pci_host, + PROP_PXB_PCIE_DEV, NULL); + if (!obj) { + /* we are in q35 host */ + obj =3D pci_host; + } + o =3D object_property_get_qobject(obj, PROP_PXB_PCIE_DOMAIN_NR= , NULL); + assert(o); + domain_nr =3D qnum_get_uint(qobject_to(QNum, o)); + qobject_unref(o); + + o =3D object_property_get_qobject(pci_host, "bus_nr", NULL); + if (!o) { + /* we are in q35 host */ + bus_nr =3D 0; + } else { + bus_nr =3D qnum_get_uint(qobject_to(QNum, o)); + qobject_unref(o); + } + bus =3D PCI_HOST_BRIDGE(pci_host)->bus; - } + if (bus) { + Aml *scope =3D aml_scope("PCI%d", index); + aml_append(scope, aml_name_decl("_SEG", aml_int(domain_nr)= )); + aml_append(scope, aml_name_decl("_BBN", aml_int(bus_nr))); + /* Scan all PCI buses. Generate tables to support hotplug.= */ + build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_= en); =20 - if (bus) { - Aml *scope =3D aml_scope("PCI0"); - /* Scan all PCI buses. Generate tables to support hotplug. */ - build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en); + /* Only add TPM once */ + if (index++ =3D=3D 0 && TPM_IS_TIS(tpm_find())) { + dev =3D aml_device("ISA.TPM"); + aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0= C31"))); + aml_append(dev, aml_name_decl("_STA", aml_int(0xF))); + crs =3D aml_resource_template(); + aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, + TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); + /* + FIXME: TPM_TIS_IRQ=3D5 conflicts with PNP0C0F irqs, + Rewrite to take IRQ from TPM device model and + fix default IRQ value there to use some unused IRQ + */ + /* aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); */ + aml_append(dev, aml_name_decl("_CRS", crs)); + aml_append(scope, dev); + } =20 - if (TPM_IS_TIS(tpm_find())) { - dev =3D aml_device("ISA.TPM"); - aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C31"= ))); - aml_append(dev, aml_name_decl("_STA", aml_int(0xF))); - crs =3D aml_resource_template(); - aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, - TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); - /* - FIXME: TPM_TIS_IRQ=3D5 conflicts with PNP0C0F irqs, - Rewrite to take IRQ from TPM device model and - fix default IRQ value there to use some unused IRQ - */ - /* aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); */ - aml_append(dev, aml_name_decl("_CRS", crs)); - aml_append(scope, dev); + aml_append(sb_scope, scope); } - - aml_append(sb_scope, scope); + pci_host =3D OBJECT(QTAILQ_NEXT(PCI_HOST_BRIDGE(pci_host), nex= t)); } } =20 --=20 2.7.4 From nobody Wed Nov 5 05:11:01 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1533178104501114.40361529226766; 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Wed, 01 Aug 2018 19:43:08 -0700 (PDT) From: Zihan Yang To: qemu-devel@nongnu.org Date: Thu, 2 Aug 2018 10:42:21 +0800 Message-Id: <1533177743-20894-5-git-send-email-whois.zihan.yang@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1533177743-20894-1-git-send-email-whois.zihan.yang@gmail.com> References: <1533177743-20894-1-git-send-email-whois.zihan.yang@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::244 Subject: [Qemu-devel] [RFC v3 4/6] pci_expander_bridge: Add config_read callback X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Zihan Yang Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This allows SeaBIOS to retrieve MCFG base and size when it initializes pxb host bridges. A backlink to PXBPCIEHost is added in PXBDev to achieve above goal Signed-off-by: Zihan Yang --- hw/pci-bridge/pci_expander_bridge.c | 55 +++++++++++++++++++++++++= ++++ include/hw/pci-bridge/pci_expander_bridge.h | 1 + 2 files changed, 56 insertions(+) diff --git a/hw/pci-bridge/pci_expander_bridge.c b/hw/pci-bridge/pci_expand= er_bridge.c index f50938f..cdfdb90 100644 --- a/hw/pci-bridge/pci_expander_bridge.c +++ b/hw/pci-bridge/pci_expander_bridge.c @@ -49,11 +49,18 @@ typedef struct PXBBus { #define PROP_PXB_PCIE_MAX_BUS "max_bus" #define PROP_PXB_NUMA_NODE "numa_node" =20 +typedef struct PXBPCIEHost PXBPCIEHost; +typedef struct PXBDev PXBDev; + typedef struct PXBDev { /*< private >*/ PCIDevice parent_obj; /*< public >*/ =20 + /* backlink to PXBPCIEHost, this makes it easier to get + * mcfg properties in pxb-pcie-host bridge */ + PXBPCIEHost *pxbhost; + uint32_t domain_nr; /* PCI domain number, non-zero means separate doma= in */ uint8_t max_bus; /* max bus number to use(including this one) */ uint8_t bus_nr; @@ -342,9 +349,15 @@ static void pxb_dev_realize_common(PCIDevice *dev, boo= l pcie, Error **errp) if (pcie) { g_assert (pxb->max_bus >=3D pxb->bus_nr); ds =3D qdev_create(NULL, TYPE_PXB_PCIE_HOST); + /* attach it under /machine, so that we can resolve a valid path in + * object_property_set_link below */ + object_property_add_child(qdev_get_machine(), "pxb-pcie-host[*]", = OBJECT(ds), NULL); =20 + /* set link and backlink between PXBPCIEHost and PXBDev */ object_property_set_link(OBJECT(ds), OBJECT(pxb), PROP_PXB_PCIE_DEV, errp); + object_property_set_link(OBJECT(pxb), OBJECT(ds), + PROP_PXB_PCIE_HOST, errp); =20 /* will be overwritten by firmware, but kept for readability */ qdev_prop_set_uint64(ds, PCIE_HOST_MCFG_BASE, @@ -413,6 +426,36 @@ static void pxb_dev_exitfn(PCIDevice *pci_dev) pxb_dev_list =3D g_list_remove(pxb_dev_list, pxb); } =20 +static uint32_t pxb_pcie_config_read(PCIDevice *d, uint32_t address, int l= en) +{ + PXBDev *pxb =3D convert_to_pxb(d); + uint32_t val; + Object *host; + + switch (address) { + case MCH_HOST_BRIDGE_PCIEXBAR: + host =3D object_property_get_link(OBJECT(pxb), PROP_PXB_PCIE_HOST,= NULL); + assert(host); + val =3D object_property_get_uint(host, PCIE_HOST_MCFG_BASE, NULL) = & 0xFFFFFFFF; + break; + case MCH_HOST_BRIDGE_PCIEXBAR + 4: + host =3D object_property_get_link(OBJECT(pxb), PROP_PXB_PCIE_HOST,= NULL); + assert(host); + val =3D (object_property_get_uint(host, PCIE_HOST_MCFG_BASE, NULL)= >> 32) & 0xFFFFFFFF; + break; + case MCH_HOST_BRIDGE_PCIEXBAR + 8: // Fix me! + host =3D object_property_get_link(OBJECT(pxb), PROP_PXB_PCIE_HOST,= NULL); + assert(host); + val =3D object_property_get_uint(host, PCIE_HOST_MCFG_SIZE, NULL) = & 0xFFFFFFFF; + break; + default: + val =3D pci_default_read_config(d, address, len); + break; + } + + return val; +} + static Property pxb_dev_properties[] =3D { /* Note: 0 is not a legal PXB bus number. */ DEFINE_PROP_UINT8(PROP_PXB_BUS_NR, PXBDev, bus_nr, 0), @@ -447,6 +490,16 @@ static void pxb_dev_class_init(ObjectClass *klass, voi= d *data) set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); } =20 +static void pxb_pcie_dev_initfn(Object *obj) +{ + PXBDev *pxb =3D PXB_PCIE_DEV(obj); + + /* Add backlink to pxb-pcie-host */ + object_property_add_link(obj, PROP_PXB_PCIE_HOST, TYPE_PXB_PCIE_HOST, + (Object **)&pxb->pxbhost, + qdev_prop_allow_set_link_before_realize, 0, NULL); +} + static const TypeInfo pxb_dev_info =3D { .name =3D TYPE_PXB_DEVICE, .parent =3D TYPE_PCI_DEVICE, @@ -478,6 +531,7 @@ static void pxb_pcie_dev_class_init(ObjectClass *klass,= void *data) =20 k->realize =3D pxb_pcie_dev_realize; k->exit =3D pxb_dev_exitfn; + k->config_read =3D pxb_pcie_config_read; k->vendor_id =3D PCI_VENDOR_ID_REDHAT; k->device_id =3D PCI_DEVICE_ID_REDHAT_PXB_PCIE; k->class_id =3D PCI_CLASS_BRIDGE_HOST; @@ -492,6 +546,7 @@ static const TypeInfo pxb_pcie_dev_info =3D { .name =3D TYPE_PXB_PCIE_DEVICE, .parent =3D TYPE_PCI_DEVICE, .instance_size =3D sizeof(PXBDev), + .instance_init =3D pxb_pcie_dev_initfn, .class_init =3D pxb_pcie_dev_class_init, .interfaces =3D (InterfaceInfo[]) { { INTERFACE_CONVENTIONAL_PCI_DEVICE }, diff --git a/include/hw/pci-bridge/pci_expander_bridge.h b/include/hw/pci-b= ridge/pci_expander_bridge.h index 870c4cd..1119210 100644 --- a/include/hw/pci-bridge/pci_expander_bridge.h +++ b/include/hw/pci-bridge/pci_expander_bridge.h @@ -2,6 +2,7 @@ #define HW_PCI_EXPANDER_H =20 #define PROP_PXB_PCIE_DEV "pxbdev" +#define PROP_PXB_PCIE_HOST "x-pxb-host" =20 #define PROP_PXB_PCIE_DOMAIN_NR "domain_nr" #define PROP_PXB_BUS_NR "bus_nr" --=20 2.7.4 From nobody Wed Nov 5 05:11:01 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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X-Received-From: 2a00:1450:400c:c09::241 Subject: [Qemu-devel] [RFC v3 5/6] pci_expander_bridge: Add ioport for pxb host bus X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Zihan Yang Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This enables seabios to read config file in pxb host bus other than sysbus Signed-off-by: Zihan Yang --- hw/pci-bridge/pci_expander_bridge.c | 15 +++++++++++++++ include/hw/pci-bridge/pci_expander_bridge.h | 3 +++ 2 files changed, 18 insertions(+) diff --git a/hw/pci-bridge/pci_expander_bridge.c b/hw/pci-bridge/pci_expand= er_bridge.c index cdfdb90..38212db 100644 --- a/hw/pci-bridge/pci_expander_bridge.c +++ b/hw/pci-bridge/pci_expander_bridge.c @@ -226,6 +226,20 @@ static void pxb_pcie_host_initfn(Object *obj) qdev_prop_allow_set_link_before_realize, 0, NULL); } =20 +static void pxb_pcie_host_realize(DeviceState *dev, Error **errp) +{ + PCIHostState *pci =3D PCI_HOST_BRIDGE(dev); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); + + // FIX ME! Use specific port number for pxb-pcie host bridge, not scal= able! + /* port layout is | pxb1_cmd | pxb1_data | pxb2_cmd | pxb2_data | ... = | */ + sysbus_add_io(sbd, PXB_PCIE_HOST_BRIDGE_CONFIG_ADDR_BASE, &pci->conf_m= em); + sysbus_init_ioports(sbd, PXB_PCIE_HOST_BRIDGE_CONFIG_ADDR_BASE + g_lis= t_length(pxb_dev_list) * 8, 4); + + sysbus_add_io(sbd, PXB_PCIE_HOST_BRIDGE_CONFIG_DATA_BASE, &pci->data_m= em); + sysbus_init_ioports(sbd, PXB_PCIE_HOST_BRIDGE_CONFIG_DATA_BASE + g_lis= t_length(pxb_dev_list) * 8, 4); +} + static Property pxb_pcie_host_props[] =3D { DEFINE_PROP_UINT64(PCIE_HOST_MCFG_BASE, PXBPCIEHost, parent_obj.base_a= ddr, PCIE_BASE_ADDR_UNMAPPED), @@ -254,6 +268,7 @@ static void pxb_pcie_host_class_init(ObjectClass *class= , void *data) =20 dc->fw_name =3D "pcie"; dc->props =3D pxb_pcie_host_props; + dc->realize =3D pxb_pcie_host_realize; /* Reason: Internal part of the pxb/pxb-pcie device, not usable by its= elf */ dc->user_creatable =3D false; sbc->explicit_ofw_unit_address =3D pxb_host_ofw_unit_address; diff --git a/include/hw/pci-bridge/pci_expander_bridge.h b/include/hw/pci-b= ridge/pci_expander_bridge.h index 1119210..e6d3b67 100644 --- a/include/hw/pci-bridge/pci_expander_bridge.h +++ b/include/hw/pci-bridge/pci_expander_bridge.h @@ -7,6 +7,9 @@ #define PROP_PXB_PCIE_DOMAIN_NR "domain_nr" #define PROP_PXB_BUS_NR "bus_nr" =20 +#define PXB_PCIE_HOST_BRIDGE_CONFIG_ADDR_BASE 0x1000 +#define PXB_PCIE_HOST_BRIDGE_CONFIG_DATA_BASE 0x1004 + uint64_t pxb_pcie_mcfg_hole(void); =20 #endif --=20 2.7.4 From nobody Wed Nov 5 05:11:01 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1533178288008841.1064807585519; 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Wed, 01 Aug 2018 19:43:15 -0700 (PDT) From: Zihan Yang To: qemu-devel@nongnu.org Date: Thu, 2 Aug 2018 10:42:23 +0800 Message-Id: <1533177743-20894-7-git-send-email-whois.zihan.yang@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1533177743-20894-1-git-send-email-whois.zihan.yang@gmail.com> References: <1533177743-20894-1-git-send-email-whois.zihan.yang@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 Subject: [Qemu-devel] [RFC v3 6/6] pci_expander_bridge: add start_bus property X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Zihan Yang Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The former bus_nr property indicates the bus number of pxb-pcie device on pcie.0 bus, not the Base Bus Number of pxb-pcie host bridge. Use start_bus property to represent this BBN when building acpi table Signed-off-by: Zihan Yang --- hw/i386/acpi-build.c | 22 +++++++++++----------- hw/pci-bridge/pci_expander_bridge.c | 25 ++++++++++++++----------- include/hw/pci-bridge/pci_expander_bridge.h | 2 +- 3 files changed, 26 insertions(+), 23 deletions(-) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 4b6ef78..874e0fa 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -91,7 +91,7 @@ typedef struct AcpiMcfgInfo { uint64_t mcfg_base; uint32_t mcfg_size; uint32_t domain_nr; - uint8_t bus_nr; // start bus number + uint8_t start_bus; // start bus number struct AcpiMcfgInfo *next; } AcpiMcfgInfo; =20 @@ -2129,7 +2129,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, QObject *o; PCIBus *bus =3D NULL; uint32_t domain_nr; - uint8_t bus_nr; + uint8_t start_bus; int index =3D 0; =20 pci_host =3D acpi_get_i386_pci_host(); @@ -2145,12 +2145,12 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, domain_nr =3D qnum_get_uint(qobject_to(QNum, o)); qobject_unref(o); =20 - o =3D object_property_get_qobject(pci_host, "bus_nr", NULL); + o =3D object_property_get_qobject(pci_host, "start_bus", NULL); if (!o) { /* we are in q35 host */ - bus_nr =3D 0; + start_bus =3D 0; } else { - bus_nr =3D qnum_get_uint(qobject_to(QNum, o)); + start_bus =3D qnum_get_uint(qobject_to(QNum, o)); qobject_unref(o); } =20 @@ -2158,7 +2158,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, if (bus) { Aml *scope =3D aml_scope("PCI%d", index); aml_append(scope, aml_name_decl("_SEG", aml_int(domain_nr)= )); - aml_append(scope, aml_name_decl("_BBN", aml_int(bus_nr))); + aml_append(scope, aml_name_decl("_BBN", aml_int(start_bus)= )); /* Scan all PCI buses. Generate tables to support hotplug.= */ build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_= en); =20 @@ -2486,8 +2486,8 @@ build_mcfg_q35(GArray *table_data, BIOSLinker *linker= , AcpiMcfgInfo *info) while (info) { mcfg[count].allocation[0].address =3D cpu_to_le64(info->mcfg_base); mcfg[count].allocation[0].pci_segment =3D cpu_to_le16(info->domain= _nr); - mcfg[count].allocation[0].start_bus_number =3D info->bus_nr; - mcfg[count++].allocation[0].end_bus_number =3D info->bus_nr + \ + mcfg[count].allocation[0].start_bus_number =3D info->start_bus; + mcfg[count++].allocation[0].end_bus_number =3D info->start_bus + \ PCIE_MMCFG_BUS(info->mcfg_size - 1); info =3D info->next; } @@ -2710,12 +2710,12 @@ static AcpiMcfgInfo *acpi_get_mcfg(void) mcfg->mcfg_size =3D qnum_get_uint(qobject_to(QNum, o)); qobject_unref(o); =20 - o =3D object_property_get_qobject(obj, PROP_PXB_BUS_NR, NULL); + o =3D object_property_get_qobject(obj, PROP_PXB_PCIE_START_BUS, NU= LL); if (!o) { /* we are in q35 host again */ - mcfg->bus_nr =3D 0; + mcfg->start_bus =3D 0; } else { - mcfg->bus_nr =3D qnum_get_uint(qobject_to(QNum, o)); + mcfg->start_bus =3D qnum_get_uint(qobject_to(QNum, o)); qobject_unref(o); } =20 diff --git a/hw/pci-bridge/pci_expander_bridge.c b/hw/pci-bridge/pci_expand= er_bridge.c index 38212db..85630ff 100644 --- a/hw/pci-bridge/pci_expander_bridge.c +++ b/hw/pci-bridge/pci_expander_bridge.c @@ -46,6 +46,7 @@ typedef struct PXBBus { #define TYPE_PXB_PCIE_DEVICE "pxb-pcie" #define PXB_PCIE_DEV(obj) OBJECT_CHECK(PXBDev, (obj), TYPE_PXB_PCIE_DEVICE) =20 +#define PROP_PXB_BUS_NR "bus_nr" #define PROP_PXB_PCIE_MAX_BUS "max_bus" #define PROP_PXB_NUMA_NODE "numa_node" =20 @@ -62,8 +63,9 @@ typedef struct PXBDev { PXBPCIEHost *pxbhost; =20 uint32_t domain_nr; /* PCI domain number, non-zero means separate doma= in */ + uint8_t start_bus; /* indicates the BBN of pxb-pcie-host bridge */ uint8_t max_bus; /* max bus number to use(including this one) */ - uint8_t bus_nr; + uint8_t bus_nr; /* bus number of pxb-pcie device on pcei.0 bus */ uint16_t numa_node; } PXBDev; =20 @@ -137,8 +139,8 @@ static void pxb_pcie_foreach(gpointer data, gpointer us= er_data) =20 if (pxb->domain_nr > 0) { /* only reserve what users ask for to reduce memory cost. Plus one - * as the interval [bus_nr, max_bus] has (max_bus-bus_nr+1) buses = */ - pxb_mcfg_hole_size +=3D ((pxb->max_bus - pxb->bus_nr + 1ULL) * MiB= ); + * as the interval [start_bus, max_bus] has (max_bus-start_bus+1) = buses */ + pxb_mcfg_hole_size +=3D ((pxb->max_bus - pxb->start_bus + 1ULL) * = MiB); } } =20 @@ -333,11 +335,11 @@ static gint pxb_compare(gconstpointer a, gconstpointe= r b) { const PXBDev *pxb_a =3D a, *pxb_b =3D b; =20 - /* check domain_nr, then bus_nr */ + /* check domain_nr, then start_bus */ return pxb_a->domain_nr < pxb_b->domain_nr ? -1 : pxb_a->domain_nr > pxb_b->domain_nr ? 1 : - pxb_a->bus_nr < pxb_b->bus_nr ? -1 : - pxb_a->bus_nr > pxb_b->bus_nr ? 1 : + pxb_a->start_bus < pxb_b->start_bus ? -1 : + pxb_a->start_bus > pxb_b->start_bus ? 1 : 0; } =20 @@ -362,7 +364,7 @@ static void pxb_dev_realize_common(PCIDevice *dev, bool= pcie, Error **errp) } =20 if (pcie) { - g_assert (pxb->max_bus >=3D pxb->bus_nr); + g_assert (pxb->max_bus >=3D pxb->start_bus); ds =3D qdev_create(NULL, TYPE_PXB_PCIE_HOST); /* attach it under /machine, so that we can resolve a valid path in * object_property_set_link below */ @@ -377,9 +379,9 @@ static void pxb_dev_realize_common(PCIDevice *dev, bool= pcie, Error **errp) /* will be overwritten by firmware, but kept for readability */ qdev_prop_set_uint64(ds, PCIE_HOST_MCFG_BASE, pxb->domain_nr ? pxb_pcie_mcfg_base : MCH_HOST_BRIDGE_PCIEXBAR= _DEFAULT); - /* +1 because [bus_nr, max_bus] has (max_bus-bus_nr+1) buses */ + /* +1 because [start_bus, max_bus] has (max_bus-start_bus+1) buses= */ qdev_prop_set_uint64(ds, PCIE_HOST_MCFG_SIZE, - pxb->domain_nr ? (pxb->max_bus - pxb->bus_nr + 1ULL) * MiB : 0= ); + pxb->domain_nr ? (pxb->max_bus - pxb->start_bus + 1ULL) * MiB = : 0); if (pxb->domain_nr) pxb_pcie_mcfg_base +=3D ((pxb->max_bus + 1ULL) * MiB); =20 @@ -389,7 +391,7 @@ static void pxb_dev_realize_common(PCIDevice *dev, bool= pcie, Error **errp) bus =3D pci_root_bus_new(ds, "pxb-internal", NULL, NULL, 0, TYPE_P= XB_BUS); bds =3D qdev_create(BUS(bus), "pci-bridge"); bds->id =3D dev_name; - qdev_prop_set_uint8(bds, PCI_BRIDGE_DEV_PROP_CHASSIS_NR, pxb->bus_= nr); + qdev_prop_set_uint8(bds, PCI_BRIDGE_DEV_PROP_CHASSIS_NR, pxb->star= t_bus); qdev_prop_set_bit(bds, PCI_BRIDGE_DEV_PROP_SHPC, false); } =20 @@ -482,7 +484,8 @@ static Property pxb_pcie_dev_properties[] =3D { DEFINE_PROP_UINT8(PROP_PXB_BUS_NR, PXBDev, bus_nr, 0), DEFINE_PROP_UINT16(PROP_PXB_NUMA_NODE, PXBDev, numa_node, NUMA_NODE_UN= ASSIGNED), DEFINE_PROP_UINT32(PROP_PXB_PCIE_DOMAIN_NR, PXBDev, domain_nr, 0), - /* set a small default value, bus interval is [bus_nr, max_bus] */ + DEFINE_PROP_UINT8(PROP_PXB_PCIE_START_BUS, PXBDev, start_bus, 0), + /* set a small default value, bus interval is [start_bus, max_bus] */ DEFINE_PROP_UINT8(PROP_PXB_PCIE_MAX_BUS, PXBDev, max_bus, 16), =20 DEFINE_PROP_END_OF_LIST(), diff --git a/include/hw/pci-bridge/pci_expander_bridge.h b/include/hw/pci-b= ridge/pci_expander_bridge.h index e6d3b67..54b050c 100644 --- a/include/hw/pci-bridge/pci_expander_bridge.h +++ b/include/hw/pci-bridge/pci_expander_bridge.h @@ -5,7 +5,7 @@ #define PROP_PXB_PCIE_HOST "x-pxb-host" =20 #define PROP_PXB_PCIE_DOMAIN_NR "domain_nr" -#define PROP_PXB_BUS_NR "bus_nr" +#define PROP_PXB_PCIE_START_BUS "start_bus" =20 #define PXB_PCIE_HOST_BRIDGE_CONFIG_ADDR_BASE 0x1000 #define PXB_PCIE_HOST_BRIDGE_CONFIG_DATA_BASE 0x1004 --=20 2.7.4