From nobody Wed Nov 5 05:25:08 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1532971319771476.5881165289535; Mon, 30 Jul 2018 10:21:59 -0700 (PDT) Received: from localhost ([::1]:53920 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fkBlq-00038N-JC for importer@patchew.org; Mon, 30 Jul 2018 13:15:46 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37539) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fkAz9-0001q3-SA for qemu-devel@nongnu.org; Mon, 30 Jul 2018 12:25:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fkAz7-0001OE-2Q for qemu-devel@nongnu.org; Mon, 30 Jul 2018 12:25:27 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:40066 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fkAz6-0001Nl-N6 for qemu-devel@nongnu.org; Mon, 30 Jul 2018 12:25:25 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 729381A1FEF; Mon, 30 Jul 2018 18:25:23 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 4E9D91A1E6F; Mon, 30 Jul 2018 18:25:23 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Mon, 30 Jul 2018 18:12:18 +0200 Message-Id: <1532967169-22265-46-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1532967169-22265-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1532967169-22265-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v5 45/76] target/mips: Implement emulation of nanoMIPS LLWP/SCWP pair X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pburton@wavecomp.com, smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, philippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Rikalo Implement nanoMIPS LLWP and SCWP instruction pair. Signed-off-by: Dimitrije Nikolic Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic --- linux-user/mips/cpu_loop.c | 25 +++++++++++--- target/mips/cpu.h | 2 ++ target/mips/helper.h | 2 ++ target/mips/op_helper.c | 35 ++++++++++++++++++++ target/mips/translate.c | 81 ++++++++++++++++++++++++++++++++++++++++++= ++++ 5 files changed, 140 insertions(+), 5 deletions(-) diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c index 084ad6a..1d3dc9e 100644 --- a/linux-user/mips/cpu_loop.c +++ b/linux-user/mips/cpu_loop.c @@ -397,10 +397,13 @@ static int do_store_exclusive(CPUMIPSState *env) target_ulong addr; target_ulong page_addr; target_ulong val; + uint32_t val_wp =3D 0; + uint32_t llnewval_wp =3D 0; int flags; int segv =3D 0; int reg; int d; + int wp; =20 addr =3D env->lladdr; page_addr =3D addr & TARGET_PAGE_MASK; @@ -412,19 +415,31 @@ static int do_store_exclusive(CPUMIPSState *env) } else { reg =3D env->llreg & 0x1f; d =3D (env->llreg & 0x20) !=3D 0; - if (d) { - segv =3D get_user_s64(val, addr); + wp =3D (env->llreg & 0x40) !=3D 0; + if (!wp) { + if (d) { + segv =3D get_user_s64(val, addr); + } else { + segv =3D get_user_s32(val, addr); + } } else { segv =3D get_user_s32(val, addr); + segv |=3D get_user_s32(val_wp, addr); + llnewval_wp =3D env->llnewval_wp; } if (!segv) { - if (val !=3D env->llval) { + if (val !=3D env->llval && val_wp =3D=3D llnewval_wp) { env->active_tc.gpr[reg] =3D 0; } else { - if (d) { - segv =3D put_user_u64(env->llnewval, addr); + if (!wp) { + if (d) { + segv =3D put_user_u64(env->llnewval, addr); + } else { + segv =3D put_user_u32(env->llnewval, addr); + } } else { segv =3D put_user_u32(env->llnewval, addr); + segv |=3D put_user_u32(env->llnewval_wp, addr + 4); } if (!segv) { env->active_tc.gpr[reg] =3D 1; diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 009202c..28af4d1 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -506,6 +506,8 @@ struct CPUMIPSState { uint64_t lladdr; target_ulong llval; target_ulong llnewval; + uint64_t llval_wp; + uint32_t llnewval_wp; target_ulong llreg; uint64_t CP0_LLAddr_rw_bitmask; int CP0_LLAddr_shift; diff --git a/target/mips/helper.h b/target/mips/helper.h index b2a780a..deca307 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -14,6 +14,8 @@ DEF_HELPER_4(swr, void, env, tl, tl, int) #ifndef CONFIG_USER_ONLY DEF_HELPER_3(ll, tl, env, tl, int) DEF_HELPER_4(sc, tl, env, tl, tl, int) +DEF_HELPER_5(llwp, void, env, tl, i32, i32, i32) +DEF_HELPER_4(scwp, tl, env, tl, i64, int) #ifdef TARGET_MIPS64 DEF_HELPER_3(lld, tl, env, tl, int) DEF_HELPER_4(scd, tl, env, tl, tl, int) diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index b3eef9f..cb83b6d 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -380,6 +380,19 @@ HELPER_LD_ATOMIC(lld, ld, 0x7) #endif #undef HELPER_LD_ATOMIC =20 +void helper_llwp(CPUMIPSState *env, target_ulong addr, uint32_t reg1, + uint32_t reg2, uint32_t mem_idx) +{ + if (addr & 0x7) { + env->CP0_BadVAddr =3D addr; + do_raise_exception(env, EXCP_AdEL, GETPC()); + } + env->lladdr =3D do_translate_address(env, addr, 0, GETPC()); + env->active_tc.gpr[reg1] =3D env->llval =3D do_lw(env, addr, mem_idx, = GETPC()); + env->active_tc.gpr[reg2] =3D env->llval_wp =3D do_lw(env, addr + 4, me= m_idx, + GETPC()); +} + #define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask) = \ target_ulong helper_##name(CPUMIPSState *env, target_ulong arg1, = \ target_ulong arg2, int mem_idx) = \ @@ -406,6 +419,28 @@ HELPER_ST_ATOMIC(sc, lw, sw, 0x3) HELPER_ST_ATOMIC(scd, ld, sd, 0x7) #endif #undef HELPER_ST_ATOMIC + +target_ulong helper_scwp(CPUMIPSState *env, target_ulong addr, + uint64_t data, int mem_idx) +{ + uint32_t tmp; + uint32_t tmp2; + + if (addr & 0x7) { + env->CP0_BadVAddr =3D addr; + do_raise_exception(env, EXCP_AdES, GETPC()); + } + if (do_translate_address(env, addr, 1, GETPC()) =3D=3D env->lladdr) { + tmp =3D do_lw(env, addr, mem_idx, GETPC()); + tmp2 =3D do_lw(env, addr + 4, mem_idx, GETPC()); + if (tmp =3D=3D env->llval && tmp2 =3D=3D env->llval_wp) { + do_sw(env, addr, (uint32_t) data, mem_idx, GETPC()); + do_sw(env, addr + 4, (uint32_t) *(&data + 4), mem_idx, GETPC()= ); + return 1; + } + } + return 0; +} #endif =20 #ifdef TARGET_WORDS_BIGENDIAN diff --git a/target/mips/translate.c b/target/mips/translate.c index ea6fdeb..c4b6a26 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1459,6 +1459,7 @@ typedef struct DisasContext { bool nan2008; bool abs2008; bool has_isa_mode; + bool xnp; } DisasContext; =20 #define DISAS_STOP DISAS_TARGET_0 @@ -2348,6 +2349,31 @@ static void gen_ld(DisasContext *ctx, uint32_t opc, tcg_temp_free(t0); } =20 +static void gen_llwp(DisasContext *ctx, uint32_t base, int16_t offset, + uint32_t reg1, uint32_t reg2) +{ + TCGv taddr =3D tcg_temp_new(); + TCGv_i64 tval =3D tcg_temp_new_i64(); + TCGv tmp1 =3D tcg_temp_new(); + TCGv tmp2 =3D tcg_temp_new(); + + gen_base_offset_addr(ctx, taddr, base, offset); + tcg_gen_qemu_ld64(tval, taddr, ctx->mem_idx); +#ifdef TARGET_WORDS_BIGENDIAN + tcg_gen_extr_i64_tl(tmp2, tmp1, tval); +#else + tcg_gen_extr_i64_tl(tmp1, tmp2, tval); +#endif + gen_store_gpr(tmp1, reg1); + tcg_temp_free(tmp1); + gen_store_gpr(tmp2, reg2); + tcg_temp_free(tmp2); + tcg_gen_st_i64(tval, cpu_env, offsetof(CPUMIPSState, llval_wp)); + tcg_temp_free_i64(tval); + tcg_gen_st_tl(taddr, cpu_env, offsetof(CPUMIPSState, lladdr)); + tcg_temp_free(taddr); +} + /* Store */ static void gen_st (DisasContext *ctx, uint32_t opc, int rt, int base, int offset) @@ -2444,6 +2470,48 @@ static void gen_st_cond (DisasContext *ctx, uint32_t= opc, int rt, tcg_temp_free(t0); } =20 +static void gen_scwp(DisasContext *ctx, uint32_t base, int16_t offset, + uint32_t reg1, uint32_t reg2) +{ + TCGv taddr =3D tcg_temp_new(); + TCGv lladdr =3D tcg_temp_new(); + TCGv_i64 tval =3D tcg_temp_new_i64(); + TCGv_i64 llval =3D tcg_temp_new_i64(); + TCGv_i64 val =3D tcg_temp_new_i64(); + TCGv tmp1 =3D tcg_temp_new(); + TCGv tmp2 =3D tcg_temp_new(); + TCGLabel *lab_fail =3D gen_new_label(); + TCGLabel *lab_done =3D gen_new_label(); + + gen_base_offset_addr(ctx, taddr, base, offset); + + tcg_gen_ld_tl(lladdr, cpu_env, offsetof(CPUMIPSState, lladdr)); + tcg_gen_brcond_tl(TCG_COND_NE, taddr, lladdr, lab_fail); + + gen_load_gpr(tmp1, reg1); + gen_load_gpr(tmp2, reg2); + +#ifdef TARGET_WORDS_BIGENDIAN + tcg_gen_concat_tl_i64(tval, tmp2, tmp1); +#else + tcg_gen_concat_tl_i64(tval, tmp1, tmp2); +#endif + + tcg_gen_ld_i64(llval, cpu_env, offsetof(CPUMIPSState, llval_wp)); + tcg_gen_atomic_cmpxchg_i64(val, taddr, llval, tval, + ctx->mem_idx, MO_64); + tcg_gen_movi_tl(cpu_gpr[reg1], 1); + tcg_gen_brcond_i64(TCG_COND_EQ, val, llval, lab_done); + + gen_set_label(lab_fail); + + tcg_gen_movi_tl(cpu_gpr[reg1], 0); + + gen_set_label(lab_done); + tcg_gen_movi_tl(lladdr, -1); + tcg_gen_st_tl(lladdr, cpu_env, offsetof(CPUMIPSState, lladdr)); +} + /* Load and store */ static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft, TCGv t0) @@ -19365,6 +19433,12 @@ static int decode_nanomips_32_48_opc(CPUMIPSState = *env, DisasContext *ctx) gen_ld(ctx, OPC_LL, rt, rs, s); break; case NM_LLWP: + if (ctx->xnp) { + generate_exception_end(ctx, EXCP_RI); + } else { + gen_llwp(ctx, rs, 0, rt, + extract32(ctx->opcode, 3, 5)); + } break; } break; @@ -19374,6 +19448,12 @@ static int decode_nanomips_32_48_opc(CPUMIPSState = *env, DisasContext *ctx) gen_st_cond(ctx, OPC_SC, rt, rs, s); break; case NM_SCWP: + if (ctx->xnp) { + generate_exception_end(ctx, EXCP_RI); + } else { + gen_scwp(ctx, rs, 0, rt, + extract32(ctx->opcode, 3, 5)); + } break; } break; @@ -24683,6 +24763,7 @@ static void mips_tr_init_disas_context(DisasContext= Base *dcbase, CPUState *cs) ctx->nan2008 =3D (env->active_fpu.fcr31 >> FCR31_NAN2008) & 1; ctx->abs2008 =3D (env->active_fpu.fcr31 >> FCR31_ABS2008) & 1; ctx->has_isa_mode =3D ((env->CP0_Config3 >> CP0C3_MMAR) & 0x7) < 3; + ctx->xnp =3D (env->CP0_Config5 >> CP0C5_XNP) & 1; restore_cpu_state(env, ctx); #ifdef CONFIG_USER_ONLY ctx->mem_idx =3D MIPS_HFLAG_UM; --=20 2.7.4