From nobody Wed Nov 5 05:10:59 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 15324544528541004.3114793382614; Tue, 24 Jul 2018 10:47:32 -0700 (PDT) Received: from localhost ([::1]:41769 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fi1PH-0005KO-Pn for importer@patchew.org; Tue, 24 Jul 2018 13:47:31 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41265) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fi1NK-0004JA-Lp for qemu-devel@nongnu.org; Tue, 24 Jul 2018 13:45:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fi1NH-0002mm-I3 for qemu-devel@nongnu.org; Tue, 24 Jul 2018 13:45:30 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:46310 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fi1NH-0002lO-2V for qemu-devel@nongnu.org; Tue, 24 Jul 2018 13:45:27 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 980171A4573; Tue, 24 Jul 2018 19:45:25 +0200 (CEST) Received: from rtrkw774-lin.mipstec.com (unknown [82.117.201.26]) by mail.rt-rk.com (Postfix) with ESMTPSA id 71BA01A44E6; Tue, 24 Jul 2018 19:45:25 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Tue, 24 Jul 2018 19:31:18 +0200 Message-Id: <1532453527-22911-7-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1532453527-22911-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1532453527-22911-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v4 06/55] target/mips: Add emulation of misc nanoMIPS 16-bit instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pburton@wavecomp.com, smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, philippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Yongbok Kim Add emulation of misc nanoMIPS 16-bit instructions from instruction pools P16, P16.BR, P16.BRI, P16.4X4 and other related pools. Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic --- target/mips/translate.c | 260 ++++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 260 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index 2ddc6c9..076637c 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -16512,6 +16512,266 @@ static inline int decode_gpr_gpr4_zero(int r) =20 static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx) { + uint32_t op; + int rt =3D decode_gpr_gpr3(NANOMIPS_EXTRACT_RD(ctx->opcode)); + int rs =3D decode_gpr_gpr3(NANOMIPS_EXTRACT_RS(ctx->opcode)); + int rd =3D decode_gpr_gpr3(NANOMIPS_EXTRACT_RS1(ctx->opcode)); + + /* make sure instructions are on a halfword boundary */ + if (ctx->base.pc_next & 0x1) { + TCGv tmp =3D tcg_const_tl(ctx->base.pc_next); + tcg_gen_st_tl(tmp, cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr)); + tcg_temp_free(tmp); + return 2; + } + + op =3D extract32(ctx->opcode, 10, 6); + switch (op) { + case NM_P16_MV: + { + int rt1 =3D NANOMIPS_EXTRACT_RD5(ctx->opcode); + if (rt1 !=3D 0) { + /* MOVE */ + int rs1 =3D NANOMIPS_EXTRACT_RS5(ctx->opcode); + gen_arith(ctx, OPC_ADDU, rt1, rs1, 0); + } else { + /* P16.RI */ + switch (extract32(ctx->opcode, 3, 2)) { + case NM_P16_SYSCALL: + if (extract32(ctx->opcode, 2, 1) =3D=3D 0) { + generate_exception_end(ctx, EXCP_SYSCALL); + } else { + generate_exception_end(ctx, EXCP_RI); + } + break; + case NM_BREAK16: + generate_exception_end(ctx, EXCP_BREAK); + break; + case NM_SDBBP16: + if (is_uhi(extract32(ctx->opcode, 0, 3))) { + gen_helper_do_semihosting(cpu_env); + } else { + if (ctx->hflags & MIPS_HFLAG_SBRI) { + generate_exception_end(ctx, EXCP_RI); + } else { + generate_exception_end(ctx, EXCP_DBp); + } + } + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } + } + } + break; + case NM_P16_SHIFT: + { + int shift =3D extract32(ctx->opcode, 0, 3); + uint32_t opc =3D 0; + shift =3D (shift =3D=3D 0) ? 8 : shift; + + switch (extract32(ctx->opcode, 3, 1)) { + case NM_SLL16: + opc =3D OPC_SLL; + break; + case NM_SRL16: + opc =3D OPC_SRL; + break; + } + gen_shift_imm(ctx, opc, rt, rs, shift); + } + break; + case NM_P16C: + break; + case NM_P16_A1: + switch (extract32(ctx->opcode, 6, 1)) { + case NM_ADDIUR1SP: + gen_arith_imm(ctx, OPC_ADDIU, rt, 29, + extract32(ctx->opcode, 0, 6) << 2); + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } + break; + case NM_P16_A2: + switch (extract32(ctx->opcode, 3, 1)) { + case NM_ADDIUR2: + { + uint8_t u =3D extract32(ctx->opcode, 0, 3) << 2; + gen_arith_imm(ctx, OPC_ADDIU, rt, rs, u); + } + break; + case NM_P_ADDIURS5: + { + int rt1 =3D extract32(ctx->opcode, 5, 5); + if (rt1 !=3D 0) { + int s =3D (sextract32(ctx->opcode, 4, 1) << 3) | + extract32(ctx->opcode, 0, 3); + /* s =3D sign_extend( s[3] . s[2:0] , from_nbits =3D 4= )*/ + gen_arith_imm(ctx, OPC_ADDIU, rt1, rt1, s); + } + } + break; + } + break; + case NM_P16_ADDU: + switch (ctx->opcode & 0x1) { + case NM_ADDU16: + gen_arith(ctx, OPC_ADDU, rd, rs, rt); + break; + case NM_SUBU16: + gen_arith(ctx, OPC_SUBU, rd, rs, rt); + break; + } + break; + case NM_P16_4X4: + { + int rt1 =3D (extract32(ctx->opcode, 9, 1) << 3) | + extract32(ctx->opcode, 5, 3); + int rs1 =3D (extract32(ctx->opcode, 4, 1) << 3) | + extract32(ctx->opcode, 0, 3); + rt1 =3D decode_gpr_gpr4(rt1); + rs1 =3D decode_gpr_gpr4(rs1); + + switch (((ctx->opcode >> 7) & 0x2) | ((ctx->opcode >> 3) & 0x1= )) { + case NM_ADDU4X4: + gen_arith(ctx, OPC_ADDU, rt1, rs1, rt1); + break; + case NM_MUL4X4: + gen_r6_muldiv(ctx, R6_OPC_MUL, rt1, rs1, rt1); + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } + } + break; + case NM_LI16: + { + int imm =3D extract32(ctx->opcode, 0, 7); + imm =3D (imm =3D=3D 0x7f ? -1 : imm); + if (rt !=3D 0) { + tcg_gen_movi_tl(cpu_gpr[rt], imm); + } + } + break; + case NM_ANDI16: + { + uint32_t u =3D extract32(ctx->opcode, 0, 4); + u =3D (u =3D=3D 12) ? 0xff : + (u =3D=3D 13) ? 0xffff : u; + gen_logic_imm(ctx, OPC_ANDI, rt, rs, u); + } + break; + case NM_P16_LB: + break; + case NM_P16_LH: + break; + case NM_LW16: + break; + case NM_LWSP16: + break; + case NM_LW4X4: + break; + case NM_SW4X4: + break; + case NM_LWGP16: + break; + case NM_SWSP16: + break; + case NM_SW16: + break; + case NM_SWGP16: + break; + case NM_BC16: + gen_compute_branch(ctx, OPC_BEQ, 2, 0, 0, + (sextract32(ctx->opcode, 0, 1) << 10) | + (extract32(ctx->opcode, 1, 9) << 1), 0); + break; + case NM_BALC16: + gen_compute_branch(ctx, OPC_BGEZAL, 2, 0, 0, + (sextract32(ctx->opcode, 0, 1) << 10) | + (extract32(ctx->opcode, 1, 9) << 1), 0); + break; + case NM_BEQZC16: + case NM_BNEZC16: + gen_compute_branch(ctx, op =3D=3D NM_BNEZC16 ? OPC_BNE : OPC_BEQ, = 2, + rt, 0, + (sextract32(ctx->opcode, 0, 1) << 7) | + (extract32(ctx->opcode, 1, 6) << 1), 0); + break; + case NM_P16_BR: + switch (ctx->opcode & 0xf) { + case 0: + /* P16.JRC */ + switch (extract32(ctx->opcode, 4, 1)) { + case NM_JRC: + gen_compute_branch(ctx, OPC_JR, 2, + extract32(ctx->opcode, 5, 5), 0, 0, 0); + break; + case NM_JALRC16: + gen_compute_branch(ctx, OPC_JALR, 2, + extract32(ctx->opcode, 5, 5), 31, 0, 0); + break; + } + break; + default: + /* P16.BRI */ + if (extract32(ctx->opcode, 4, 3) < extract32(ctx->opcode, 7, 3= )) { + /* BEQC16 */ + gen_compute_branch(ctx, OPC_BEQ, 2, rs, rt, + extract32(ctx->opcode, 0, 4) << 1, 0); + } else { + /* BNEC16 */ + gen_compute_branch(ctx, OPC_BNE, 2, rs, rt, + extract32(ctx->opcode, 0, 4) << 1, 0); + } + break; + } + break; + case NM_P16_SR: + break; + case NM_MOVEP: + case NM_MOVEPREV: + { + static const int gpr2reg1[] =3D {4, 5, 6, 7}; + static const int gpr2reg2[] =3D {5, 6, 7, 8}; + int re; + int rd2 =3D extract32(ctx->opcode, 3, 1) << 1 | + extract32(ctx->opcode, 8, 1); + int r1 =3D gpr2reg1[rd2]; + int r2 =3D gpr2reg2[rd2]; + int r3 =3D extract32(ctx->opcode, 4, 1) << 3 | + extract32(ctx->opcode, 0, 3); + int r4 =3D extract32(ctx->opcode, 9, 1) << 3 | + extract32(ctx->opcode, 5, 3); + TCGv t0 =3D tcg_temp_new(); + TCGv t1 =3D tcg_temp_new(); + if (op =3D=3D NM_MOVEP) { + rd =3D r1; + re =3D r2; + rs =3D decode_gpr_gpr4_zero(r3); + rt =3D decode_gpr_gpr4_zero(r4); + } else { + rd =3D decode_gpr_gpr4(r3); + re =3D decode_gpr_gpr4(r4); + rs =3D r1; + rt =3D r2; + } + gen_load_gpr(t0, rs); + gen_load_gpr(t1, rt); + tcg_gen_mov_tl(cpu_gpr[rd], t0); + tcg_gen_mov_tl(cpu_gpr[re], t1); + tcg_temp_free(t0); + tcg_temp_free(t1); + } + break; + default: + break; + } + return 2; } =20 --=20 2.7.4