From nobody Wed Nov 5 06:42:37 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1532456832426315.018077955305; Tue, 24 Jul 2018 11:27:12 -0700 (PDT) Received: from localhost ([::1]:42001 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fi21f-0000ya-Ac for importer@patchew.org; Tue, 24 Jul 2018 14:27:11 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53768) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fi1ew-00057i-E1 for qemu-devel@nongnu.org; Tue, 24 Jul 2018 14:03:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fi1er-0004jl-IF for qemu-devel@nongnu.org; Tue, 24 Jul 2018 14:03:42 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:57355 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fi1er-0004iY-Ab for qemu-devel@nongnu.org; Tue, 24 Jul 2018 14:03:37 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 1F49F1A44EA; Tue, 24 Jul 2018 20:03:36 +0200 (CEST) Received: from rtrkw774-lin.mipstec.com (unknown [82.117.201.26]) by mail.rt-rk.com (Postfix) with ESMTPSA id 003841A1DCE; Tue, 24 Jul 2018 20:03:35 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Tue, 24 Jul 2018 19:31:53 +0200 Message-Id: <1532453527-22911-42-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1532453527-22911-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1532453527-22911-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v4 41/55] target/mips: Add definition of nanoMIPS I7200 CPU X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pburton@wavecomp.com, smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, philippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Stefan Markovic Add definition of the first nanoMIPS processor in QEMU. Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic --- target/mips/translate_init.inc.c | 40 ++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 40 insertions(+) diff --git a/target/mips/translate_init.inc.c b/target/mips/translate_init.= inc.c index c7ba6ee..d3f32e8 100644 --- a/target/mips/translate_init.inc.c +++ b/target/mips/translate_init.inc.c @@ -449,6 +449,46 @@ const mips_def_t mips_defs[] =3D .insn_flags =3D CPU_MIPS32R6 | ASE_MICROMIPS, .mmu_type =3D MMU_TYPE_R4000, }, + { + .name =3D "I7200", + .CP0_PRid =3D 0x00010000, + .CP0_Config0 =3D MIPS_CONFIG0 | (1 << CP0C0_MM) | (0x2 << CP0C0_AR= ) | + (MMU_TYPE_R4000 << CP0C0_MT), + .CP0_Config1 =3D (1U << CP0C1_M) | (15 << CP0C1_MMU) | (2 << CP0C1= _IS) | + (4 << CP0C1_IL) | (3 << CP0C1_IA) | (2 << CP0C1_DS)= | + (4 << CP0C1_DL) | (3 << CP0C1_DA) | (1 << CP0C1_PC)= | + (1 << CP0C1_EP), + .CP0_Config2 =3D MIPS_CONFIG2, + .CP0_Config3 =3D MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_CMGC= R) | + (1 << CP0C3_BI) | (1 << CP0C3_SC) | (3 << CP0C3_MMA= R) | + (1 << CP0C3_ISA_ON_EXC) | (1 << CP0C3_ISA) | + (1 << CP0C3_ULRI) | (1 << CP0C3_RXI) | + (1 << CP0C3_DSP2P) | (1 << CP0C3_DSPP) | + (1 << CP0C3_CTXTC) | (1 << CP0C3_VInt) | + (1 << CP0C3_CDMM) | (1 << CP0C3_MT) | (1 << CP0C3_T= L), + .CP0_Config4 =3D MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) | + (2 << CP0C4_IE) | (1U << CP0C4_M), + .CP0_Config5 =3D MIPS_CONFIG5 | (1 << CP0C5_MVH) | (1 << CP0C5_LLB= ), + .CP0_Config5_rw_bitmask =3D (1 << CP0C5_SBRI) | (1 << CP0C5_FRE) | + (1 << CP0C5_UFE), + .CP0_LLAddr_rw_bitmask =3D 0, + .CP0_LLAddr_shift =3D 0, + .SYNCI_Step =3D 32, + .CCRes =3D 2, + .CP0_Status_rw_bitmask =3D 0x3158FF1F, + .CP0_PageGrain =3D (1 << CP0PG_IEC) | (1 << CP0PG_XIE) | + (1U << CP0PG_RIE), + .CP0_PageGrain_rw_bitmask =3D 0, + .CP1_fcr0 =3D (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_= F64) | + (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | + (1 << FCR0_S) | (0x02 << FCR0_PRID) | (0x0 << FCR0_REV= ), + .CP1_fcr31 =3D (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008), + .SEGBITS =3D 32, + .PABITS =3D 32, + .insn_flags =3D CPU_NANOMIPS32 | ASE_MICROMIPS | ASE_DSP | ASE_DSP= R2 | + ASE_MT, + .mmu_type =3D MMU_TYPE_R4000, + }, #if defined(TARGET_MIPS64) { .name =3D "R4000", --=20 2.7.4