From nobody Wed Nov 5 05:17:51 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1532454445184881.7567598173589; Tue, 24 Jul 2018 10:47:25 -0700 (PDT) Received: from localhost ([::1]:41768 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fi1PA-0005F6-29 for importer@patchew.org; Tue, 24 Jul 2018 13:47:24 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40149) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fi1Lm-0002iw-Rb for qemu-devel@nongnu.org; Tue, 24 Jul 2018 13:43:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fi1Ll-0001DB-MV for qemu-devel@nongnu.org; Tue, 24 Jul 2018 13:43:54 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:46010 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fi1Ll-0001Br-Ac for qemu-devel@nongnu.org; Tue, 24 Jul 2018 13:43:53 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id EC5B41A44E6; Tue, 24 Jul 2018 19:43:51 +0200 (CEST) Received: from rtrkw774-lin.mipstec.com (unknown [82.117.201.26]) by mail.rt-rk.com (Postfix) with ESMTPSA id CBE881A1DCE; Tue, 24 Jul 2018 19:43:51 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Tue, 24 Jul 2018 19:31:15 +0200 Message-Id: <1532453527-22911-4-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1532453527-22911-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1532453527-22911-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v4 03/55] target/mips: Add nanoMIPS DSP ASE opcodes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pburton@wavecomp.com, smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, philippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Stefan Markovic Add nanoMIPS opcodes for DSP ASE instruction pools and instructions. Reviewed-by: Richard Henderson Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic --- target/mips/translate.c | 144 ++++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 144 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index 6a99a61..227b2c0 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -16142,10 +16142,154 @@ enum { =20 /* POOL32Axf instruction pool */ enum { + NM_POOL32AXF_1 =3D 0x01, + NM_POOL32AXF_2 =3D 0x02, NM_POOL32AXF_4 =3D 0x04, NM_POOL32AXF_5 =3D 0x05, + NM_POOL32AXF_7 =3D 0x07, }; =20 +/* POOL32Axf_1 instruction pool */ +enum { + NM_POOL32AXF_1_0 =3D 0x00, + NM_POOL32AXF_1_1 =3D 0x01, + NM_POOL32AXF_1_3 =3D 0x03, + NM_POOL32AXF_1_4 =3D 0x04, + NM_POOL32AXF_1_5 =3D 0x05, + NM_POOL32AXF_1_7 =3D 0x07, +}; + +/* POOL32Axf_2 instruction pool */ +enum { + NM_POOL32AXF_2_0_7 =3D 0x00, + NM_POOL32AXF_2_8_15 =3D 0x01, + NM_POOL32AXF_2_16_23 =3D 0x02, + NM_POOL32AXF_2_24_31 =3D 0x03, +}; + +/* POOL32Axf_{4, 5} instruction pool */ +enum { + /* nanoMIPS DSP instructions */ + NM_ABSQ_S_QB =3D 0x00, + NM_ABSQ_S_PH =3D 0x08, + NM_ABSQ_S_W =3D 0x10, + NM_PRECEQ_W_PHL =3D 0x28, + NM_PRECEQ_W_PHR =3D 0x30, + NM_PRECEQU_PH_QBL =3D 0x38, + NM_PRECEQU_PH_QBR =3D 0x48, + NM_PRECEU_PH_QBL =3D 0x58, + NM_PRECEU_PH_QBR =3D 0x68, + NM_PRECEQU_PH_QBLA =3D 0x39, + NM_PRECEQU_PH_QBRA =3D 0x49, + NM_PRECEU_PH_QBLA =3D 0x59, + NM_PRECEU_PH_QBRA =3D 0x69, + NM_REPLV_PH =3D 0x01, + NM_REPLV_QB =3D 0x09, + NM_BITREV =3D 0x18, + NM_INSV =3D 0x20, + NM_RADDU_W_QB =3D 0x78, + + NM_BITSWAP =3D 0x05, + NM_WSBH =3D 0x3d, +}; + +/* POOL32Axf_7 instruction pool */ +enum { + NM_SHRA_R_QB =3D 0x0, + NM_SHRL_PH =3D 0x1, + NM_REPL_QB =3D 0x2, +}; + +/* POOL32Axf_1_0 instruction pool */ +enum { + NM_MFHI =3D 0x0, + NM_MFLO =3D 0x1, + NM_MTHI =3D 0x2, + NM_MTLO =3D 0x3, +}; + +/* POOL32Axf_1_1 instruction pool */ +enum { + NM_MTHLIP =3D 0x0, + NM_SHILOV =3D 0x1, +}; + +/* POOL32Axf_1_3 instruction pool */ +enum { + NM_RDDSP =3D 0x0, + NM_WRDSP =3D 0x1, + NM_EXTP =3D 0x2, + NM_EXTPDP =3D 0x3, +}; + +/* POOL32Axf_1_4 instruction pool */ +enum { + NM_SHLL_QB =3D 0x0, + NM_SHRL_QB =3D 0x1, +}; + +/* POOL32Axf_1_5 instruction pool */ +enum { + NM_MAQ_S_W_PHR =3D 0x0, + NM_MAQ_S_W_PHL =3D 0x1, + NM_MAQ_SA_W_PHR =3D 0x2, + NM_MAQ_SA_W_PHL =3D 0x3, +}; + +/* POOL32Axf_1_7 instruction pool */ +enum { + NM_EXTR_W =3D 0x0, + NM_EXTR_R_W =3D 0x1, + NM_EXTR_RS_W =3D 0x2, + NM_EXTR_S_H =3D 0x3, +}; + +/* POOL32Axf_2_0_7 instruction pool */ +enum { + NM_DPA_W_PH =3D 0x0, + NM_DPAQ_S_W_PH =3D 0x1, + NM_DPS_W_PH =3D 0x2, + NM_DPSQ_S_W_PH =3D 0x3, + NM_BALIGN =3D 0x4, + NM_MADD =3D 0x5, + NM_MULT =3D 0x6, + NM_EXTRV_W =3D 0x7, +}; + +/* POOL32Axf_2_8_15 instruction pool */ +enum { + NM_DPAX_W_PH =3D 0x0, + NM_DPAQ_SA_L_W =3D 0x1, + NM_DPSX_W_PH =3D 0x2, + NM_DPSQ_SA_L_W =3D 0x3, + NM_MADDU =3D 0x5, + NM_MULTU =3D 0x6, + NM_EXTRV_R_W =3D 0x7, +}; + +/* POOL32Axf_2_16_23 instruction pool */ +enum { + NM_DPAU_H_QBL =3D 0x0, + NM_DPAQX_S_W_PH =3D 0x1, + NM_DPSU_H_QBL =3D 0x2, + NM_DPSQX_S_W_PH =3D 0x3, + NM_EXTPV =3D 0x4, + NM_MSUB =3D 0x5, + NM_MULSA_W_PH =3D 0x6, + NM_EXTRV_RS_W =3D 0x7, +}; + +/* POOL32Axf_2_24_31 instruction pool */ +enum { + NM_DPAU_H_QBR =3D 0x0, + NM_DPAQX_SA_W_PH =3D 0x1, + NM_DPSU_H_QBR =3D 0x2, + NM_DPSQX_SA_W_PH =3D 0x3, + NM_EXTPDPV =3D 0x4, + NM_MSUBU =3D 0x5, + NM_MULSAQ_S_W_PH =3D 0x6, + NM_EXTRV_S_H =3D 0x7, +}; /* POOL32Axf_{4, 5} instruction pool */ enum { NM_CLO =3D 0x25, --=20 2.7.4