From nobody Wed Nov 5 06:42:36 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1532455038789322.5398029644007; Tue, 24 Jul 2018 10:57:18 -0700 (PDT) Received: from localhost ([::1]:41824 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fi1Yf-0007GJ-Jc for importer@patchew.org; Tue, 24 Jul 2018 13:57:13 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47726) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fi1Wm-00066g-8r for qemu-devel@nongnu.org; Tue, 24 Jul 2018 13:55:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fi1Wh-0004HQ-6L for qemu-devel@nongnu.org; Tue, 24 Jul 2018 13:55:16 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:53250 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fi1Wg-0004DO-Qz for qemu-devel@nongnu.org; Tue, 24 Jul 2018 13:55:11 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 8BB011A44E6; Tue, 24 Jul 2018 19:55:09 +0200 (CEST) Received: from rtrkw774-lin.mipstec.com (unknown [82.117.201.26]) by mail.rt-rk.com (Postfix) with ESMTPSA id 6BDA81A1DCE; Tue, 24 Jul 2018 19:55:09 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Tue, 24 Jul 2018 19:31:39 +0200 Message-Id: <1532453527-22911-28-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1532453527-22911-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1532453527-22911-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v4 27/55] target/mips: Implement CP0 Config0.WR bit functionality X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pburton@wavecomp.com, smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, philippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Stefan Markovic Add testing Config0.WR bit into watch exception handling logic. Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic --- target/mips/helper.c | 12 +++++++++++- target/mips/translate.c | 22 ++++++++++++++++------ 2 files changed, 27 insertions(+), 7 deletions(-) diff --git a/target/mips/helper.c b/target/mips/helper.c index b25e000..a576fa4 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -747,6 +747,14 @@ void mips_cpu_do_interrupt(CPUState *cs) (env->hflags & MIPS_HFLAG_DM)) { cs->exception_index =3D EXCP_DINT; } + + if ((cs->exception_index =3D=3D EXCP_DWATCH || + cs->exception_index =3D=3D EXCP_DFWATCH || + cs->exception_index =3D=3D EXCP_IWATCH) && + (env->CP0_Config1 & (1 << CP0C1_WR))) { + cs->exception_index =3D EXCP_NONE; + } + offset =3D 0x180; switch (cs->exception_index) { case EXCP_DSS: @@ -797,7 +805,9 @@ void mips_cpu_do_interrupt(CPUState *cs) break; case EXCP_SRESET: env->CP0_Status |=3D (1 << CP0St_SR); - memset(env->CP0_WatchLo, 0, sizeof(env->CP0_WatchLo)); + if (env->CP0_Config1 & (1 << CP0C1_WR)) { + memset(env->CP0_WatchLo, 0, sizeof(env->CP0_WatchLo)); + } goto set_error_EPC; case EXCP_NMI: env->CP0_Status |=3D (1 << CP0St_NMI); diff --git a/target/mips/translate.c b/target/mips/translate.c index cf28c60..68f1879 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -5622,6 +5622,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) case 5: case 6: case 7: + CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); gen_helper_1e0i(mfc0_watchlo, arg, sel); rn =3D "WatchLo"; break; @@ -5639,6 +5640,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) case 5: case 6: case 7: + CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); gen_helper_1e0i(mfc0_watchhi, arg, sel); rn =3D "WatchHi"; break; @@ -6321,6 +6323,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) case 5: case 6: case 7: + CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); gen_helper_0e1i(mtc0_watchlo, arg, sel); rn =3D "WatchLo"; break; @@ -6338,6 +6341,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) case 5: case 6: case 7: + CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); gen_helper_0e1i(mtc0_watchhi, arg, sel); rn =3D "WatchHi"; break; @@ -7024,6 +7028,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) case 5: case 6: case 7: + CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); gen_helper_1e0i(dmfc0_watchlo, arg, sel); rn =3D "WatchLo"; break; @@ -7041,6 +7046,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) case 5: case 6: case 7: + CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); gen_helper_1e0i(mfc0_watchhi, arg, sel); rn =3D "WatchHi"; break; @@ -7705,6 +7711,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) case 5: case 6: case 7: + CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); gen_helper_0e1i(mtc0_watchlo, arg, sel); rn =3D "WatchLo"; break; @@ -7722,6 +7729,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) case 5: case 6: case 7: + CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); gen_helper_0e1i(mtc0_watchhi, arg, sel); rn =3D "WatchHi"; break; @@ -25285,14 +25293,16 @@ void cpu_state_reset(CPUMIPSState *env) no performance counters. */ env->CP0_IntCtl =3D 0xe0000000; { - int i; + if (env->CP0_Config1 & (1 << CP0C1_WR)) { + int i; =20 - for (i =3D 0; i < 7; i++) { - env->CP0_WatchLo[i] =3D 0; - env->CP0_WatchHi[i] =3D 0x80000000; + for (i =3D 0; i < 7; i++) { + env->CP0_WatchLo[i] =3D 0; + env->CP0_WatchHi[i] =3D 0x80000000; + } + env->CP0_WatchLo[7] =3D 0; + env->CP0_WatchHi[7] =3D 0; } - env->CP0_WatchLo[7] =3D 0; - env->CP0_WatchHi[7] =3D 0; } /* Count register increments in debug mode, EJTAG version 1 */ env->CP0_Debug =3D (1 << CP0DB_CNT) | (0x1 << CP0DB_VER); --=20 2.7.4