From nobody Wed Nov 5 04:44:52 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 153245485333286.66453795096834; Tue, 24 Jul 2018 10:54:13 -0700 (PDT) Received: from localhost ([::1]:41803 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fi1Vk-00049k-9D for importer@patchew.org; Tue, 24 Jul 2018 13:54:12 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44137) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fi1RF-0007FN-FU for qemu-devel@nongnu.org; Tue, 24 Jul 2018 13:49:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fi1RD-0006ye-Ay for qemu-devel@nongnu.org; Tue, 24 Jul 2018 13:49:33 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:49657 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fi1RC-0006xV-Us for qemu-devel@nongnu.org; Tue, 24 Jul 2018 13:49:31 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id A46941A44E6; Tue, 24 Jul 2018 19:49:29 +0200 (CEST) Received: from rtrkw774-lin.mipstec.com (unknown [82.117.201.26]) by mail.rt-rk.com (Postfix) with ESMTPSA id 847921A1DCE; Tue, 24 Jul 2018 19:49:29 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Tue, 24 Jul 2018 19:31:28 +0200 Message-Id: <1532453527-22911-17-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1532453527-22911-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1532453527-22911-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v4 16/55] target/mips: Implement emulation of nanoMIPS ROTX instruction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pburton@wavecomp.com, smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, philippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Matthew Fortune Added a helper for ROTX based on the pseudocode from the architecture spec. This instraction was not present in previous MIPS instruction sets. Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic Reviewed-by: Aleksandar Markovic Reviewed-by: Richard Henderson --- target/mips/helper.h | 2 ++ target/mips/op_helper.c | 94 +++++++++++++++++++++++++++++++++++++++++++++= ++++ target/mips/translate.c | 15 ++++++++ 3 files changed, 111 insertions(+) diff --git a/target/mips/helper.h b/target/mips/helper.h index 5f49234..b2a780a 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -40,6 +40,8 @@ DEF_HELPER_FLAGS_1(bitswap, TCG_CALL_NO_RWG_SE, tl, tl) DEF_HELPER_FLAGS_1(dbitswap, TCG_CALL_NO_RWG_SE, tl, tl) #endif =20 +DEF_HELPER_FLAGS_4(rotx, TCG_CALL_NO_RWG_SE, tl, tl, i32, i32, i32) + #ifndef CONFIG_USER_ONLY /* CP0 helpers */ DEF_HELPER_1(mfc0_mvpcontrol, tl, env) diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 0b2663b..b3eef9f 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -249,6 +249,100 @@ target_ulong helper_bitswap(target_ulong rt) return (int32_t)bitswap(rt); } =20 +target_ulong helper_rotx(target_ulong rs, uint32_t shift, uint32_t shiftx, + uint32_t stripe) +{ + int i; + uint64_t tmp0 =3D ((uint64_t)rs) << 32 | ((uint64_t)rs & 0xffffffff); + uint64_t tmp1 =3D tmp0; + for (i =3D 0; i <=3D 46; i++) { + int s; + if (i & 0x8) { + s =3D shift; + } else { + s =3D shiftx; + } + + if (stripe !=3D 0 && !(i & 0x4)) { + s =3D ~s; + } + if (s & 0x10) { + if (tmp0 & (1LL << (i + 16))) { + tmp1 |=3D 1LL << i; + } else { + tmp1 &=3D ~(1LL << i); + } + } + } + + uint64_t tmp2 =3D tmp1; + for (i =3D 0; i <=3D 38; i++) { + int s; + if (i & 0x4) { + s =3D shift; + } else { + s =3D shiftx; + } + + if (s & 0x8) { + if (tmp1 & (1LL << (i + 8))) { + tmp2 |=3D 1LL << i; + } else { + tmp2 &=3D ~(1LL << i); + } + } + } + + uint64_t tmp3 =3D tmp2; + for (i =3D 0; i <=3D 34; i++) { + int s; + if (i & 0x2) { + s =3D shift; + } else { + s =3D shiftx; + } + if (s & 0x4) { + if (tmp2 & (1LL << (i + 4))) { + tmp3 |=3D 1LL << i; + } else { + tmp3 &=3D ~(1LL << i); + } + } + } + + uint64_t tmp4 =3D tmp3; + for (i =3D 0; i <=3D 32; i++) { + int s; + if (i & 0x1) { + s =3D shift; + } else { + s =3D shiftx; + } + if (s & 0x2) { + if (tmp3 & (1LL << (i + 2))) { + tmp4 |=3D 1LL << i; + } else { + tmp4 &=3D ~(1LL << i); + } + } + } + + uint64_t tmp5 =3D tmp4; + for (i =3D 0; i <=3D 31; i++) { + int s; + s =3D shift; + if (s & 0x1) { + if (tmp4 & (1LL << (i + 1))) { + tmp5 |=3D 1LL << i; + } else { + tmp5 &=3D ~(1LL << i); + } + } + } + + return (int64_t)(int32_t)(uint32_t)tmp5; +} + #ifndef CONFIG_USER_ONLY =20 static inline hwaddr do_translate_address(CPUMIPSState *env, diff --git a/target/mips/translate.c b/target/mips/translate.c index 1aafb74..1d2bc02 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -17581,6 +17581,21 @@ static int decode_nanomips_32_48_opc(CPUMIPSState = *env, DisasContext *ctx) } break; case NM_P_ROTX: + if (rt !=3D 0) { + TCGv t0 =3D tcg_temp_new(); + TCGv_i32 shift =3D tcg_const_i32(extract32(ctx->opcode, 0,= 5)); + TCGv_i32 shiftx =3D tcg_const_i32(extract32(ctx->opcode, 7= , 4) + << 1); + TCGv_i32 stripe =3D tcg_const_i32((ctx->opcode >> 6) & 1); + + gen_load_gpr(t0, rs); + gen_helper_rotx(cpu_gpr[rt], t0, shift, shiftx, stripe); + tcg_temp_free(t0); + + tcg_temp_free_i32(shift); + tcg_temp_free_i32(shiftx); + tcg_temp_free_i32(stripe); + } break; case NM_P_INS: switch (((ctx->opcode >> 10) & 2) | ((ctx->opcode >> 5) & 1)) { --=20 2.7.4