From nobody Wed Nov 5 04:43:53 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1532455001526523.7354295356347; Tue, 24 Jul 2018 10:56:41 -0700 (PDT) Received: from localhost ([::1]:41821 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fi1Xz-0006gZ-N8 for importer@patchew.org; Tue, 24 Jul 2018 13:56:31 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42295) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fi1Ov-0005Ri-EA for qemu-devel@nongnu.org; Tue, 24 Jul 2018 13:47:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fi1Oq-0004Dr-NX for qemu-devel@nongnu.org; Tue, 24 Jul 2018 13:47:09 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:46739 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fi1Oq-0004Bp-9E for qemu-devel@nongnu.org; Tue, 24 Jul 2018 13:47:04 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 0951C1A44E6; Tue, 24 Jul 2018 19:47:03 +0200 (CEST) Received: from rtrkw774-lin.mipstec.com (unknown [82.117.201.26]) by mail.rt-rk.com (Postfix) with ESMTPSA id DB0241A1DCE; Tue, 24 Jul 2018 19:47:02 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Tue, 24 Jul 2018 19:31:22 +0200 Message-Id: <1532453527-22911-11-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1532453527-22911-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1532453527-22911-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v4 10/55] target/mips: Add emulation of some common nanoMIPS 32-bit instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pburton@wavecomp.com, smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, philippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Yongbok Kim Add emulation of SIGRIE, SYSCALL, BREAK, SDBBP, ADDIU, ADDIUPC, ADDIUGP.W, LWGP, SWGP, ORI, XORI, ANDI, and other instructions. Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic Reviewed-by: Aleksandar Markovic --- target/mips/translate.c | 285 ++++++++++++++++++++++++++++++++++++++++++++= +++- 1 file changed, 284 insertions(+), 1 deletion(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index b76d8ec..0b69ceb 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -16590,6 +16590,289 @@ static void gen_pool16c_nanomips_insn(DisasContex= t *ctx) } } =20 +static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) +{ + uint16_t insn; + int rt, rs; + uint32_t op; + + insn =3D cpu_lduw_code(env, ctx->base.pc_next + 2); + ctx->opcode =3D (ctx->opcode << 16) | insn; + + rt =3D (ctx->opcode >> 21) & 0x1f; + rs =3D (ctx->opcode >> 16) & 0x1f; + + op =3D (ctx->opcode >> 26) & 0x3f; + switch (op) { + case NM_P_ADDIU: + if (rt =3D=3D 0) { + /* P.RI */ + switch ((ctx->opcode >> 19) & 0x03) { + case NM_SIGRIE: + default: + generate_exception_end(ctx, EXCP_RI); + break; + case NM_P_SYSCALL: + if (((ctx->opcode >> 18) & 0x01) =3D=3D NM_SYSCALL) { + generate_exception_end(ctx, EXCP_SYSCALL); + } else { + generate_exception_end(ctx, EXCP_RI); + } + break; + case NM_BREAK: + generate_exception_end(ctx, EXCP_BREAK); + break; + case NM_SDBBP: + if (is_uhi(extract32(ctx->opcode, 0, 19))) { + gen_helper_do_semihosting(cpu_env); + } else { + if (ctx->hflags & MIPS_HFLAG_SBRI) { + generate_exception_end(ctx, EXCP_RI); + } else { + generate_exception_end(ctx, EXCP_DBp); + } + } + break; + } + } else { + uint16_t imm; + imm =3D (uint16_t) extract32(ctx->opcode, 0, 16); + if (rs !=3D 0) { + tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rs], imm); + tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]); + } else { + tcg_gen_movi_tl(cpu_gpr[rt], imm); + } + } + break; + case NM_ADDIUPC: + if (rt !=3D 0) { + int32_t offset =3D sextract32(ctx->opcode, 0, 1) << 21 + | extract32(ctx->opcode, 1, 20) << 1; + target_long addr =3D addr_add(ctx, ctx->base.pc_next + 4, offs= et); + tcg_gen_movi_tl(cpu_gpr[rt], addr); + tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]); + } + break; + case NM_POOL32A: + break; + case NM_P_GP_W: + switch (ctx->opcode & 0x03) { + case NM_ADDIUGP_W: + if (rt !=3D 0) { + uint32_t offset =3D extract32(ctx->opcode, 0, 21); + if (offset =3D=3D 0) { + gen_load_gpr(cpu_gpr[rt], 28); + } else { + TCGv t0; + t0 =3D tcg_temp_new(); + tcg_gen_movi_tl(t0, offset); + gen_op_addr_add(ctx, cpu_gpr[rt], cpu_gpr[28], t0); + tcg_temp_free(t0); + } + } + break; + case NM_LWGP: + gen_ld(ctx, OPC_LW, rt, 28, extract32(ctx->opcode, 2, 19) << 2= ); + break; + case NM_SWGP: + gen_st(ctx, OPC_SW, rt, 28, extract32(ctx->opcode, 2, 19) << 2= ); + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } + break; + case NM_P48I: + return 6; + case NM_P_U12: + switch ((ctx->opcode >> 12) & 0x0f) { + case NM_ORI: + gen_logic_imm(ctx, OPC_ORI, rt, rs, extract32(ctx->opcode, 0, = 12)); + break; + case NM_XORI: + gen_logic_imm(ctx, OPC_XORI, rt, rs, extract32(ctx->opcode, 0,= 12)); + break; + case NM_ANDI: + gen_logic_imm(ctx, OPC_ANDI, rt, rs, extract32(ctx->opcode, 0,= 12)); + break; + case NM_P_SR: + switch ((ctx->opcode >> 20) & 1) { + case NM_PP_SR: + switch (ctx->opcode & 3) { + case NM_SAVE: + gen_save(ctx, rt, extract32(ctx->opcode, 16, 4), + (ctx->opcode >> 2) & 1, + extract32(ctx->opcode, 3, 9) << 3); + break; + case NM_RESTORE: + case NM_RESTORE_JRC: + gen_restore(ctx, rt, extract32(ctx->opcode, 16, 4), + (ctx->opcode >> 2) & 1, + extract32(ctx->opcode, 3, 9) << 3); + if ((ctx->opcode & 3) =3D=3D NM_RESTORE_JRC) { + gen_compute_branch(ctx, OPC_JR, 2, 31, 0, 0, 0); + } + break; + } + break; + case NM_P_SR_F: + generate_exception_end(ctx, EXCP_RI); + break; + } + break; + case NM_SLTI: + gen_slt_imm(ctx, OPC_SLTI, rt, rs, extract32(ctx->opcode, 0, 1= 2)); + break; + case NM_SLTIU: + gen_slt_imm(ctx, OPC_SLTIU, rt, rs, extract32(ctx->opcode, 0, = 12)); + break; + case NM_SEQI: + { + TCGv t0 =3D tcg_temp_new(); + TCGv t1 =3D tcg_temp_new(); + TCGv t2 =3D tcg_temp_local_new(); + TCGLabel *l1 =3D gen_new_label(); + + gen_load_gpr(t0, rs); + tcg_gen_movi_tl(t1, extract32(ctx->opcode, 0, 12)); + tcg_gen_movi_tl(t2, 0); + tcg_gen_brcond_tl(TCG_COND_NE, t0, t1, l1); + tcg_gen_movi_tl(t2, 1); + gen_set_label(l1); + gen_store_gpr(t2, rt); + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(t2); + } + break; + case NM_ADDIUNEG: + { + int16_t imm; + imm =3D (int16_t) extract32(ctx->opcode, 0, 12); + gen_arith_imm(ctx, OPC_ADDIU, rt, rs, -imm); + } + break; + case NM_P_SHIFT: + { + int shift =3D extract32(ctx->opcode, 0, 5); + switch ((ctx->opcode >> 5) & 0x0f) { + case NM_P_SLL: + if (rt =3D=3D 0 && shift =3D=3D 0) { + /* NOP */ + } else if (rt =3D=3D 0 && shift =3D=3D 3) { + /* EHB treat as NOP */ + } else if (rt =3D=3D 0 && shift =3D=3D 5) { + /* PAUSE */ + if (ctx->hflags & MIPS_HFLAG_BMASK) { + generate_exception_end(ctx, EXCP_RI); + } + } else if (rt =3D=3D 0 && shift =3D=3D 6) { + /* SYNC */ + check_insn(ctx, ISA_MIPS2); + /* Treat as NOP. */ + } else { + /* SLL */ + gen_shift_imm(ctx, OPC_SLL, rt, rs, + extract32(ctx->opcode, 0, 5)); + } + break; + case NM_SRL: + gen_shift_imm(ctx, OPC_SRL, rt, rs, + extract32(ctx->opcode, 0, 5)); + break; + case NM_SRA: + gen_shift_imm(ctx, OPC_SRA, rt, rs, + extract32(ctx->opcode, 0, 5)); + break; + case NM_ROTR: + gen_shift_imm(ctx, OPC_ROTR, rt, rs, + extract32(ctx->opcode, 0, 5)); + break; + } + } + break; + case NM_P_ROTX: + break; + case NM_P_INS: + switch (((ctx->opcode >> 10) & 2) | ((ctx->opcode >> 5) & 1)) { + case NM_INS: + gen_bitops(ctx, OPC_INS, rt, rs, extract32(ctx->opcode, 0,= 5), + extract32(ctx->opcode, 6, 5)); + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } + break; + case NM_P_EXT: + switch (((ctx->opcode >> 10) & 2) | ((ctx->opcode >> 5) & 1)) { + case NM_EXT: + gen_bitops(ctx, OPC_EXT, rt, rs, extract32(ctx->opcode, 0,= 5), + extract32(ctx->opcode, 6, 5)); + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } + break; + case NM_POOL32F: + break; + case NM_POOL32S: + break; + case NM_P_LUI: + switch ((ctx->opcode >> 1) & 1) { + case NM_LUI: + if (rt !=3D 0) { + tcg_gen_movi_tl(cpu_gpr[rt], + sextract32(ctx->opcode, 0, 1) << 31 | + extract32(ctx->opcode, 2, 10) << 21 | + extract32(ctx->opcode, 12, 9) << 12); + } + break; + case NM_ALUIPC: + if (rt !=3D 0) { + int offset =3D sextract32(ctx->opcode, 0, 1) << 31 | + extract32(ctx->opcode, 2, 10) << 21 | + extract32(ctx->opcode, 12, 9) << 12; + target_long addr; + addr =3D ~0xFFF & addr_add(ctx, ctx->base.pc_next + 4, off= set); + tcg_gen_movi_tl(cpu_gpr[rt], addr); + } + break; + } + break; + case NM_P_GP_BH: + break; + case NM_P_LS_U12: + break; + case NM_P_LS_S9: + break; + case NM_MOVE_BALC: + break; + case NM_P_BAL: + break; + case NM_P_J: + break; + case NM_P_BR1: + break; + case NM_P_BR2: + break; + case NM_P_BRI: + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } + return 4; +} + static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx) { uint32_t op; @@ -16971,7 +17254,7 @@ static int decode_nanomips_opc(CPUMIPSState *env, D= isasContext *ctx) } break; default: - break; + return decode_nanomips_32_48_opc(env, ctx); } =20 return 2; --=20 2.7.4