From nobody Tue Feb 10 11:12:45 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 153245246700863.516429808896305; Tue, 24 Jul 2018 10:14:27 -0700 (PDT) Received: from localhost ([::1]:41649 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fi0tG-0001Jf-1n for importer@patchew.org; Tue, 24 Jul 2018 13:14:26 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45574) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fi0lw-0003ic-68 for qemu-devel@nongnu.org; Tue, 24 Jul 2018 13:06:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fi0ls-0000pP-30 for qemu-devel@nongnu.org; Tue, 24 Jul 2018 13:06:52 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:37243 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fi0lr-0000oV-R6 for qemu-devel@nongnu.org; Tue, 24 Jul 2018 13:06:47 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 7E4301A225C; Tue, 24 Jul 2018 19:06:46 +0200 (CEST) Received: from rtrkw774-lin.mipstec.com (unknown [82.117.201.26]) by mail.rt-rk.com (Postfix) with ESMTPSA id 5D89A1A1E52; Tue, 24 Jul 2018 19:06:46 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Tue, 24 Jul 2018 19:04:44 +0200 Message-Id: <1532451888-8958-7-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1532451888-8958-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1532451888-8958-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v7 06/10] target/mips: Check ELPA flag only in some cases of MFHC0 and MTHC0 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pburton@wavecomp.com, smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, philippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Yongbok Kim MFHC0 and MTHC0 used to handle EntryLo0 and EntryLo1 registers only, and placing ELPA flag checks before switch statement were technically correct. However, after adding handling more registers, these checks should be moved to act only in cases of handling EntryLo0 and EntryLo1. Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic Reviewed-by: Aleksandar Markovic Reviewed-by: Richard Henderson --- target/mips/translate.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 9871182..de0d55b 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -4884,12 +4884,11 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, = int reg, int sel) { const char *rn =3D "invalid"; =20 - CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA); - switch (reg) { case 2: switch (sel) { case 0: + CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA); gen_mfhc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo0)); rn =3D "EntryLo0"; break; @@ -4900,6 +4899,7 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) case 3: switch (sel) { case 0: + CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA); gen_mfhc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo1)); rn =3D "EntryLo1"; break; @@ -4952,12 +4952,11 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, = int reg, int sel) const char *rn =3D "invalid"; uint64_t mask =3D ctx->PAMask >> 36; =20 - CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA); - switch (reg) { case 2: switch (sel) { case 0: + CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA); tcg_gen_andi_tl(arg, arg, mask); gen_mthc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo0)); rn =3D "EntryLo0"; @@ -4969,6 +4968,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) case 3: switch (sel) { case 0: + CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA); tcg_gen_andi_tl(arg, arg, mask); gen_mthc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo1)); rn =3D "EntryLo1"; --=20 2.7.4