From nobody Mon Feb 9 15:46:02 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1532007956757813.2155500993492; Thu, 19 Jul 2018 06:45:56 -0700 (PDT) Received: from localhost ([::1]:43050 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg9Fe-0008BP-Ha for importer@patchew.org; Thu, 19 Jul 2018 09:45:50 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50694) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg8WM-0003JS-7X for qemu-devel@nongnu.org; Thu, 19 Jul 2018 09:00:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fg8Tb-0004g7-Ne for qemu-devel@nongnu.org; Thu, 19 Jul 2018 08:59:02 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:56653 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fg8Tb-0004dy-1y for qemu-devel@nongnu.org; Thu, 19 Jul 2018 08:56:11 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 813F31A416D; Thu, 19 Jul 2018 14:56:09 +0200 (CEST) Received: from smarkovic.mipstec.com (smarkovic.domain.local [10.10.14.46]) by mail.rt-rk.com (Postfix) with ESMTPSA id 63DC51A1D42; Thu, 19 Jul 2018 14:56:09 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Stefan Markovic To: qemu-devel@nongnu.org Date: Thu, 19 Jul 2018 14:54:39 +0200 Message-Id: <1532004912-13899-8-git-send-email-stefan.markovic@rt-rk.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> References: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-Mailman-Approved-At: Thu, 19 Jul 2018 09:35:10 -0400 Subject: [Qemu-devel] [PATCH v3 07/40] target/mips: Add emulation of nanoMIPS 16-bit load and store instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pburton@wavecomp.com, smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, philippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Yongbok Kim Add emulation of LWXS16, LB16, SB16, LBU16, LH16, SH16, LHU16, LW16, LWSP16, LW4X4, SW4X4, LWGP16, SWSP16, SW16, and SWGP16 instructions. Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic --- target/mips/translate.c | 114 ++++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 114 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index 798f977..1a839be 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -16472,6 +16472,14 @@ static int decode_gpr_gpr3(int r) return map[r & 0x7]; } =20 +/* Used for 16-bit store instructions. */ +static int decode_gpr_gpr3_src_store(int r) +{ + static const int map[] =3D { 0, 17, 18, 19, 4, 5, 6, 7 }; + + return map[r & 0x7]; +} + static int decode_gpr_gpr4(int r) { static const int map[] =3D { 8, 9, 10, 11, 4, 5, 6, 7, @@ -16568,6 +16576,13 @@ static int decode_nanomips_opc(CPUMIPSState *env, = DisasContext *ctx) } break; case NM_P16C: + switch (ctx->opcode & 1) { + case NM_POOL16C_0: + break; + case NM_LWXS16: + gen_ldxs(ctx, rt, rs, rd); + break; + } break; case NM_P16_A1: switch ((ctx->opcode >> 6) & 1) { @@ -16651,24 +16666,123 @@ static int decode_nanomips_opc(CPUMIPSState *env= , DisasContext *ctx) } break; case NM_P16_LB: + { + uint32_t u =3D extract32(ctx->opcode, 0, 2); + switch (((ctx->opcode) >> 2) & 0x03) { + case NM_LB16: + gen_ld(ctx, OPC_LB, rt, rs, u); + break; + case NM_SB16: + { + int rt =3D decode_gpr_gpr3_src_store( + NANOMIPS_EXTRACT_RD(ctx->opcode)); + gen_st(ctx, OPC_SB, rt, rs, u); + } + break; + case NM_LBU16: + gen_ld(ctx, OPC_LBU, rt, rs, u); + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } + } break; case NM_P16_LH: + { + uint32_t u =3D extract32(ctx->opcode, 1, 2) << 1; + switch ((((ctx->opcode >> 3) & 1) << 1) | (ctx->opcode & 1)) { + case NM_LH16: + gen_ld(ctx, OPC_LH, rt, rs, u); + break; + case NM_SH16: + { + int rt =3D decode_gpr_gpr3_src_store( + NANOMIPS_EXTRACT_RD(ctx->opcode)); + gen_st(ctx, OPC_SH, rt, rs, u); + } + break; + case NM_LHU16: + gen_ld(ctx, OPC_LHU, rt, rs, u); + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } + } break; case NM_LW16: + { + int u =3D extract32(ctx->opcode, 0, 4) << 2; + gen_ld(ctx, OPC_LW, rt, rs, u); + } break; case NM_LWSP16: + { + int rt =3D NANOMIPS_EXTRACT_RD5(ctx->opcode); + int u =3D extract32(ctx->opcode, 0, 5) << 2; + + gen_ld(ctx, OPC_LW, rt, 29, u); + } break; case NM_LW4X4: + { + int rt =3D (extract32(ctx->opcode, 9, 1) << 3) | + extract32(ctx->opcode, 5, 3); + int rs =3D (extract32(ctx->opcode, 4, 1) << 3) | + extract32(ctx->opcode, 0, 3); + int u =3D (extract32(ctx->opcode, 3, 1) << 3) | + (extract32(ctx->opcode, 8, 1) << 2); + rt =3D decode_gpr_gpr4(rt); + rs =3D decode_gpr_gpr4(rs); + gen_ld(ctx, OPC_LW, rt, rs, u); + } break; case NM_SW4X4: + { + int rt =3D (extract32(ctx->opcode, 9, 1) << 3) | + extract32(ctx->opcode, 5, 3); + int rs =3D (extract32(ctx->opcode, 4, 1) << 3) | + extract32(ctx->opcode, 0, 3); + int u =3D (extract32(ctx->opcode, 3, 1) << 3) | + (extract32(ctx->opcode, 8, 1) << 2); + rt =3D decode_gpr_gpr4_zero(rt); + rs =3D decode_gpr_gpr4(rs); + gen_st(ctx, OPC_SW, rt, rs, u); + } break; case NM_LWGP16: + { + int u =3D extract32(ctx->opcode, 0, 7) << 2; + gen_ld(ctx, OPC_LW, rt, 28, u); + } break; case NM_SWSP16: + { + int rt =3D NANOMIPS_EXTRACT_RD5(ctx->opcode); + int u =3D extract32(ctx->opcode, 0, 5) << 2; + + gen_st(ctx, OPC_SW, rt, 29, u); + } break; case NM_SW16: + { + int rt =3D decode_gpr_gpr3_src_store( + NANOMIPS_EXTRACT_RD(ctx->opcode)); + int rs =3D decode_gpr_gpr3(NANOMIPS_EXTRACT_RS(ctx->opcode)); + int u =3D extract32(ctx->opcode, 0, 4) << 2; + + gen_st(ctx, OPC_SW, rt, rs, u); + } break; case NM_SWGP16: + { + int rt =3D decode_gpr_gpr3_src_store( + NANOMIPS_EXTRACT_RD(ctx->opcode)); + int u =3D extract32(ctx->opcode, 0, 7) << 2; + + gen_st(ctx, OPC_SW, rt, 28, u); + } break; case NM_BC16: gen_compute_branch(ctx, OPC_BEQ, 2, 0, 0, --=20 2.7.4