From nobody Mon Feb 9 13:59:00 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1532008113363172.59151863961154; Thu, 19 Jul 2018 06:48:33 -0700 (PDT) Received: from localhost ([::1]:43018 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg9AC-0003CS-PT for importer@patchew.org; Thu, 19 Jul 2018 09:40:12 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48819) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fg8VG-00039f-S2 for qemu-devel@nongnu.org; Thu, 19 Jul 2018 08:59:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fg8UC-0005N5-Q1 for qemu-devel@nongnu.org; Thu, 19 Jul 2018 08:57:54 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:56879 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fg8UC-0005LM-67 for qemu-devel@nongnu.org; Thu, 19 Jul 2018 08:56:48 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 9659E1A22AF; Thu, 19 Jul 2018 14:56:46 +0200 (CEST) Received: from smarkovic.mipstec.com (smarkovic.domain.local [10.10.14.46]) by mail.rt-rk.com (Postfix) with ESMTPSA id 78F7F1A1D42; Thu, 19 Jul 2018 14:56:46 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Stefan Markovic To: qemu-devel@nongnu.org Date: Thu, 19 Jul 2018 14:54:43 +0200 Message-Id: <1532004912-13899-12-git-send-email-stefan.markovic@rt-rk.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> References: <1532004912-13899-1-git-send-email-stefan.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-Mailman-Approved-At: Thu, 19 Jul 2018 09:35:09 -0400 Subject: [Qemu-devel] [PATCH v3 11/40] target/mips: Add emulation of nanoMIPS 48-bit instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pburton@wavecomp.com, smarkovic@wavecomp.com, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, philippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Yongbok Kim Add emulation of LI48, ADDIU48, ADDIUGP48, ADDIUPC48, LWPC48, and SWPC48 instructions. Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic Reviewed-by: Aleksandar Markovic --- target/mips/translate.c | 66 +++++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 66 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index 201baf1..c47ee7d 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -16682,6 +16682,72 @@ static int decode_nanomips_32_48_opc(CPUMIPSState = *env, DisasContext *ctx) } break; case NM_P48I: + insn =3D cpu_lduw_code(env, ctx->base.pc_next + 4); + switch ((ctx->opcode >> 16) & 0x1f) { + case NM_LI48: + if (rt !=3D 0) { + tcg_gen_movi_tl(cpu_gpr[rt], + extract32(ctx->opcode, 0, 16) | insn << 16= ); + } + break; + case NM_ADDIU48: + if (rt !=3D 0) { + tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rt], + extract32(ctx->opcode, 0, 16) | insn << 16= ); + tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]); + } + break; + case NM_ADDIUGP48: + if (rt !=3D 0) { + tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[28], + extract32(ctx->opcode, 0, 16) | insn << 16= ); + tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]); + } + break; + case NM_ADDIUPC48: + if (rt !=3D 0) { + int32_t offset =3D extract32(ctx->opcode, 0, 16) | insn <<= 16; + target_long addr =3D addr_add(ctx, ctx->base.pc_next + 6, = offset); + + tcg_gen_movi_tl(cpu_gpr[rt], addr); + tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]); + } + break; + case NM_LWPC48: + if (rt !=3D 0) { + TCGv t0; + t0 =3D tcg_temp_new(); + + int32_t offset =3D extract32(ctx->opcode, 0, 16) | insn <<= 16; + target_long addr =3D addr_add(ctx, ctx->base.pc_next + 6, = offset); + + tcg_gen_movi_tl(t0, addr); + tcg_gen_qemu_ld_tl(cpu_gpr[rt], t0, ctx->mem_idx, MO_TESL); + tcg_temp_free(t0); + } + break; + case NM_SWPC48: + { + TCGv t0, t1; + t0 =3D tcg_temp_new(); + t1 =3D tcg_temp_new(); + + int32_t offset =3D extract32(ctx->opcode, 0, 16) | insn <<= 16; + target_long addr =3D addr_add(ctx, ctx->base.pc_next + 6, = offset); + + tcg_gen_movi_tl(t0, addr); + gen_load_gpr(t1, rt); + + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL); + + tcg_temp_free(t0); + tcg_temp_free(t1); + } + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } return 6; case NM_P_U12: switch ((ctx->opcode >> 12) & 0x0f) { --=20 2.7.4