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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Thu, 5 Jul 2018 13:25:57 -0400 Received: from b01ledav005.gho.pok.ibm.com (b01ledav005.gho.pok.ibm.com [9.57.199.110]) by b01cxnp22036.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id w65HPtIa64422066 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 5 Jul 2018 17:25:55 GMT Received: from b01ledav005.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 162AAAE060; Thu, 5 Jul 2018 13:25:36 -0400 (EDT) Received: from b01ledav005.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id DE11BAE05C; Thu, 5 Jul 2018 13:25:35 -0400 (EDT) Received: from jason-laptop.endicott.ibm.com (unknown [9.60.75.201]) by b01ledav005.gho.pok.ibm.com (Postfix) with ESMTP; Thu, 5 Jul 2018 13:25:35 -0400 (EDT) From: "Jason J. Herne" To: qemu-devel@nongnu.org, qemu-s390x@nongnu.org, cohuck@redhat.com, pasic@linux.ibm.com, bjsdjshi@linux.ibm.com, borntraeger@de.ibm.com Date: Thu, 5 Jul 2018 13:25:38 -0400 X-Mailer: git-send-email 2.7.4 In-Reply-To: <1530811543-6881-1-git-send-email-jjherne@linux.ibm.com> References: <1530811543-6881-1-git-send-email-jjherne@linux.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 18070517-0052-0000-0000-0000030987DD X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00009314; HX=3.00000241; KW=3.00000007; PH=3.00000004; SC=3.00000266; SDB=6.01056994; UDB=6.00542264; IPR=6.00834914; MB=3.00022012; MTD=3.00000008; XFM=3.00000015; UTC=2018-07-05 17:25:59 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18070517-0053-0000-0000-00005D4167BA Message-Id: <1530811543-6881-11-git-send-email-jjherne@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2018-07-05_06:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1806210000 definitions=main-1807050196 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.156.1 X-Mailman-Approved-At: Thu, 05 Jul 2018 14:03:14 -0400 Subject: [Qemu-devel] [RFC 10/15] s390-bios: Support for running format-0/1 channel programs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Jason J. Herne" Add struct for format-0 ccws. Support executing format-0 channel programs and waiting for their completion before continuing execution. This will be used for real dasd ipl. Add cu_type() to channel io library. This will be used to query control unit type which is used to determine if we are booting a virtio device or a real dasd device. Signed-off-by: Jason J. Herne Signed-off-by: Jason J. Herne --- pc-bios/s390-ccw/cio.c | 127 +++++++++++++++++++++++++++++++++++++++++++++= ++++ pc-bios/s390-ccw/cio.h | 25 +++++++++- 2 files changed, 151 insertions(+), 1 deletion(-) diff --git a/pc-bios/s390-ccw/cio.c b/pc-bios/s390-ccw/cio.c index 095f79b..f440380 100644 --- a/pc-bios/s390-ccw/cio.c +++ b/pc-bios/s390-ccw/cio.c @@ -10,6 +10,7 @@ =20 #include "libc.h" #include "s390-ccw.h" +#include "s390-arch.h" #include "cio.h" =20 static char chsc_page[PAGE_SIZE] __attribute__((__aligned__(PAGE_SIZE))); @@ -39,3 +40,129 @@ void enable_subchannel(SubChannelId schid) schib.pmcw.ena =3D 1; msch(schid, &schib); } + +__u16 cu_type(SubChannelId schid) +{ + Ccw1 senseIdCcw; + SenseId senseData; + + senseIdCcw.cmd_code =3D CCW_CMD_SENSE_ID; + senseIdCcw.cda =3D ptr2u32(&senseData); + senseIdCcw.count =3D sizeof(senseData); + + if (do_cio(schid, ptr2u32(&senseIdCcw), CCW_FMT1)) { + panic("Failed to run SenseID CCw\n"); + } + + return senseData.cu_type; +} + +static bool irb_error(Irb *irb) +{ + /* We have to ignore Incorrect Length (cstat =3D=3D 0x40) indicators b= ecause + * real devices expect a 24 byte SenseID buffer, and virtio devices e= xpect + * a much larger buffer. Neither device type can tolerate a buffer size + * different from what they expect so they set this indicator. + */ + if (irb->scsw.cstat !=3D 0x00 && irb->scsw.cstat !=3D 0x40) { + return true; + } + return irb->scsw.dstat !=3D 0xc; +} + +/* Executes a channel program at a given subchannel. The request to run the + * channel program is sent to the subchannel, we then wait for the interru= pt + * singaling completion of the I/O operation(s) perfomed by the channel + * program. Lastly we verify that the i/o operation completed without erro= r and + * that the interrupt we received was for the subchannel used to run the + * channel program. + * + * Note: This function assumes it is running in an environment where no ot= her + * cpus are generating or receiving I/O interrupts. So either run it in a + * single-cpu environment or make sure all other cpus are not doing I/O and + * have I/O interrupts masked off. + */ +int do_cio(SubChannelId schid, uint32_t ccw_addr, int fmt) +{ + Ccw0 *this_ccw, *prev_ccw; + CmdOrb orb =3D {}; + Irb irb =3D {}; + int rc; + + IPL_assert(fmt =3D=3D 0 || fmt =3D=3D 1, "Invalid ccw format"); + + /* ccw_addr must be <=3D 24 bits and point to at least one whole ccw. = */ + if (fmt =3D=3D 0) { + IPL_assert(ccw_addr <=3D 0xFFFFFF - 8, "Invalid ccw address"); + } + + orb.fmt =3D fmt ; + orb.pfch =3D 1; /* QEMU's cio implementation requires prefetch */ + orb.c64 =3D 1; /* QEMU's cio implementation requires 64-bit idaws */ + orb.lpm =3D 0xFF; /* All paths allowed */ + orb.cpa =3D ccw_addr; + + rc =3D ssch(schid, &orb); + if (rc) { + print_int("ssch failed with rc=3D", rc); + return rc; + } + + await_io_int(schid.sch_no); + + /* Clear read */ + rc =3D tsch(schid, &irb); + if (rc) { + print_int("tsch failed with rc=3D", rc); + return rc; + } + + if (irb_error(&irb)) { + this_ccw =3D u32toptr(irb.scsw.cpa); + prev_ccw =3D u32toptr(irb.scsw.cpa - 8); + + print_int("irb_error: cstat=3D", irb.scsw.cstat); + print_int(" dstat=3D", irb.scsw.dstat); + print_int(" cpa=3D", irb.scsw.cpa); + print_int(" prev_ccw=3D", *((uint64_t *)prev_ccw)); + print_int(" this_ccw=3D", *((uint64_t *)this_ccw)); + } + + return 0; +} + +void await_io_int(uint16_t sch_no) +{ + /* + * wait_psw and ctl6 must be static to avoid stack allocation as gcc c= annot + * align stack variables. The stctg, lctlg and lpswe instructions requ= ire + * that their operands be aligned on an 8-byte boundary. + */ + static uint64_t ctl6 __attribute__((__aligned__(8))); + static PSW wait_psw; + + /* PSW to load when I/O interrupt happens */ + lowcore->io_new_psw.mask =3D PSW_MASK_ZMODE; + lowcore->io_new_psw.addr =3D (uint64_t)&&IOIntWakeup; /* Wake-up addre= ss */ + + /* Enable io interrupts subclass mask */ + asm volatile("stctg 6,6,%0" : "=3DS" (ctl6) : : "memory"); + ctl6 |=3D 0x00000000FF000000; + asm volatile("lctlg 6,6,%0" : : "S" (ctl6)); + + /* Set wait psw enabled for io interrupt */ + wait_psw.mask =3D (PSW_MASK_ZMODE | PSW_MASK_IOINT | PSW_MASK_WAIT); + asm volatile("lpswe %0" : : "Q" (wait_psw) : "cc"); + + panic("await_io_int: lpswe failed!!\n"); + +IOIntWakeup: + /* Should never happen - all other subchannels are disabled by default= */ + IPL_assert(lowcore->subchannel_nr =3D=3D sch_no, + "Interrupt from unexpected device"); + + /* Disable all subclasses of I/O interrupts for this cpu */ + asm volatile("stctg 6,6,%0" : "=3DS" (ctl6) : : "memory"); + ctl6 &=3D ~(0x00000000FF000000); + asm volatile("lctlg 6,6,%0" : : "S" (ctl6)); +} diff --git a/pc-bios/s390-ccw/cio.h b/pc-bios/s390-ccw/cio.h index 7b07d75..d8e2955 100644 --- a/pc-bios/s390-ccw/cio.h +++ b/pc-bios/s390-ccw/cio.h @@ -127,7 +127,23 @@ struct tpi_info { __u32 reserved4 : 12; } __attribute__ ((packed, aligned(4))); =20 -/* channel command word (type 1) */ +/* channel command word (format 0) */ +typedef struct ccw0 { + __u8 cmd_code; + __u32 cda : 24; + __u32 chainData : 1; + __u32 chain : 1; + __u32 sli : 1; + __u32 skip : 1; + __u32 pci : 1; + __u32 ida : 1; + __u32 suspend : 1; + __u32 mida : 1; + __u8 reserved; + __u16 count; +} __attribute__ ((packed, aligned(8))) Ccw0; + +/* channel command word (format 1) */ typedef struct ccw1 { __u8 cmd_code; __u8 flags; @@ -135,6 +151,10 @@ typedef struct ccw1 { __u32 cda; } __attribute__ ((packed, aligned(8))) Ccw1; =20 +/* do_cio() CCW formats */ +#define CCW_FMT0 0x00 +#define CCW_FMT1 0x01 + #define CCW_FLAG_DC 0x80 #define CCW_FLAG_CC 0x40 #define CCW_FLAG_SLI 0x20 @@ -215,6 +235,9 @@ typedef struct irb { =20 int enable_mss_facility(void); void enable_subchannel(SubChannelId schid); +__u16 cu_type(SubChannelId schid); +void await_io_int(uint16_t sch_no); +int do_cio(SubChannelId schid, uint32_t ccw_addr, int fmt); =20 /* * Some S390 specific IO instructions as inline --=20 2.7.4