From nobody Tue Nov 4 18:40:41 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linux.intel.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 153069559308356.24817772689562; Wed, 4 Jul 2018 02:13:13 -0700 (PDT) Received: from localhost ([::1]:44800 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fadqa-0006CB-7d for importer@patchew.org; Wed, 04 Jul 2018 05:13:12 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50029) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fadkd-0001hG-Nb for qemu-devel@nongnu.org; Wed, 04 Jul 2018 05:07:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fadkZ-0007Oq-Uq for qemu-devel@nongnu.org; Wed, 04 Jul 2018 05:07:03 -0400 Received: from mga04.intel.com ([192.55.52.120]:53506) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fadkZ-0007OO-JS for qemu-devel@nongnu.org; Wed, 04 Jul 2018 05:06:59 -0400 Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 04 Jul 2018 02:06:54 -0700 Received: from sqa-gate.sh.intel.com (HELO robert-ivt.tsp.org) ([10.239.48.212]) by orsmga002.jf.intel.com with ESMTP; 04 Jul 2018 02:06:44 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.51,306,1526367600"; d="scan'208";a="72161377" From: Robert Hoo To: qemu-devel@nongnu.org, pbonzini@redhat.com, rth@twiddle.net, ehabkost@redhat.com Date: Wed, 4 Jul 2018 17:06:35 +0800 Message-Id: <1530695199-27601-2-git-send-email-robert.hu@linux.intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1530695199-27601-1-git-send-email-robert.hu@linux.intel.com> References: <1530695199-27601-1-git-send-email-robert.hu@linux.intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 192.55.52.120 Subject: [Qemu-devel] [PATCH v3 1/5] i386: Add new MSR indices for IA32_PRED_CMD and IA32_ARCH_CAPABILITIES X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: robert.hu@intel.com, Robert Hoo Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" IA32_PRED_CMD MSR gives software a way to issue commands that affect the st= ate of indirect branch predictors. Enumerated by CPUID.(EAX=3D7H,ECX=3D0):EDX[2= 6]. IA32_ARCH_CAPABILITIES MSR enumerates architectural features of RDCL_NO, IBRS_ALL, RSBA, SSB_NO. Enumerated by CPUID.(EAX=3D07H, ECX=3D0):EDX[29]. https://software.intel.com/sites/default/files/managed/c5/63/336996-Specula= tive-Execution-Side-Channel-Mitigations.pdf Signed-off-by: Robert Hoo --- target/i386/cpu.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 2c5a0d9..ae97005 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -354,6 +354,8 @@ typedef enum X86Seg { #define MSR_TSC_ADJUST 0x0000003b #define MSR_IA32_SPEC_CTRL 0x48 #define MSR_VIRT_SSBD 0xc001011f +#define MSR_IA32_PRED_CMD 0x49 +#define MSR_IA32_ARCH_CAPABILITIES 0x10a #define MSR_IA32_TSCDEADLINE 0x6e0 =20 #define FEATURE_CONTROL_LOCKED (1<<0) --=20 1.8.3.1