From nobody Mon Feb 9 15:13:28 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530271121994134.82329865852898; Fri, 29 Jun 2018 04:18:41 -0700 (PDT) Received: from localhost ([::1]:41209 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYrQG-0000vu-EL for importer@patchew.org; Fri, 29 Jun 2018 07:18:40 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36378) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYrO0-0008Fl-9R for qemu-devel@nongnu.org; Fri, 29 Jun 2018 07:16:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fYrNw-00029C-O1 for qemu-devel@nongnu.org; Fri, 29 Jun 2018 07:16:20 -0400 Received: from foss.arm.com ([217.140.101.70]:39228) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYrNw-00028U-GZ for qemu-devel@nongnu.org; Fri, 29 Jun 2018 07:16:16 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 00FB01529; Fri, 29 Jun 2018 04:16:16 -0700 (PDT) Received: from en101.cambridge.arm.com (en101.cambridge.arm.com [10.1.206.73]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 104AB3F266; Fri, 29 Jun 2018 04:16:12 -0700 (PDT) From: Suzuki K Poulose To: linux-arm-kernel@lists.infradead.org Date: Fri, 29 Jun 2018 12:15:21 +0100 Message-Id: <1530270944-11351-2-git-send-email-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1530270944-11351-1-git-send-email-suzuki.poulose@arm.com> References: <1530270944-11351-1-git-send-email-suzuki.poulose@arm.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 217.140.101.70 Subject: [Qemu-devel] [PATCH v3 01/20] virtio: mmio-v1: Validate queue PFN X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydel , cdall@kernel.org, kvm@vger.kernel.org, Suzuki K Poulose , marc.zyngier@arm.com, catalin.marinas@arm.com, Jason Wang , punit.agrawal@arm.com, will.deacon@arm.com, linux-kernel@vger.kernel.org, qemu-devel@nongnu.org, eric.auger@redhat.com, julien.grall@arm.com, james.morse@arm.com, Jean-Philippe Brucker , "Michael S. Tsirkin" , kvmarm@lists.cs.columbia.edu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" virtio-mmio with virtio-v1 uses a 32bit PFN for the queue. If the queue pfn is too large to fit in 32bits, which we could hit on arm64 systems with 52bit physical addresses (even with 64K page size), we simply miss out a proper link to the other side of the queue. Add a check to validate the PFN, rather than silently breaking the devices. Cc: "Michael S. Tsirkin" Cc: Jason Wang Cc: Marc Zyngier Cc: Christoffer Dall Cc: Peter Maydel Cc: Jean-Philippe Brucker Signed-off-by: Suzuki K Poulose --- Changes since v2: - Change errno to -E2BIG --- drivers/virtio/virtio_mmio.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/virtio/virtio_mmio.c b/drivers/virtio/virtio_mmio.c index 67763d3..82cedc8 100644 --- a/drivers/virtio/virtio_mmio.c +++ b/drivers/virtio/virtio_mmio.c @@ -397,9 +397,21 @@ static struct virtqueue *vm_setup_vq(struct virtio_dev= ice *vdev, unsigned index, /* Activate the queue */ writel(virtqueue_get_vring_size(vq), vm_dev->base + VIRTIO_MMIO_QUEUE_NUM= ); if (vm_dev->version =3D=3D 1) { + u64 q_pfn =3D virtqueue_get_desc_addr(vq) >> PAGE_SHIFT; + + /* + * virtio-mmio v1 uses a 32bit QUEUE PFN. If we have something + * that doesn't fit in 32bit, fail the setup rather than + * pretending to be successful. + */ + if (q_pfn >> 32) { + dev_err(&vdev->dev, "virtio-mmio: queue address too large\n"); + err =3D -E2BIG; + goto error_bad_pfn; + } + writel(PAGE_SIZE, vm_dev->base + VIRTIO_MMIO_QUEUE_ALIGN); - writel(virtqueue_get_desc_addr(vq) >> PAGE_SHIFT, - vm_dev->base + VIRTIO_MMIO_QUEUE_PFN); + writel(q_pfn, vm_dev->base + VIRTIO_MMIO_QUEUE_PFN); } else { u64 addr; =20 @@ -430,6 +442,8 @@ static struct virtqueue *vm_setup_vq(struct virtio_devi= ce *vdev, unsigned index, =20 return vq; =20 +error_bad_pfn: + vring_del_virtqueue(vq); error_new_virtqueue: if (vm_dev->version =3D=3D 1) { writel(0, vm_dev->base + VIRTIO_MMIO_QUEUE_PFN); --=20 2.7.4 From nobody Mon Feb 9 15:13:28 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530271310670664.5305720043729; Fri, 29 Jun 2018 04:21:50 -0700 (PDT) Received: from localhost ([::1]:41227 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYrTE-0003fQ-02 for importer@patchew.org; Fri, 29 Jun 2018 07:21:44 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36392) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYrO0-0008Fp-Us for qemu-devel@nongnu.org; Fri, 29 Jun 2018 07:16:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fYrNz-0002Cf-TS for qemu-devel@nongnu.org; Fri, 29 Jun 2018 07:16:20 -0400 Received: from foss.arm.com ([217.140.101.70]:39246) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYrNz-0002Bo-Mb for qemu-devel@nongnu.org; Fri, 29 Jun 2018 07:16:19 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3114615AD; Fri, 29 Jun 2018 04:16:19 -0700 (PDT) Received: from en101.cambridge.arm.com (en101.cambridge.arm.com [10.1.206.73]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 411A03F266; Fri, 29 Jun 2018 04:16:16 -0700 (PDT) From: Suzuki K Poulose To: linux-arm-kernel@lists.infradead.org Date: Fri, 29 Jun 2018 12:15:22 +0100 Message-Id: <1530270944-11351-3-git-send-email-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1530270944-11351-1-git-send-email-suzuki.poulose@arm.com> References: <1530270944-11351-1-git-send-email-suzuki.poulose@arm.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 217.140.101.70 Subject: [Qemu-devel] [PATCH v3 02/20] virtio: pci-legacy: Validate queue pfn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydel , cdall@kernel.org, kvm@vger.kernel.org, Suzuki K Poulose , marc.zyngier@arm.com, catalin.marinas@arm.com, Jason Wang , punit.agrawal@arm.com, will.deacon@arm.com, linux-kernel@vger.kernel.org, qemu-devel@nongnu.org, eric.auger@redhat.com, julien.grall@arm.com, james.morse@arm.com, Jean-Philippe Brucker , "Michael S. Tsirkin" , kvmarm@lists.cs.columbia.edu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Legacy PCI over virtio uses a 32bit PFN for the queue. If the queue pfn is too large to fit in 32bits, which we could hit on arm64 systems with 52bit physical addresses (even with 64K page size), we simply miss out a proper link to the other side of the queue. Add a check to validate the PFN, rather than silently breaking the devices. Cc: "Michael S. Tsirkin" Cc: Jason Wang Cc: Marc Zyngier Cc: Christoffer Dall Cc: Peter Maydel Cc: Jean-Philippe Brucker Signed-off-by: Suzuki K Poulose --- Changes since v2: - Change errno to -E2BIG --- drivers/virtio/virtio_pci_legacy.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/virtio/virtio_pci_legacy.c b/drivers/virtio/virtio_pci= _legacy.c index 2780886..c0d6987a 100644 --- a/drivers/virtio/virtio_pci_legacy.c +++ b/drivers/virtio/virtio_pci_legacy.c @@ -122,6 +122,7 @@ static struct virtqueue *setup_vq(struct virtio_pci_dev= ice *vp_dev, struct virtqueue *vq; u16 num; int err; + u64 q_pfn; =20 /* Select the queue we're interested in */ iowrite16(index, vp_dev->ioaddr + VIRTIO_PCI_QUEUE_SEL); @@ -141,9 +142,15 @@ static struct virtqueue *setup_vq(struct virtio_pci_de= vice *vp_dev, if (!vq) return ERR_PTR(-ENOMEM); =20 + q_pfn =3D virtqueue_get_desc_addr(vq) >> VIRTIO_PCI_QUEUE_ADDR_SHIFT; + if (q_pfn >> 32) { + dev_err(&vp_dev->pci_dev->dev, "virtio-pci queue PFN too large\n"); + err =3D -E2BIG; + goto out_del_vq; + } + /* activate the queue */ - iowrite32(virtqueue_get_desc_addr(vq) >> VIRTIO_PCI_QUEUE_ADDR_SHIFT, - vp_dev->ioaddr + VIRTIO_PCI_QUEUE_PFN); + iowrite32(q_pfn, vp_dev->ioaddr + VIRTIO_PCI_QUEUE_PFN); =20 vq->priv =3D (void __force *)vp_dev->ioaddr + VIRTIO_PCI_QUEUE_NOTIFY; =20 @@ -160,6 +167,7 @@ static struct virtqueue *setup_vq(struct virtio_pci_dev= ice *vp_dev, =20 out_deactivate: iowrite32(0, vp_dev->ioaddr + VIRTIO_PCI_QUEUE_PFN); +out_del_vq: vring_del_virtqueue(vq); return ERR_PTR(err); } --=20 2.7.4 From nobody Mon Feb 9 15:13:28 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530271130176668.4921799950904; Fri, 29 Jun 2018 04:18:50 -0700 (PDT) Received: from localhost ([::1]:41211 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYrQP-00013i-Ay for importer@patchew.org; Fri, 29 Jun 2018 07:18:49 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36407) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYrO3-0008Gp-IM for qemu-devel@nongnu.org; Fri, 29 Jun 2018 07:16:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fYrO2-0002FP-Pe for qemu-devel@nongnu.org; Fri, 29 Jun 2018 07:16:23 -0400 Received: from foss.arm.com ([217.140.101.70]:39262) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYrO2-0002Ep-Ip for qemu-devel@nongnu.org; Fri, 29 Jun 2018 07:16:22 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C59F61682; Fri, 29 Jun 2018 04:16:21 -0700 (PDT) Received: from en101.cambridge.arm.com (en101.cambridge.arm.com [10.1.206.73]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 6EF483F266; Fri, 29 Jun 2018 04:16:19 -0700 (PDT) From: Suzuki K Poulose To: linux-arm-kernel@lists.infradead.org Date: Fri, 29 Jun 2018 12:15:23 +0100 Message-Id: <1530270944-11351-4-git-send-email-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1530270944-11351-1-git-send-email-suzuki.poulose@arm.com> References: <1530270944-11351-1-git-send-email-suzuki.poulose@arm.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 217.140.101.70 Subject: [Qemu-devel] [PATCH v3 03/20] arm64: Add a helper for PARange to physical shift conversion X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cdall@kernel.org, kvm@vger.kernel.org, Suzuki K Poulose , marc.zyngier@arm.com, catalin.marinas@arm.com, punit.agrawal@arm.com, will.deacon@arm.com, linux-kernel@vger.kernel.org, qemu-devel@nongnu.org, eric.auger@redhat.com, julien.grall@arm.com, james.morse@arm.com, kvmarm@lists.cs.columbia.edu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" On arm64, ID_AA64MMFR0_EL1.PARange encodes the maximum Physical Address range supported by the CPU. Add a helper to decode this to actual physical shift. If we hit an unallocated value, return the maximum range supported by the kernel. This is will be used by the KVM to set the VTCR_EL2.T0SZ, as it is about to move its place. Having this helper keeps the code movement cleaner. Cc: Catalin Marinas Cc: Marc Zyngier Cc: James Morse Cc: Christoffer Dall Signed-off-by: Suzuki K Poulose Reviewed-by: Eric Auger --- Changes since V2: - Split the patch - Limit the physical shift only for values unrecognized. --- arch/arm64/include/asm/cpufeature.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/c= pufeature.h index 1717ba1..855cf0e 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -530,6 +530,19 @@ void arm64_set_ssbd_mitigation(bool state); static inline void arm64_set_ssbd_mitigation(bool state) {} #endif =20 +static inline u32 id_aa64mmfr0_parange_to_phys_shift(int parange) +{ + switch (parange) { + case 0: return 32; + case 1: return 36; + case 2: return 40; + case 3: return 42; + case 4: return 44; + case 5: return 48; + case 6: return 52; + default: return CONFIG_ARM64_PA_BITS; + } +} #endif /* __ASSEMBLY__ */ =20 #endif --=20 2.7.4 From nobody Mon Feb 9 15:13:28 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 153027114659639.65177080641661; Fri, 29 Jun 2018 04:19:06 -0700 (PDT) Received: from localhost ([::1]:41212 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYrQf-0001CJ-OX for importer@patchew.org; Fri, 29 Jun 2018 07:19:05 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36423) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYrO6-0008J1-4F for qemu-devel@nongnu.org; Fri, 29 Jun 2018 07:16:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fYrO5-0002Go-69 for qemu-devel@nongnu.org; Fri, 29 Jun 2018 07:16:26 -0400 Received: from foss.arm.com ([217.140.101.70]:39280) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYrO4-0002GL-VN for qemu-devel@nongnu.org; Fri, 29 Jun 2018 07:16:25 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6651A1684; Fri, 29 Jun 2018 04:16:24 -0700 (PDT) Received: from en101.cambridge.arm.com (en101.cambridge.arm.com [10.1.206.73]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 0F87C3F266; Fri, 29 Jun 2018 04:16:21 -0700 (PDT) From: Suzuki K Poulose To: linux-arm-kernel@lists.infradead.org Date: Fri, 29 Jun 2018 12:15:24 +0100 Message-Id: <1530270944-11351-5-git-send-email-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1530270944-11351-1-git-send-email-suzuki.poulose@arm.com> References: <1530270944-11351-1-git-send-email-suzuki.poulose@arm.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 217.140.101.70 Subject: [Qemu-devel] [PATCH v3 04/20] kvm: arm64: Clean up VTCR_EL2 initialisation X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cdall@kernel.org, kvm@vger.kernel.org, Suzuki K Poulose , marc.zyngier@arm.com, catalin.marinas@arm.com, punit.agrawal@arm.com, will.deacon@arm.com, linux-kernel@vger.kernel.org, qemu-devel@nongnu.org, eric.auger@redhat.com, julien.grall@arm.com, james.morse@arm.com, kvmarm@lists.cs.columbia.edu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Use the new helper for converting the parange to the physical shift. Also, add the missing definitions for the VTCR_EL2 register fields and use them instead of hard coding numbers. Cc: Marc Zyngier Cc: Christoffer Dall Signed-off-by: Suzuki K Poulose Reviewed-by: Eric Auger --- Changes since V2 - Part 2 of the split from original patch. - Also add missing VTCR field helpers and use them. --- arch/arm64/include/asm/kvm_arm.h | 3 +++ arch/arm64/kvm/hyp/s2-setup.c | 30 ++++++------------------------ 2 files changed, 9 insertions(+), 24 deletions(-) diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_= arm.h index 6dd285e..3dffd38 100644 --- a/arch/arm64/include/asm/kvm_arm.h +++ b/arch/arm64/include/asm/kvm_arm.h @@ -106,6 +106,7 @@ #define VTCR_EL2_RES1 (1 << 31) #define VTCR_EL2_HD (1 << 22) #define VTCR_EL2_HA (1 << 21) +#define VTCR_EL2_PS_SHIFT TCR_EL2_PS_SHIFT #define VTCR_EL2_PS_MASK TCR_EL2_PS_MASK #define VTCR_EL2_TG0_MASK TCR_TG0_MASK #define VTCR_EL2_TG0_4K TCR_TG0_4K @@ -126,6 +127,8 @@ #define VTCR_EL2_VS_8BIT (0 << VTCR_EL2_VS_SHIFT) #define VTCR_EL2_VS_16BIT (1 << VTCR_EL2_VS_SHIFT) =20 +#define VTCR_EL2_T0SZ(x) TCR_T0SZ(x) + /* * We configure the Stage-2 page tables to always restrict the IPA space t= o be * 40 bits wide (T0SZ =3D 24). Systems with a PARange smaller than 40 bit= s are diff --git a/arch/arm64/kvm/hyp/s2-setup.c b/arch/arm64/kvm/hyp/s2-setup.c index 603e1ee..81094f1 100644 --- a/arch/arm64/kvm/hyp/s2-setup.c +++ b/arch/arm64/kvm/hyp/s2-setup.c @@ -19,11 +19,13 @@ #include #include #include +#include =20 u32 __hyp_text __init_stage2_translation(void) { u64 val =3D VTCR_EL2_FLAGS; u64 parange; + u32 phys_shift; u64 tmp; =20 /* @@ -34,30 +36,10 @@ u32 __hyp_text __init_stage2_translation(void) parange =3D read_sysreg(id_aa64mmfr0_el1) & 7; if (parange > ID_AA64MMFR0_PARANGE_MAX) parange =3D ID_AA64MMFR0_PARANGE_MAX; - val |=3D parange << 16; + val |=3D parange << VTCR_EL2_PS_SHIFT; =20 /* Compute the actual PARange... */ - switch (parange) { - case 0: - parange =3D 32; - break; - case 1: - parange =3D 36; - break; - case 2: - parange =3D 40; - break; - case 3: - parange =3D 42; - break; - case 4: - parange =3D 44; - break; - case 5: - default: - parange =3D 48; - break; - } + phys_shift =3D id_aa64mmfr0_parange_to_phys_shift(parange); =20 /* * ... and clamp it to 40 bits, unless we have some braindead @@ -65,7 +47,7 @@ u32 __hyp_text __init_stage2_translation(void) * return that value for the rest of the kernel to decide what * to do. */ - val |=3D 64 - (parange > 40 ? 40 : parange); + val |=3D VTCR_EL2_T0SZ(phys_shift > 40 ? 40 : phys_shift); =20 /* * Check the availability of Hardware Access Flag / Dirty Bit @@ -86,5 +68,5 @@ u32 __hyp_text __init_stage2_translation(void) =20 write_sysreg(val, vtcr_el2); =20 - return parange; + return phys_shift; } --=20 2.7.4 From nobody Mon Feb 9 15:13:28 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530271324183909.7319897718522; Fri, 29 Jun 2018 04:22:04 -0700 (PDT) Received: from localhost ([::1]:41230 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYrTX-0003u5-EA for importer@patchew.org; Fri, 29 Jun 2018 07:22:03 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36446) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYrOB-0008NE-4j for qemu-devel@nongnu.org; Fri, 29 Jun 2018 07:16:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fYrO7-0002IU-Q0 for qemu-devel@nongnu.org; Fri, 29 Jun 2018 07:16:31 -0400 Received: from foss.arm.com ([217.140.101.70]:39296) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYrO7-0002I7-JY for qemu-devel@nongnu.org; Fri, 29 Jun 2018 07:16:27 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1026C15AD; Fri, 29 Jun 2018 04:16:27 -0700 (PDT) Received: from en101.cambridge.arm.com (en101.cambridge.arm.com [10.1.206.73]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id A3E423F266; Fri, 29 Jun 2018 04:16:24 -0700 (PDT) From: Suzuki K Poulose To: linux-arm-kernel@lists.infradead.org Date: Fri, 29 Jun 2018 12:15:25 +0100 Message-Id: <1530270944-11351-6-git-send-email-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1530270944-11351-1-git-send-email-suzuki.poulose@arm.com> References: <1530270944-11351-1-git-send-email-suzuki.poulose@arm.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 217.140.101.70 Subject: [Qemu-devel] [PATCH v3 05/20] kvm: arm/arm64: Fix stage2_flush_memslot for 4 level page table X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cdall@kernel.org, kvm@vger.kernel.org, Suzuki K Poulose , marc.zyngier@arm.com, catalin.marinas@arm.com, punit.agrawal@arm.com, will.deacon@arm.com, linux-kernel@vger.kernel.org, qemu-devel@nongnu.org, eric.auger@redhat.com, julien.grall@arm.com, james.morse@arm.com, kvmarm@lists.cs.columbia.edu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" So far we have only supported 3 level page table with fixed IPA of 40bits. Fix stage2_flush_memslot() to accommodate for 4 level tables. Cc: Marc Zyngier Acked-by: Christoffer Dall Signed-off-by: Suzuki K Poulose Reviewed-by: Eric Auger Reviewed-by: Marc Zyngier --- virt/kvm/arm/mmu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/virt/kvm/arm/mmu.c b/virt/kvm/arm/mmu.c index 1d90d79..061e6b3 100644 --- a/virt/kvm/arm/mmu.c +++ b/virt/kvm/arm/mmu.c @@ -379,7 +379,8 @@ static void stage2_flush_memslot(struct kvm *kvm, pgd =3D kvm->arch.pgd + stage2_pgd_index(addr); do { next =3D stage2_pgd_addr_end(addr, end); - stage2_flush_puds(kvm, pgd, addr, next); + if (!stage2_pgd_none(*pgd)) + stage2_flush_puds(kvm, pgd, addr, next); } while (pgd++, addr =3D next, addr !=3D end); } =20 --=20 2.7.4 From nobody Mon Feb 9 15:13:28 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530271310759143.5241617695923; Fri, 29 Jun 2018 04:21:50 -0700 (PDT) Received: from localhost ([::1]:41228 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYrTK-0003kX-28 for importer@patchew.org; Fri, 29 Jun 2018 07:21:50 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36448) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYrOB-0008NT-BK for qemu-devel@nongnu.org; Fri, 29 Jun 2018 07:16:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fYrOA-0002Jp-DA for qemu-devel@nongnu.org; Fri, 29 Jun 2018 07:16:31 -0400 Received: from foss.arm.com ([217.140.101.70]:39310) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYrOA-0002JW-70 for qemu-devel@nongnu.org; Fri, 29 Jun 2018 07:16:30 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id AE7EE18A; Fri, 29 Jun 2018 04:16:29 -0700 (PDT) Received: from en101.cambridge.arm.com (en101.cambridge.arm.com [10.1.206.73]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 4DD553F266; Fri, 29 Jun 2018 04:16:27 -0700 (PDT) From: Suzuki K Poulose To: linux-arm-kernel@lists.infradead.org Date: Fri, 29 Jun 2018 12:15:26 +0100 Message-Id: <1530270944-11351-7-git-send-email-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1530270944-11351-1-git-send-email-suzuki.poulose@arm.com> References: <1530270944-11351-1-git-send-email-suzuki.poulose@arm.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 217.140.101.70 Subject: [Qemu-devel] [PATCH v3 06/20] kvm: arm/arm64: Remove spurious WARN_ON X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cdall@kernel.org, kvm@vger.kernel.org, Suzuki K Poulose , marc.zyngier@arm.com, catalin.marinas@arm.com, punit.agrawal@arm.com, will.deacon@arm.com, linux-kernel@vger.kernel.org, qemu-devel@nongnu.org, eric.auger@redhat.com, julien.grall@arm.com, james.morse@arm.com, kvmarm@lists.cs.columbia.edu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" On a 4-level page table pgd entry can be empty, unlike a 3-level page table. Remove the spurious WARN_ON() in stage_get_pud(). Cc: Marc Zyngier Acked-by: Christoffer Dall Signed-off-by: Suzuki K Poulose Acked-by: Marc Zyngier Reviewed-by: Eric Auger --- virt/kvm/arm/mmu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/virt/kvm/arm/mmu.c b/virt/kvm/arm/mmu.c index 061e6b3..308171c 100644 --- a/virt/kvm/arm/mmu.c +++ b/virt/kvm/arm/mmu.c @@ -976,7 +976,7 @@ static pud_t *stage2_get_pud(struct kvm *kvm, struct kv= m_mmu_memory_cache *cache pud_t *pud; =20 pgd =3D kvm->arch.pgd + stage2_pgd_index(addr); - if (WARN_ON(stage2_pgd_none(*pgd))) { + if (stage2_pgd_none(*pgd)) { if (!cache) return NULL; pud =3D mmu_memory_cache_alloc(cache); --=20 2.7.4 From nobody Mon Feb 9 15:13:28 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530271497363882.0101205352017; Fri, 29 Jun 2018 04:24:57 -0700 (PDT) Received: from localhost ([::1]:41243 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYrWK-0006CU-Fe for importer@patchew.org; Fri, 29 Jun 2018 07:24:56 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36482) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYrOG-0008SX-GA for qemu-devel@nongnu.org; Fri, 29 Jun 2018 07:16:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fYrOD-0002L0-Bd for qemu-devel@nongnu.org; Fri, 29 Jun 2018 07:16:36 -0400 Received: from foss.arm.com ([217.140.101.70]:39324) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYrOC-0002Km-VO for qemu-devel@nongnu.org; Fri, 29 Jun 2018 07:16:33 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 725611529; Fri, 29 Jun 2018 04:16:32 -0700 (PDT) Received: from en101.cambridge.arm.com (en101.cambridge.arm.com [10.1.206.73]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id EC42A3F266; Fri, 29 Jun 2018 04:16:29 -0700 (PDT) From: Suzuki K Poulose To: linux-arm-kernel@lists.infradead.org Date: Fri, 29 Jun 2018 12:15:27 +0100 Message-Id: <1530270944-11351-8-git-send-email-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1530270944-11351-1-git-send-email-suzuki.poulose@arm.com> References: <1530270944-11351-1-git-send-email-suzuki.poulose@arm.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 217.140.101.70 Subject: [Qemu-devel] [PATCH v3 07/20] kvm: arm/arm64: Prepare for VM specific stage2 translations X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cdall@kernel.org, kvm@vger.kernel.org, Suzuki K Poulose , marc.zyngier@arm.com, catalin.marinas@arm.com, punit.agrawal@arm.com, will.deacon@arm.com, linux-kernel@vger.kernel.org, qemu-devel@nongnu.org, eric.auger@redhat.com, julien.grall@arm.com, james.morse@arm.com, kvmarm@lists.cs.columbia.edu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Right now the stage2 page table for a VM is hard coded, assuming an IPA of 40bits. As we are about to add support for per VM IPA, prepare the stage2 page table helpers to accept the kvm instance to make the right decision for the VM. No functional changes. Adds stage2_pgd_size(kvm) to replace S2_PGD_SIZE. Also, moves some of the definitions dependent on kvm instance to asm/kvm_mmu.h for arm32. In that process drop the _AC() specifier constants Cc: Marc Zyngier Cc: Christoffer Dall Signed-off-by: Suzuki K Poulose Acked-by: Marc Zyngier --- Changes since V2: - Update commit description abuot the movement to asm/kvm_mmu.h for arm32 - Drop _AC() specifiers --- arch/arm/include/asm/kvm_arm.h | 3 +- arch/arm/include/asm/kvm_mmu.h | 15 +++- arch/arm/include/asm/stage2_pgtable.h | 42 ++++----- arch/arm64/include/asm/kvm_mmu.h | 7 +- arch/arm64/include/asm/stage2_pgtable-nopmd.h | 18 ++-- arch/arm64/include/asm/stage2_pgtable-nopud.h | 16 ++-- arch/arm64/include/asm/stage2_pgtable.h | 49 ++++++----- virt/kvm/arm/arm.c | 2 +- virt/kvm/arm/mmu.c | 119 +++++++++++++---------= ---- virt/kvm/arm/vgic/vgic-kvm-device.c | 2 +- 10 files changed, 148 insertions(+), 125 deletions(-) diff --git a/arch/arm/include/asm/kvm_arm.h b/arch/arm/include/asm/kvm_arm.h index 3ab8b37..c3f1f9b 100644 --- a/arch/arm/include/asm/kvm_arm.h +++ b/arch/arm/include/asm/kvm_arm.h @@ -133,8 +133,7 @@ * space. */ #define KVM_PHYS_SHIFT (40) -#define KVM_PHYS_SIZE (_AC(1, ULL) << KVM_PHYS_SHIFT) -#define KVM_PHYS_MASK (KVM_PHYS_SIZE - _AC(1, ULL)) + #define PTRS_PER_S2_PGD (_AC(1, ULL) << (KVM_PHYS_SHIFT - 30)) =20 /* Virtualization Translation Control Register (VTCR) bits */ diff --git a/arch/arm/include/asm/kvm_mmu.h b/arch/arm/include/asm/kvm_mmu.h index 8553d68..f36eb20 100644 --- a/arch/arm/include/asm/kvm_mmu.h +++ b/arch/arm/include/asm/kvm_mmu.h @@ -36,15 +36,19 @@ }) =20 /* - * KVM_MMU_CACHE_MIN_PAGES is the number of stage2 page table translation = levels. + * kvm_mmu_cache_min_pages() is the number of stage2 page + * table translation levels, excluding the top level, for + * the given VM. Since we have a 3 level page-table, this + * is fixed. */ -#define KVM_MMU_CACHE_MIN_PAGES 2 +#define kvm_mmu_cache_min_pages(kvm) 2 =20 #ifndef __ASSEMBLY__ =20 #include #include #include +#include #include #include #include @@ -52,6 +56,13 @@ /* Ensure compatibility with arm64 */ #define VA_BITS 32 =20 +#define kvm_phys_shift(kvm) KVM_PHYS_SHIFT +#define kvm_phys_size(kvm) (1ULL << kvm_phys_shift(kvm)) +#define kvm_phys_mask(kvm) (kvm_phys_size(kvm) - 1ULL) +#define kvm_vttbr_baddr_mask(kvm) VTTBR_BADDR_MASK + +#define stage2_pgd_size(kvm) (PTRS_PER_S2_PGD * sizeof(pgd_t)) + int create_hyp_mappings(void *from, void *to, pgprot_t prot); int create_hyp_io_mappings(phys_addr_t phys_addr, size_t size, void __iomem **kaddr, diff --git a/arch/arm/include/asm/stage2_pgtable.h b/arch/arm/include/asm/s= tage2_pgtable.h index 460d616..e22ae94 100644 --- a/arch/arm/include/asm/stage2_pgtable.h +++ b/arch/arm/include/asm/stage2_pgtable.h @@ -19,43 +19,45 @@ #ifndef __ARM_S2_PGTABLE_H_ #define __ARM_S2_PGTABLE_H_ =20 -#define stage2_pgd_none(pgd) pgd_none(pgd) -#define stage2_pgd_clear(pgd) pgd_clear(pgd) -#define stage2_pgd_present(pgd) pgd_present(pgd) -#define stage2_pgd_populate(pgd, pud) pgd_populate(NULL, pgd, pud) -#define stage2_pud_offset(pgd, address) pud_offset(pgd, address) -#define stage2_pud_free(pud) pud_free(NULL, pud) +#define stage2_pgd_none(kvm, pgd) pgd_none(pgd) +#define stage2_pgd_clear(kvm, pgd) pgd_clear(pgd) +#define stage2_pgd_present(kvm, pgd) pgd_present(pgd) +#define stage2_pgd_populate(kvm, pgd, pud) pgd_populate(NULL, pgd, pud) +#define stage2_pud_offset(kvm, pgd, address) pud_offset(pgd, address) +#define stage2_pud_free(kvm, pud) pud_free(NULL, pud) =20 -#define stage2_pud_none(pud) pud_none(pud) -#define stage2_pud_clear(pud) pud_clear(pud) -#define stage2_pud_present(pud) pud_present(pud) -#define stage2_pud_populate(pud, pmd) pud_populate(NULL, pud, pmd) -#define stage2_pmd_offset(pud, address) pmd_offset(pud, address) -#define stage2_pmd_free(pmd) pmd_free(NULL, pmd) +#define stage2_pud_none(kvm, pud) pud_none(pud) +#define stage2_pud_clear(kvm, pud) pud_clear(pud) +#define stage2_pud_present(kvm, pud) pud_present(pud) +#define stage2_pud_populate(kvm, pud, pmd) pud_populate(NULL, pud, pmd) +#define stage2_pmd_offset(kvm, pud, address) pmd_offset(pud, address) +#define stage2_pmd_free(kvm, pmd) pmd_free(NULL, pmd) =20 -#define stage2_pud_huge(pud) pud_huge(pud) +#define stage2_pud_huge(kvm, pud) pud_huge(pud) =20 /* Open coded p*d_addr_end that can deal with 64bit addresses */ -static inline phys_addr_t stage2_pgd_addr_end(phys_addr_t addr, phys_addr_= t end) +static inline phys_addr_t +stage2_pgd_addr_end(struct kvm *kvm, phys_addr_t addr, phys_addr_t end) { phys_addr_t boundary =3D (addr + PGDIR_SIZE) & PGDIR_MASK; =20 return (boundary - 1 < end - 1) ? boundary : end; } =20 -#define stage2_pud_addr_end(addr, end) (end) +#define stage2_pud_addr_end(kvm, addr, end) (end) =20 -static inline phys_addr_t stage2_pmd_addr_end(phys_addr_t addr, phys_addr_= t end) +static inline phys_addr_t +stage2_pmd_addr_end(struct kvm *kvm, phys_addr_t addr, phys_addr_t end) { phys_addr_t boundary =3D (addr + PMD_SIZE) & PMD_MASK; =20 return (boundary - 1 < end - 1) ? boundary : end; } =20 -#define stage2_pgd_index(addr) pgd_index(addr) +#define stage2_pgd_index(kvm, addr) pgd_index(addr) =20 -#define stage2_pte_table_empty(ptep) kvm_page_empty(ptep) -#define stage2_pmd_table_empty(pmdp) kvm_page_empty(pmdp) -#define stage2_pud_table_empty(pudp) false +#define stage2_pte_table_empty(kvm, ptep) kvm_page_empty(ptep) +#define stage2_pmd_table_empty(kvm, pmdp) kvm_page_empty(pmdp) +#define stage2_pud_table_empty(kvm, pudp) false =20 #endif /* __ARM_S2_PGTABLE_H_ */ diff --git a/arch/arm64/include/asm/kvm_mmu.h b/arch/arm64/include/asm/kvm_= mmu.h index fb9a712..5da8f52 100644 --- a/arch/arm64/include/asm/kvm_mmu.h +++ b/arch/arm64/include/asm/kvm_mmu.h @@ -141,8 +141,11 @@ static inline unsigned long __kern_hyp_va(unsigned lon= g v) * We currently only support a 40bit IPA. */ #define KVM_PHYS_SHIFT (40) -#define KVM_PHYS_SIZE (1UL << KVM_PHYS_SHIFT) -#define KVM_PHYS_MASK (KVM_PHYS_SIZE - 1UL) + +#define kvm_phys_shift(kvm) KVM_PHYS_SHIFT +#define kvm_phys_size(kvm) (_AC(1, ULL) << kvm_phys_shift(kvm)) +#define kvm_phys_mask(kvm) (kvm_phys_size(kvm) - _AC(1, ULL)) +#define kvm_vttbr_baddr_mask(kvm) VTTBR_BADDR_MASK =20 #include =20 diff --git a/arch/arm64/include/asm/stage2_pgtable-nopmd.h b/arch/arm64/inc= lude/asm/stage2_pgtable-nopmd.h index 2656a0f..0280ded 100644 --- a/arch/arm64/include/asm/stage2_pgtable-nopmd.h +++ b/arch/arm64/include/asm/stage2_pgtable-nopmd.h @@ -26,17 +26,17 @@ #define S2_PMD_SIZE (1UL << S2_PMD_SHIFT) #define S2_PMD_MASK (~(S2_PMD_SIZE-1)) =20 -#define stage2_pud_none(pud) (0) -#define stage2_pud_present(pud) (1) -#define stage2_pud_clear(pud) do { } while (0) -#define stage2_pud_populate(pud, pmd) do { } while (0) -#define stage2_pmd_offset(pud, address) ((pmd_t *)(pud)) +#define stage2_pud_none(kvm, pud) (0) +#define stage2_pud_present(kvm, pud) (1) +#define stage2_pud_clear(kvm, pud) do { } while (0) +#define stage2_pud_populate(kvm, pud, pmd) do { } while (0) +#define stage2_pmd_offset(kvm, pud, address) ((pmd_t *)(pud)) =20 -#define stage2_pmd_free(pmd) do { } while (0) +#define stage2_pmd_free(kvm, pmd) do { } while (0) =20 -#define stage2_pmd_addr_end(addr, end) (end) +#define stage2_pmd_addr_end(kvm, addr, end) (end) =20 -#define stage2_pud_huge(pud) (0) -#define stage2_pmd_table_empty(pmdp) (0) +#define stage2_pud_huge(kvm, pud) (0) +#define stage2_pmd_table_empty(kvm, pmdp) (0) =20 #endif diff --git a/arch/arm64/include/asm/stage2_pgtable-nopud.h b/arch/arm64/inc= lude/asm/stage2_pgtable-nopud.h index 5ee87b5..cd6304e 100644 --- a/arch/arm64/include/asm/stage2_pgtable-nopud.h +++ b/arch/arm64/include/asm/stage2_pgtable-nopud.h @@ -24,16 +24,16 @@ #define S2_PUD_SIZE (_AC(1, UL) << S2_PUD_SHIFT) #define S2_PUD_MASK (~(S2_PUD_SIZE-1)) =20 -#define stage2_pgd_none(pgd) (0) -#define stage2_pgd_present(pgd) (1) -#define stage2_pgd_clear(pgd) do { } while (0) -#define stage2_pgd_populate(pgd, pud) do { } while (0) +#define stage2_pgd_none(kvm, pgd) (0) +#define stage2_pgd_present(kvm, pgd) (1) +#define stage2_pgd_clear(kvm, pgd) do { } while (0) +#define stage2_pgd_populate(kvm, pgd, pud) do { } while (0) =20 -#define stage2_pud_offset(pgd, address) ((pud_t *)(pgd)) +#define stage2_pud_offset(kvm, pgd, address) ((pud_t *)(pgd)) =20 -#define stage2_pud_free(x) do { } while (0) +#define stage2_pud_free(kvm, x) do { } while (0) =20 -#define stage2_pud_addr_end(addr, end) (end) -#define stage2_pud_table_empty(pmdp) (0) +#define stage2_pud_addr_end(kvm, addr, end) (end) +#define stage2_pud_table_empty(kvm, pmdp) (0) =20 #endif diff --git a/arch/arm64/include/asm/stage2_pgtable.h b/arch/arm64/include/a= sm/stage2_pgtable.h index 8b68099..057a405 100644 --- a/arch/arm64/include/asm/stage2_pgtable.h +++ b/arch/arm64/include/asm/stage2_pgtable.h @@ -65,10 +65,10 @@ #define PTRS_PER_S2_PGD (1 << (KVM_PHYS_SHIFT - S2_PGDIR_SHIFT)) =20 /* - * KVM_MMU_CACHE_MIN_PAGES is the number of stage2 page table translation + * kvm_mmmu_cache_min_pages is the number of stage2 page table translation * levels in addition to the PGD. */ -#define KVM_MMU_CACHE_MIN_PAGES (STAGE2_PGTABLE_LEVELS - 1) +#define kvm_mmu_cache_min_pages(kvm) (STAGE2_PGTABLE_LEVELS - 1) =20 =20 #if STAGE2_PGTABLE_LEVELS > 3 @@ -77,16 +77,17 @@ #define S2_PUD_SIZE (_AC(1, UL) << S2_PUD_SHIFT) #define S2_PUD_MASK (~(S2_PUD_SIZE - 1)) =20 -#define stage2_pgd_none(pgd) pgd_none(pgd) -#define stage2_pgd_clear(pgd) pgd_clear(pgd) -#define stage2_pgd_present(pgd) pgd_present(pgd) -#define stage2_pgd_populate(pgd, pud) pgd_populate(NULL, pgd, pud) -#define stage2_pud_offset(pgd, address) pud_offset(pgd, address) -#define stage2_pud_free(pud) pud_free(NULL, pud) +#define stage2_pgd_none(kvm, pgd) pgd_none(pgd) +#define stage2_pgd_clear(kvm, pgd) pgd_clear(pgd) +#define stage2_pgd_present(kvm, pgd) pgd_present(pgd) +#define stage2_pgd_populate(kvm, pgd, pud) pgd_populate(NULL, pgd, pud) +#define stage2_pud_offset(kvm, pgd, address) pud_offset(pgd, address) +#define stage2_pud_free(kvm, pud) pud_free(NULL, pud) =20 -#define stage2_pud_table_empty(pudp) kvm_page_empty(pudp) +#define stage2_pud_table_empty(kvm, pudp) kvm_page_empty(pudp) =20 -static inline phys_addr_t stage2_pud_addr_end(phys_addr_t addr, phys_addr_= t end) +static inline phys_addr_t +stage2_pud_addr_end(struct kvm *kvm, phys_addr_t addr, phys_addr_t end) { phys_addr_t boundary =3D (addr + S2_PUD_SIZE) & S2_PUD_MASK; =20 @@ -102,17 +103,18 @@ static inline phys_addr_t stage2_pud_addr_end(phys_ad= dr_t addr, phys_addr_t end) #define S2_PMD_SIZE (_AC(1, UL) << S2_PMD_SHIFT) #define S2_PMD_MASK (~(S2_PMD_SIZE - 1)) =20 -#define stage2_pud_none(pud) pud_none(pud) -#define stage2_pud_clear(pud) pud_clear(pud) -#define stage2_pud_present(pud) pud_present(pud) -#define stage2_pud_populate(pud, pmd) pud_populate(NULL, pud, pmd) -#define stage2_pmd_offset(pud, address) pmd_offset(pud, address) -#define stage2_pmd_free(pmd) pmd_free(NULL, pmd) +#define stage2_pud_none(kvm, pud) pud_none(pud) +#define stage2_pud_clear(kvm, pud) pud_clear(pud) +#define stage2_pud_present(kvm, pud) pud_present(pud) +#define stage2_pud_populate(kvm, pud, pmd) pud_populate(NULL, pud, pmd) +#define stage2_pmd_offset(kvm, pud, address) pmd_offset(pud, address) +#define stage2_pmd_free(kvm, pmd) pmd_free(NULL, pmd) =20 -#define stage2_pud_huge(pud) pud_huge(pud) -#define stage2_pmd_table_empty(pmdp) kvm_page_empty(pmdp) +#define stage2_pud_huge(kvm, pud) pud_huge(pud) +#define stage2_pmd_table_empty(kvm, pmdp) kvm_page_empty(pmdp) =20 -static inline phys_addr_t stage2_pmd_addr_end(phys_addr_t addr, phys_addr_= t end) +static inline phys_addr_t +stage2_pmd_addr_end(struct kvm *kvm, phys_addr_t addr, phys_addr_t end) { phys_addr_t boundary =3D (addr + S2_PMD_SIZE) & S2_PMD_MASK; =20 @@ -121,7 +123,7 @@ static inline phys_addr_t stage2_pmd_addr_end(phys_addr= _t addr, phys_addr_t end) =20 #endif /* STAGE2_PGTABLE_LEVELS > 2 */ =20 -#define stage2_pte_table_empty(ptep) kvm_page_empty(ptep) +#define stage2_pte_table_empty(kvm, ptep) kvm_page_empty(ptep) =20 #if STAGE2_PGTABLE_LEVELS =3D=3D 2 #include @@ -129,10 +131,13 @@ static inline phys_addr_t stage2_pmd_addr_end(phys_ad= dr_t addr, phys_addr_t end) #include #endif =20 +#define stage2_pgd_size(kvm) (PTRS_PER_S2_PGD * sizeof(pgd_t)) =20 -#define stage2_pgd_index(addr) (((addr) >> S2_PGDIR_SHIFT) & (PTRS_PER_= S2_PGD - 1)) +#define stage2_pgd_index(kvm, addr) \ + (((addr) >> S2_PGDIR_SHIFT) & (PTRS_PER_S2_PGD - 1)) =20 -static inline phys_addr_t stage2_pgd_addr_end(phys_addr_t addr, phys_addr_= t end) +static inline phys_addr_t +stage2_pgd_addr_end(struct kvm *kvm, phys_addr_t addr, phys_addr_t end) { phys_addr_t boundary =3D (addr + S2_PGDIR_SIZE) & S2_PGDIR_MASK; =20 diff --git a/virt/kvm/arm/arm.c b/virt/kvm/arm/arm.c index 04e554c..d2637bb 100644 --- a/virt/kvm/arm/arm.c +++ b/virt/kvm/arm/arm.c @@ -538,7 +538,7 @@ static void update_vttbr(struct kvm *kvm) =20 /* update vttbr to be used with the new vmid */ pgd_phys =3D virt_to_phys(kvm->arch.pgd); - BUG_ON(pgd_phys & ~VTTBR_BADDR_MASK); + BUG_ON(pgd_phys & ~kvm_vttbr_baddr_mask(kvm)); vmid =3D ((u64)(kvm->arch.vmid) << VTTBR_VMID_SHIFT) & VTTBR_VMID_MASK(kv= m_vmid_bits); kvm->arch.vttbr =3D kvm_phys_to_vttbr(pgd_phys) | vmid; =20 diff --git a/virt/kvm/arm/mmu.c b/virt/kvm/arm/mmu.c index 308171c..82dd571 100644 --- a/virt/kvm/arm/mmu.c +++ b/virt/kvm/arm/mmu.c @@ -45,7 +45,6 @@ static phys_addr_t hyp_idmap_vector; =20 static unsigned long io_map_base; =20 -#define S2_PGD_SIZE (PTRS_PER_S2_PGD * sizeof(pgd_t)) #define hyp_pgd_order get_order(PTRS_PER_PGD * sizeof(pgd_t)) =20 #define KVM_S2PTE_FLAG_IS_IOMAP (1UL << 0) @@ -150,20 +149,20 @@ static void *mmu_memory_cache_alloc(struct kvm_mmu_me= mory_cache *mc) =20 static void clear_stage2_pgd_entry(struct kvm *kvm, pgd_t *pgd, phys_addr_= t addr) { - pud_t *pud_table __maybe_unused =3D stage2_pud_offset(pgd, 0UL); - stage2_pgd_clear(pgd); + pud_t *pud_table __maybe_unused =3D stage2_pud_offset(kvm, pgd, 0UL); + stage2_pgd_clear(kvm, pgd); kvm_tlb_flush_vmid_ipa(kvm, addr); - stage2_pud_free(pud_table); + stage2_pud_free(kvm, pud_table); put_page(virt_to_page(pgd)); } =20 static void clear_stage2_pud_entry(struct kvm *kvm, pud_t *pud, phys_addr_= t addr) { - pmd_t *pmd_table __maybe_unused =3D stage2_pmd_offset(pud, 0); - VM_BUG_ON(stage2_pud_huge(*pud)); - stage2_pud_clear(pud); + pmd_t *pmd_table __maybe_unused =3D stage2_pmd_offset(kvm, pud, 0); + VM_BUG_ON(stage2_pud_huge(kvm, *pud)); + stage2_pud_clear(kvm, pud); kvm_tlb_flush_vmid_ipa(kvm, addr); - stage2_pmd_free(pmd_table); + stage2_pmd_free(kvm, pmd_table); put_page(virt_to_page(pud)); } =20 @@ -219,7 +218,7 @@ static void unmap_stage2_ptes(struct kvm *kvm, pmd_t *p= md, } } while (pte++, addr +=3D PAGE_SIZE, addr !=3D end); =20 - if (stage2_pte_table_empty(start_pte)) + if (stage2_pte_table_empty(kvm, start_pte)) clear_stage2_pmd_entry(kvm, pmd, start_addr); } =20 @@ -229,9 +228,9 @@ static void unmap_stage2_pmds(struct kvm *kvm, pud_t *p= ud, phys_addr_t next, start_addr =3D addr; pmd_t *pmd, *start_pmd; =20 - start_pmd =3D pmd =3D stage2_pmd_offset(pud, addr); + start_pmd =3D pmd =3D stage2_pmd_offset(kvm, pud, addr); do { - next =3D stage2_pmd_addr_end(addr, end); + next =3D stage2_pmd_addr_end(kvm, addr, end); if (!pmd_none(*pmd)) { if (pmd_thp_or_huge(*pmd)) { pmd_t old_pmd =3D *pmd; @@ -248,7 +247,7 @@ static void unmap_stage2_pmds(struct kvm *kvm, pud_t *p= ud, } } while (pmd++, addr =3D next, addr !=3D end); =20 - if (stage2_pmd_table_empty(start_pmd)) + if (stage2_pmd_table_empty(kvm, start_pmd)) clear_stage2_pud_entry(kvm, pud, start_addr); } =20 @@ -258,14 +257,14 @@ static void unmap_stage2_puds(struct kvm *kvm, pgd_t = *pgd, phys_addr_t next, start_addr =3D addr; pud_t *pud, *start_pud; =20 - start_pud =3D pud =3D stage2_pud_offset(pgd, addr); + start_pud =3D pud =3D stage2_pud_offset(kvm, pgd, addr); do { - next =3D stage2_pud_addr_end(addr, end); - if (!stage2_pud_none(*pud)) { - if (stage2_pud_huge(*pud)) { + next =3D stage2_pud_addr_end(kvm, addr, end); + if (!stage2_pud_none(kvm, *pud)) { + if (stage2_pud_huge(kvm, *pud)) { pud_t old_pud =3D *pud; =20 - stage2_pud_clear(pud); + stage2_pud_clear(kvm, pud); kvm_tlb_flush_vmid_ipa(kvm, addr); kvm_flush_dcache_pud(old_pud); put_page(virt_to_page(pud)); @@ -275,7 +274,7 @@ static void unmap_stage2_puds(struct kvm *kvm, pgd_t *p= gd, } } while (pud++, addr =3D next, addr !=3D end); =20 - if (stage2_pud_table_empty(start_pud)) + if (stage2_pud_table_empty(kvm, start_pud)) clear_stage2_pgd_entry(kvm, pgd, start_addr); } =20 @@ -299,7 +298,7 @@ static void unmap_stage2_range(struct kvm *kvm, phys_ad= dr_t start, u64 size) assert_spin_locked(&kvm->mmu_lock); WARN_ON(size & ~PAGE_MASK); =20 - pgd =3D kvm->arch.pgd + stage2_pgd_index(addr); + pgd =3D kvm->arch.pgd + stage2_pgd_index(kvm, addr); do { /* * Make sure the page table is still active, as another thread @@ -308,8 +307,8 @@ static void unmap_stage2_range(struct kvm *kvm, phys_ad= dr_t start, u64 size) */ if (!READ_ONCE(kvm->arch.pgd)) break; - next =3D stage2_pgd_addr_end(addr, end); - if (!stage2_pgd_none(*pgd)) + next =3D stage2_pgd_addr_end(kvm, addr, end); + if (!stage2_pgd_none(kvm, *pgd)) unmap_stage2_puds(kvm, pgd, addr, next); /* * If the range is too large, release the kvm->mmu_lock @@ -338,9 +337,9 @@ static void stage2_flush_pmds(struct kvm *kvm, pud_t *p= ud, pmd_t *pmd; phys_addr_t next; =20 - pmd =3D stage2_pmd_offset(pud, addr); + pmd =3D stage2_pmd_offset(kvm, pud, addr); do { - next =3D stage2_pmd_addr_end(addr, end); + next =3D stage2_pmd_addr_end(kvm, addr, end); if (!pmd_none(*pmd)) { if (pmd_thp_or_huge(*pmd)) kvm_flush_dcache_pmd(*pmd); @@ -356,11 +355,11 @@ static void stage2_flush_puds(struct kvm *kvm, pgd_t = *pgd, pud_t *pud; phys_addr_t next; =20 - pud =3D stage2_pud_offset(pgd, addr); + pud =3D stage2_pud_offset(kvm, pgd, addr); do { - next =3D stage2_pud_addr_end(addr, end); - if (!stage2_pud_none(*pud)) { - if (stage2_pud_huge(*pud)) + next =3D stage2_pud_addr_end(kvm, addr, end); + if (!stage2_pud_none(kvm, *pud)) { + if (stage2_pud_huge(kvm, *pud)) kvm_flush_dcache_pud(*pud); else stage2_flush_pmds(kvm, pud, addr, next); @@ -376,10 +375,10 @@ static void stage2_flush_memslot(struct kvm *kvm, phys_addr_t next; pgd_t *pgd; =20 - pgd =3D kvm->arch.pgd + stage2_pgd_index(addr); + pgd =3D kvm->arch.pgd + stage2_pgd_index(kvm, addr); do { - next =3D stage2_pgd_addr_end(addr, end); - if (!stage2_pgd_none(*pgd)) + next =3D stage2_pgd_addr_end(kvm, addr, end); + if (!stage2_pgd_none(kvm, *pgd)) stage2_flush_puds(kvm, pgd, addr, next); } while (pgd++, addr =3D next, addr !=3D end); } @@ -869,7 +868,7 @@ int kvm_alloc_stage2_pgd(struct kvm *kvm) } =20 /* Allocate the HW PGD, making sure that each page gets its own refcount = */ - pgd =3D alloc_pages_exact(S2_PGD_SIZE, GFP_KERNEL | __GFP_ZERO); + pgd =3D alloc_pages_exact(stage2_pgd_size(kvm), GFP_KERNEL | __GFP_ZERO); if (!pgd) return -ENOMEM; =20 @@ -958,7 +957,7 @@ void kvm_free_stage2_pgd(struct kvm *kvm) =20 spin_lock(&kvm->mmu_lock); if (kvm->arch.pgd) { - unmap_stage2_range(kvm, 0, KVM_PHYS_SIZE); + unmap_stage2_range(kvm, 0, kvm_phys_size(kvm)); pgd =3D READ_ONCE(kvm->arch.pgd); kvm->arch.pgd =3D NULL; } @@ -966,7 +965,7 @@ void kvm_free_stage2_pgd(struct kvm *kvm) =20 /* Free the HW pgd, one page at a time */ if (pgd) - free_pages_exact(pgd, S2_PGD_SIZE); + free_pages_exact(pgd, stage2_pgd_size(kvm)); } =20 static pud_t *stage2_get_pud(struct kvm *kvm, struct kvm_mmu_memory_cache = *cache, @@ -975,16 +974,16 @@ static pud_t *stage2_get_pud(struct kvm *kvm, struct = kvm_mmu_memory_cache *cache pgd_t *pgd; pud_t *pud; =20 - pgd =3D kvm->arch.pgd + stage2_pgd_index(addr); - if (stage2_pgd_none(*pgd)) { + pgd =3D kvm->arch.pgd + stage2_pgd_index(kvm, addr); + if (stage2_pgd_none(kvm, *pgd)) { if (!cache) return NULL; pud =3D mmu_memory_cache_alloc(cache); - stage2_pgd_populate(pgd, pud); + stage2_pgd_populate(kvm, pgd, pud); get_page(virt_to_page(pgd)); } =20 - return stage2_pud_offset(pgd, addr); + return stage2_pud_offset(kvm, pgd, addr); } =20 static pmd_t *stage2_get_pmd(struct kvm *kvm, struct kvm_mmu_memory_cache = *cache, @@ -997,15 +996,15 @@ static pmd_t *stage2_get_pmd(struct kvm *kvm, struct = kvm_mmu_memory_cache *cache if (!pud) return NULL; =20 - if (stage2_pud_none(*pud)) { + if (stage2_pud_none(kvm, *pud)) { if (!cache) return NULL; pmd =3D mmu_memory_cache_alloc(cache); - stage2_pud_populate(pud, pmd); + stage2_pud_populate(kvm, pud, pmd); get_page(virt_to_page(pud)); } =20 - return stage2_pmd_offset(pud, addr); + return stage2_pmd_offset(kvm, pud, addr); } =20 static int stage2_set_pmd_huge(struct kvm *kvm, struct kvm_mmu_memory_cache @@ -1159,8 +1158,9 @@ int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_= t guest_ipa, if (writable) pte =3D kvm_s2pte_mkwrite(pte); =20 - ret =3D mmu_topup_memory_cache(&cache, KVM_MMU_CACHE_MIN_PAGES, - KVM_NR_MEM_OBJS); + ret =3D mmu_topup_memory_cache(&cache, + kvm_mmu_cache_min_pages(kvm), + KVM_NR_MEM_OBJS); if (ret) goto out; spin_lock(&kvm->mmu_lock); @@ -1248,19 +1248,21 @@ static void stage2_wp_ptes(pmd_t *pmd, phys_addr_t = addr, phys_addr_t end) =20 /** * stage2_wp_pmds - write protect PUD range + * kvm: kvm instance for the VM * @pud: pointer to pud entry * @addr: range start address * @end: range end address */ -static void stage2_wp_pmds(pud_t *pud, phys_addr_t addr, phys_addr_t end) +static void stage2_wp_pmds(struct kvm *kvm, pud_t *pud, + phys_addr_t addr, phys_addr_t end) { pmd_t *pmd; phys_addr_t next; =20 - pmd =3D stage2_pmd_offset(pud, addr); + pmd =3D stage2_pmd_offset(kvm, pud, addr); =20 do { - next =3D stage2_pmd_addr_end(addr, end); + next =3D stage2_pmd_addr_end(kvm, addr, end); if (!pmd_none(*pmd)) { if (pmd_thp_or_huge(*pmd)) { if (!kvm_s2pmd_readonly(pmd)) @@ -1280,18 +1282,19 @@ static void stage2_wp_pmds(pud_t *pud, phys_addr_t = addr, phys_addr_t end) * * Process PUD entries, for a huge PUD we cause a panic. */ -static void stage2_wp_puds(pgd_t *pgd, phys_addr_t addr, phys_addr_t end) +static void stage2_wp_puds(struct kvm *kvm, pgd_t *pgd, + phys_addr_t addr, phys_addr_t end) { pud_t *pud; phys_addr_t next; =20 - pud =3D stage2_pud_offset(pgd, addr); + pud =3D stage2_pud_offset(kvm, pgd, addr); do { - next =3D stage2_pud_addr_end(addr, end); - if (!stage2_pud_none(*pud)) { + next =3D stage2_pud_addr_end(kvm, addr, end); + if (!stage2_pud_none(kvm, *pud)) { /* TODO:PUD not supported, revisit later if supported */ - BUG_ON(stage2_pud_huge(*pud)); - stage2_wp_pmds(pud, addr, next); + BUG_ON(stage2_pud_huge(kvm, *pud)); + stage2_wp_pmds(kvm, pud, addr, next); } } while (pud++, addr =3D next, addr !=3D end); } @@ -1307,7 +1310,7 @@ static void stage2_wp_range(struct kvm *kvm, phys_add= r_t addr, phys_addr_t end) pgd_t *pgd; phys_addr_t next; =20 - pgd =3D kvm->arch.pgd + stage2_pgd_index(addr); + pgd =3D kvm->arch.pgd + stage2_pgd_index(kvm, addr); do { /* * Release kvm_mmu_lock periodically if the memory region is @@ -1321,9 +1324,9 @@ static void stage2_wp_range(struct kvm *kvm, phys_add= r_t addr, phys_addr_t end) cond_resched_lock(&kvm->mmu_lock); if (!READ_ONCE(kvm->arch.pgd)) break; - next =3D stage2_pgd_addr_end(addr, end); - if (stage2_pgd_present(*pgd)) - stage2_wp_puds(pgd, addr, next); + next =3D stage2_pgd_addr_end(kvm, addr, end); + if (stage2_pgd_present(kvm, *pgd)) + stage2_wp_puds(kvm, pgd, addr, next); } while (pgd++, addr =3D next, addr !=3D end); } =20 @@ -1472,7 +1475,7 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys= _addr_t fault_ipa, up_read(¤t->mm->mmap_sem); =20 /* We need minimum second+third level pages */ - ret =3D mmu_topup_memory_cache(memcache, KVM_MMU_CACHE_MIN_PAGES, + ret =3D mmu_topup_memory_cache(memcache, kvm_mmu_cache_min_pages(kvm), KVM_NR_MEM_OBJS); if (ret) return ret; @@ -1715,7 +1718,7 @@ int kvm_handle_guest_abort(struct kvm_vcpu *vcpu, str= uct kvm_run *run) } =20 /* Userspace should not be able to register out-of-bounds IPAs */ - VM_BUG_ON(fault_ipa >=3D KVM_PHYS_SIZE); + VM_BUG_ON(fault_ipa >=3D kvm_phys_size(vcpu->kvm)); =20 if (fault_status =3D=3D FSC_ACCESS) { handle_access_fault(vcpu, fault_ipa); @@ -2019,7 +2022,7 @@ int kvm_arch_prepare_memory_region(struct kvm *kvm, * space addressable by the KVM guest IPA space. */ if (memslot->base_gfn + memslot->npages >=3D - (KVM_PHYS_SIZE >> PAGE_SHIFT)) + (kvm_phys_size(kvm) >> PAGE_SHIFT)) return -EFAULT; =20 down_read(¤t->mm->mmap_sem); diff --git a/virt/kvm/arm/vgic/vgic-kvm-device.c b/virt/kvm/arm/vgic/vgic-k= vm-device.c index 6ada243..114dce9 100644 --- a/virt/kvm/arm/vgic/vgic-kvm-device.c +++ b/virt/kvm/arm/vgic/vgic-kvm-device.c @@ -25,7 +25,7 @@ int vgic_check_ioaddr(struct kvm *kvm, phys_addr_t *ioaddr, phys_addr_t addr, phys_addr_t alignment) { - if (addr & ~KVM_PHYS_MASK) + if (addr & ~kvm_phys_mask(kvm)) return -E2BIG; =20 if (!IS_ALIGNED(addr, alignment)) --=20 2.7.4 From nobody Mon Feb 9 15:13:28 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530271667883890.101343056525; Fri, 29 Jun 2018 04:27:47 -0700 (PDT) Received: from localhost ([::1]:41261 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYrZ2-0000Yk-Lg for importer@patchew.org; Fri, 29 Jun 2018 07:27:44 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36484) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYrOG-0008Sh-Lz for qemu-devel@nongnu.org; Fri, 29 Jun 2018 07:16:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fYrOF-0002Ma-R3 for qemu-devel@nongnu.org; Fri, 29 Jun 2018 07:16:36 -0400 Received: from foss.arm.com ([217.140.101.70]:39338) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYrOF-0002M7-Je for qemu-devel@nongnu.org; Fri, 29 Jun 2018 07:16:35 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 12E5A1682; Fri, 29 Jun 2018 04:16:35 -0700 (PDT) Received: from en101.cambridge.arm.com (en101.cambridge.arm.com [10.1.206.73]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id B01643F5AF; Fri, 29 Jun 2018 04:16:32 -0700 (PDT) From: Suzuki K Poulose To: linux-arm-kernel@lists.infradead.org Date: Fri, 29 Jun 2018 12:15:28 +0100 Message-Id: <1530270944-11351-9-git-send-email-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1530270944-11351-1-git-send-email-suzuki.poulose@arm.com> References: <1530270944-11351-1-git-send-email-suzuki.poulose@arm.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 217.140.101.70 Subject: [Qemu-devel] [PATCH v3 08/20] kvm: arm/arm64: Abstract stage2 pgd table allocation X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cdall@kernel.org, kvm@vger.kernel.org, Suzuki K Poulose , marc.zyngier@arm.com, catalin.marinas@arm.com, punit.agrawal@arm.com, will.deacon@arm.com, linux-kernel@vger.kernel.org, qemu-devel@nongnu.org, eric.auger@redhat.com, julien.grall@arm.com, james.morse@arm.com, kvmarm@lists.cs.columbia.edu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Abstract the allocation of stage2 entry level tables for given VM, so that later we can choose to fall back to the normal page table levels (i.e, avoid entry level table concatenation) on arm64. Cc: Marc Zyngier Cc: Christoffer Dall Signed-off-by: Suzuki K Poulose Reviewed-by: Eric Auger --- Changes since V2: - New patch --- arch/arm/include/asm/kvm_mmu.h | 6 ++++++ arch/arm64/include/asm/kvm_mmu.h | 6 ++++++ virt/kvm/arm/mmu.c | 2 +- 3 files changed, 13 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/kvm_mmu.h b/arch/arm/include/asm/kvm_mmu.h index f36eb20..b2da5a4 100644 --- a/arch/arm/include/asm/kvm_mmu.h +++ b/arch/arm/include/asm/kvm_mmu.h @@ -372,6 +372,12 @@ static inline int hyp_map_aux_data(void) return 0; } =20 +static inline void *stage2_alloc_pgd(struct kvm *kvm) +{ + return alloc_pages_exact(stage2_pgd_size(kvm), + GFP_KERNEL | __GFP_ZERO); +} + #define kvm_phys_to_vttbr(addr) (addr) =20 #endif /* !__ASSEMBLY__ */ diff --git a/arch/arm64/include/asm/kvm_mmu.h b/arch/arm64/include/asm/kvm_= mmu.h index 5da8f52..dbaf513 100644 --- a/arch/arm64/include/asm/kvm_mmu.h +++ b/arch/arm64/include/asm/kvm_mmu.h @@ -501,5 +501,11 @@ static inline int hyp_map_aux_data(void) =20 #define kvm_phys_to_vttbr(addr) phys_to_ttbr(addr) =20 +static inline void *stage2_alloc_pgd(struct kvm *kvm) +{ + return alloc_pages_exact(stage2_pgd_size(kvm), + GFP_KERNEL | __GFP_ZERO); +} + #endif /* __ASSEMBLY__ */ #endif /* __ARM64_KVM_MMU_H__ */ diff --git a/virt/kvm/arm/mmu.c b/virt/kvm/arm/mmu.c index 82dd571..a339e00 100644 --- a/virt/kvm/arm/mmu.c +++ b/virt/kvm/arm/mmu.c @@ -868,7 +868,7 @@ int kvm_alloc_stage2_pgd(struct kvm *kvm) } =20 /* Allocate the HW PGD, making sure that each page gets its own refcount = */ - pgd =3D alloc_pages_exact(stage2_pgd_size(kvm), GFP_KERNEL | __GFP_ZERO); + pgd =3D stage2_alloc_pgd(kvm); if (!pgd) return -ENOMEM; =20 --=20 2.7.4 From nobody Mon Feb 9 15:13:28 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530271483002158.71635450110853; Fri, 29 Jun 2018 04:24:43 -0700 (PDT) Received: from localhost ([::1]:41241 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYrW6-00060T-47 for importer@patchew.org; Fri, 29 Jun 2018 07:24:42 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36529) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYrON-0008WP-9b for qemu-devel@nongnu.org; Fri, 29 Jun 2018 07:16:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fYrOI-0002OZ-J3 for qemu-devel@nongnu.org; Fri, 29 Jun 2018 07:16:43 -0400 Received: from foss.arm.com ([217.140.101.70]:39356) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYrOI-0002Nn-A9 for qemu-devel@nongnu.org; Fri, 29 Jun 2018 07:16:38 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A7BB9168F; Fri, 29 Jun 2018 04:16:37 -0700 (PDT) Received: from en101.cambridge.arm.com (en101.cambridge.arm.com [10.1.206.73]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 50C303F266; Fri, 29 Jun 2018 04:16:35 -0700 (PDT) From: Suzuki K Poulose To: linux-arm-kernel@lists.infradead.org Date: Fri, 29 Jun 2018 12:15:29 +0100 Message-Id: <1530270944-11351-10-git-send-email-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1530270944-11351-1-git-send-email-suzuki.poulose@arm.com> References: <1530270944-11351-1-git-send-email-suzuki.poulose@arm.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 217.140.101.70 Subject: [Qemu-devel] [PATCH v3 09/20] kvm: arm64: Make stage2 page table layout dynamic X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cdall@kernel.org, kvm@vger.kernel.org, Suzuki K Poulose , marc.zyngier@arm.com, catalin.marinas@arm.com, punit.agrawal@arm.com, will.deacon@arm.com, linux-kernel@vger.kernel.org, qemu-devel@nongnu.org, eric.auger@redhat.com, julien.grall@arm.com, james.morse@arm.com, kvmarm@lists.cs.columbia.edu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" So far we had a static stage2 page table handling code, based on a fixed IPA of 40bits. As we prepare for a configurable IPA size per VM, make our stage2 page table code dynamic, to do the right thing for a given VM. We ensure the existing condition is always true even when we lift the limit on the IPA. i.e, page table levels in stage1 >=3D page table levels in stage2 Support for the IPA size configuration needs other changes in the way we configure the EL2 registers (VTTBR and VTCR). So, the IPA is still fixed to 40bits. The patch also moves the kvm_page_empty() in asm/kvm_mmu.h to the top, before including the asm/stage2_pgtable.h to avoid a forward declaration. Cc: Marc Zyngier Cc: Christoffer Dall Signed-off-by: Suzuki K Poulose --- Changes since V2 - Restrict the stage2 page table to allow reusing the host page table helpers for now, until we get stage1 independent page table helpers. --- arch/arm64/include/asm/kvm_mmu.h | 14 +- arch/arm64/include/asm/stage2_pgtable-nopmd.h | 42 ------ arch/arm64/include/asm/stage2_pgtable-nopud.h | 39 ----- arch/arm64/include/asm/stage2_pgtable.h | 207 +++++++++++++++++++---= ---- 4 files changed, 159 insertions(+), 143 deletions(-) delete mode 100644 arch/arm64/include/asm/stage2_pgtable-nopmd.h delete mode 100644 arch/arm64/include/asm/stage2_pgtable-nopud.h diff --git a/arch/arm64/include/asm/kvm_mmu.h b/arch/arm64/include/asm/kvm_= mmu.h index dbaf513..a351722 100644 --- a/arch/arm64/include/asm/kvm_mmu.h +++ b/arch/arm64/include/asm/kvm_mmu.h @@ -21,6 +21,7 @@ #include #include #include +#include =20 /* * As ARMv8.0 only has the TTBR0_EL2 register, we cannot express @@ -147,6 +148,13 @@ static inline unsigned long __kern_hyp_va(unsigned lon= g v) #define kvm_phys_mask(kvm) (kvm_phys_size(kvm) - _AC(1, ULL)) #define kvm_vttbr_baddr_mask(kvm) VTTBR_BADDR_MASK =20 +static inline bool kvm_page_empty(void *ptr) +{ + struct page *ptr_page =3D virt_to_page(ptr); + + return page_count(ptr_page) =3D=3D 1; +} + #include =20 int create_hyp_mappings(void *from, void *to, pgprot_t prot); @@ -237,12 +245,6 @@ static inline bool kvm_s2pmd_exec(pmd_t *pmdp) return !(READ_ONCE(pmd_val(*pmdp)) & PMD_S2_XN); } =20 -static inline bool kvm_page_empty(void *ptr) -{ - struct page *ptr_page =3D virt_to_page(ptr); - return page_count(ptr_page) =3D=3D 1; -} - #define hyp_pte_table_empty(ptep) kvm_page_empty(ptep) =20 #ifdef __PAGETABLE_PMD_FOLDED diff --git a/arch/arm64/include/asm/stage2_pgtable-nopmd.h b/arch/arm64/inc= lude/asm/stage2_pgtable-nopmd.h deleted file mode 100644 index 0280ded..0000000 --- a/arch/arm64/include/asm/stage2_pgtable-nopmd.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (C) 2016 - ARM Ltd - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef __ARM64_S2_PGTABLE_NOPMD_H_ -#define __ARM64_S2_PGTABLE_NOPMD_H_ - -#include - -#define __S2_PGTABLE_PMD_FOLDED - -#define S2_PMD_SHIFT S2_PUD_SHIFT -#define S2_PTRS_PER_PMD 1 -#define S2_PMD_SIZE (1UL << S2_PMD_SHIFT) -#define S2_PMD_MASK (~(S2_PMD_SIZE-1)) - -#define stage2_pud_none(kvm, pud) (0) -#define stage2_pud_present(kvm, pud) (1) -#define stage2_pud_clear(kvm, pud) do { } while (0) -#define stage2_pud_populate(kvm, pud, pmd) do { } while (0) -#define stage2_pmd_offset(kvm, pud, address) ((pmd_t *)(pud)) - -#define stage2_pmd_free(kvm, pmd) do { } while (0) - -#define stage2_pmd_addr_end(kvm, addr, end) (end) - -#define stage2_pud_huge(kvm, pud) (0) -#define stage2_pmd_table_empty(kvm, pmdp) (0) - -#endif diff --git a/arch/arm64/include/asm/stage2_pgtable-nopud.h b/arch/arm64/inc= lude/asm/stage2_pgtable-nopud.h deleted file mode 100644 index cd6304e..0000000 --- a/arch/arm64/include/asm/stage2_pgtable-nopud.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (C) 2016 - ARM Ltd - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef __ARM64_S2_PGTABLE_NOPUD_H_ -#define __ARM64_S2_PGTABLE_NOPUD_H_ - -#define __S2_PGTABLE_PUD_FOLDED - -#define S2_PUD_SHIFT S2_PGDIR_SHIFT -#define S2_PTRS_PER_PUD 1 -#define S2_PUD_SIZE (_AC(1, UL) << S2_PUD_SHIFT) -#define S2_PUD_MASK (~(S2_PUD_SIZE-1)) - -#define stage2_pgd_none(kvm, pgd) (0) -#define stage2_pgd_present(kvm, pgd) (1) -#define stage2_pgd_clear(kvm, pgd) do { } while (0) -#define stage2_pgd_populate(kvm, pgd, pud) do { } while (0) - -#define stage2_pud_offset(kvm, pgd, address) ((pud_t *)(pgd)) - -#define stage2_pud_free(kvm, x) do { } while (0) - -#define stage2_pud_addr_end(kvm, addr, end) (end) -#define stage2_pud_table_empty(kvm, pmdp) (0) - -#endif diff --git a/arch/arm64/include/asm/stage2_pgtable.h b/arch/arm64/include/a= sm/stage2_pgtable.h index 057a405..ffc37cc 100644 --- a/arch/arm64/include/asm/stage2_pgtable.h +++ b/arch/arm64/include/asm/stage2_pgtable.h @@ -19,8 +19,12 @@ #ifndef __ARM64_S2_PGTABLE_H_ #define __ARM64_S2_PGTABLE_H_ =20 +#include #include =20 +/* The PGDIR shift for a given page table with "n" levels. */ +#define pt_levels_pgdir_shift(n) ARM64_HW_PGTABLE_LEVEL_SHIFT(4 - (n)) + /* * The hardware supports concatenation of up to 16 tables at stage2 entry = level * and we use the feature whenever possible. @@ -29,118 +33,209 @@ * On arm64, the smallest PAGE_SIZE supported is 4k, which means * (PAGE_SHIFT - 3) > 4 holds for all page sizes. * This implies, the total number of page table levels at stage2 expected - * by the hardware is actually the number of levels required for (KVM_PHYS= _SHIFT - 4) + * by the hardware is actually the number of levels required for (IPA_SHIF= T - 4) * in normal translations(e.g, stage1), since we cannot have another level= in - * the range (KVM_PHYS_SHIFT, KVM_PHYS_SHIFT - 4). + * the range (IPA_SHIFT, IPA_SHIFT - 4). */ -#define STAGE2_PGTABLE_LEVELS ARM64_HW_PGTABLE_LEVELS(KVM_PHYS_SHIFT - 4) +#define stage2_pt_levels(ipa_shift) ARM64_HW_PGTABLE_LEVELS((ipa_shift) - = 4) =20 /* - * With all the supported VA_BITs and 40bit guest IPA, the following condi= tion - * is always true: + * With all the supported VA_BITs and guest IPA, the following condition + * must be always true: * - * STAGE2_PGTABLE_LEVELS <=3D CONFIG_PGTABLE_LEVELS + * stage2_pt_levels <=3D CONFIG_PGTABLE_LEVELS * * We base our stage-2 page table walker helpers on this assumption and * fall back to using the host version of the helper wherever possible. * i.e, if a particular level is not folded (e.g, PUD) at stage2, we fall = back * to using the host version, since it is guaranteed it is not folded at h= ost. * - * If the condition breaks in the future, we can rearrange the host level - * definitions and reuse them for stage2. Till then... + * If the condition breaks in the future, we need completely independent + * page table helpers. Till then... */ -#if STAGE2_PGTABLE_LEVELS > CONFIG_PGTABLE_LEVELS + +#if stage2_pt_levels(KVM_PHYS_SHIFT) > CONFIG_PGTABLE_LEVELS #error "Unsupported combination of guest IPA and host VA_BITS." #endif =20 -/* S2_PGDIR_SHIFT is the size mapped by top-level stage2 entry */ -#define S2_PGDIR_SHIFT ARM64_HW_PGTABLE_LEVEL_SHIFT(4 - STAGE2_PGTABLE_L= EVELS) -#define S2_PGDIR_SIZE (_AC(1, UL) << S2_PGDIR_SHIFT) -#define S2_PGDIR_MASK (~(S2_PGDIR_SIZE - 1)) - /* * The number of PTRS across all concatenated stage2 tables given by the * number of bits resolved at the initial level. */ -#define PTRS_PER_S2_PGD (1 << (KVM_PHYS_SHIFT - S2_PGDIR_SHIFT)) +#define __s2_pgd_ptrs(pa, lvls) (1 << ((pa) - pt_levels_pgdir_shift((lvls)= ))) +#define __s2_pgd_size(pa, lvls) (__s2_pgd_ptrs((pa), (lvls)) * sizeof(pgd_= t)) + +#define kvm_stage2_levels(kvm) stage2_pt_levels(kvm_phys_shift(kvm)) +#define stage2_pgdir_shift(kvm) \ + pt_levels_pgdir_shift(kvm_stage2_levels(kvm)) +#define stage2_pgdir_size(kvm) (_AC(1, UL) << stage2_pgdir_shift((kvm))) +#define stage2_pgdir_mask(kvm) (~(stage2_pgdir_size((kvm)) - 1)) +#define stage2_pgd_ptrs(kvm) \ + __s2_pgd_ptrs(kvm_phys_shift(kvm), kvm_stage2_levels(kvm)) + +#define stage2_pgd_size(kvm) __s2_pgd_size(kvm_phys_shift(kvm), kvm_stage2= _levels(kvm)) =20 /* * kvm_mmmu_cache_min_pages is the number of stage2 page table translation * levels in addition to the PGD. */ -#define kvm_mmu_cache_min_pages(kvm) (STAGE2_PGTABLE_LEVELS - 1) +#define kvm_mmu_cache_min_pages(kvm) (kvm_stage2_levels(kvm) - 1) =20 =20 -#if STAGE2_PGTABLE_LEVELS > 3 +/* PUD/PMD definitions if present */ +#define __S2_PUD_SHIFT ARM64_HW_PGTABLE_LEVEL_SHIFT(1) +#define __S2_PUD_SIZE (_AC(1, UL) << __S2_PUD_SHIFT) +#define __S2_PUD_MASK (~(__S2_PUD_SIZE - 1)) =20 -#define S2_PUD_SHIFT ARM64_HW_PGTABLE_LEVEL_SHIFT(1) -#define S2_PUD_SIZE (_AC(1, UL) << S2_PUD_SHIFT) -#define S2_PUD_MASK (~(S2_PUD_SIZE - 1)) +#define __S2_PMD_SHIFT ARM64_HW_PGTABLE_LEVEL_SHIFT(2) +#define __S2_PMD_SIZE (_AC(1, UL) << __S2_PMD_SHIFT) +#define __S2_PMD_MASK (~(__S2_PMD_SIZE - 1)) =20 -#define stage2_pgd_none(kvm, pgd) pgd_none(pgd) -#define stage2_pgd_clear(kvm, pgd) pgd_clear(pgd) -#define stage2_pgd_present(kvm, pgd) pgd_present(pgd) -#define stage2_pgd_populate(kvm, pgd, pud) pgd_populate(NULL, pgd, pud) -#define stage2_pud_offset(kvm, pgd, address) pud_offset(pgd, address) -#define stage2_pud_free(kvm, pud) pud_free(NULL, pud) +#define __s2_pud_index(addr) \ + (((addr) >> __S2_PUD_SHIFT) & (PTRS_PER_PTE - 1)) +#define __s2_pmd_index(addr) \ + (((addr) >> __S2_PMD_SHIFT) & (PTRS_PER_PTE - 1)) =20 -#define stage2_pud_table_empty(kvm, pudp) kvm_page_empty(pudp) +#define __kvm_has_stage2_levels(kvm, min_levels) \ + ((CONFIG_PGTABLE_LEVELS >=3D min_levels) && (kvm_stage2_levels(kvm) >=3D= min_levels)) + +#define kvm_stage2_has_pgd(kvm) __kvm_has_stage2_levels(kvm, 4) +#define kvm_stage2_has_pud(kvm) __kvm_has_stage2_levels(kvm, 3) + +static inline int stage2_pgd_none(struct kvm *kvm, pgd_t pgd) +{ + return kvm_stage2_has_pgd(kvm) ? pgd_none(pgd) : 0; +} + +static inline void stage2_pgd_clear(struct kvm *kvm, pgd_t *pgdp) +{ + if (kvm_stage2_has_pgd(kvm)) + pgd_clear(pgdp); +} + +static inline int stage2_pgd_present(struct kvm *kvm, pgd_t pgd) +{ + return kvm_stage2_has_pgd(kvm) ? pgd_present(pgd) : 1; +} + +static inline void stage2_pgd_populate(struct kvm *kvm, pgd_t *pgdp, pud_t= *pud) +{ + if (kvm_stage2_has_pgd(kvm)) + pgd_populate(NULL, pgdp, pud); + else + BUG(); +} + +static inline pud_t *stage2_pud_offset(struct kvm *kvm, + pgd_t *pgd, unsigned long address) +{ + if (kvm_stage2_has_pgd(kvm)) { + phys_addr_t pud_phys =3D pgd_page_paddr(*pgd); + + pud_phys +=3D __s2_pud_index(address) * sizeof(pud_t); + return __va(pud_phys); + } + return (pud_t *)pgd; +} + +static inline void stage2_pud_free(struct kvm *kvm, pud_t *pud) +{ + if (kvm_stage2_has_pgd(kvm)) + pud_free(NULL, pud); +} + +static inline int stage2_pud_table_empty(struct kvm *kvm, pud_t *pudp) +{ + return kvm_stage2_has_pgd(kvm) && kvm_page_empty(pudp); +} =20 static inline phys_addr_t stage2_pud_addr_end(struct kvm *kvm, phys_addr_t addr, phys_addr_t end) { - phys_addr_t boundary =3D (addr + S2_PUD_SIZE) & S2_PUD_MASK; + if (kvm_stage2_has_pgd(kvm)) { + phys_addr_t boundary =3D (addr + __S2_PUD_SIZE) & __S2_PUD_MASK; =20 - return (boundary - 1 < end - 1) ? boundary : end; + return (boundary - 1 < end - 1) ? boundary : end; + } + return end; } =20 -#endif /* STAGE2_PGTABLE_LEVELS > 3 */ +static inline int stage2_pud_none(struct kvm *kvm, pud_t pud) +{ + return kvm_stage2_has_pud(kvm) ? pud_none(pud) : 0; +} =20 +static inline void stage2_pud_clear(struct kvm *kvm, pud_t *pudp) +{ + if (kvm_stage2_has_pud(kvm)) + pud_clear(pudp); +} =20 -#if STAGE2_PGTABLE_LEVELS > 2 +static inline int stage2_pud_present(struct kvm *kvm, pud_t pud) +{ + return kvm_stage2_has_pud(kvm) ? pud_present(pud) : 1; +} =20 -#define S2_PMD_SHIFT ARM64_HW_PGTABLE_LEVEL_SHIFT(2) -#define S2_PMD_SIZE (_AC(1, UL) << S2_PMD_SHIFT) -#define S2_PMD_MASK (~(S2_PMD_SIZE - 1)) +static inline void stage2_pud_populate(struct kvm *kvm, pud_t *pudp, pmd_t= *pmd) +{ + if (kvm_stage2_has_pud(kvm)) + pud_populate(NULL, pudp, pmd); + else + BUG(); +} =20 -#define stage2_pud_none(kvm, pud) pud_none(pud) -#define stage2_pud_clear(kvm, pud) pud_clear(pud) -#define stage2_pud_present(kvm, pud) pud_present(pud) -#define stage2_pud_populate(kvm, pud, pmd) pud_populate(NULL, pud, pmd) -#define stage2_pmd_offset(kvm, pud, address) pmd_offset(pud, address) -#define stage2_pmd_free(kvm, pmd) pmd_free(NULL, pmd) +static inline pmd_t *stage2_pmd_offset(struct kvm *kvm, + pud_t *pud, unsigned long address) +{ + if (kvm_stage2_has_pud(kvm)) { + phys_addr_t pmd_phys =3D pud_page_paddr(*pud); =20 -#define stage2_pud_huge(kvm, pud) pud_huge(pud) -#define stage2_pmd_table_empty(kvm, pmdp) kvm_page_empty(pmdp) + pmd_phys +=3D __s2_pmd_index(address) * sizeof(pmd_t); + return __va(pmd_phys); + } + return (pmd_t *)pud; +} + +static inline void stage2_pmd_free(struct kvm *kvm, pmd_t *pmd) +{ + if (kvm_stage2_has_pud(kvm)) + pmd_free(NULL, pmd); +} + +static inline int stage2_pmd_table_empty(struct kvm *kvm, pmd_t *pmdp) +{ + return kvm_stage2_has_pud(kvm) && kvm_page_empty(pmdp); +} =20 static inline phys_addr_t stage2_pmd_addr_end(struct kvm *kvm, phys_addr_t addr, phys_addr_t end) { - phys_addr_t boundary =3D (addr + S2_PMD_SIZE) & S2_PMD_MASK; + if (kvm_stage2_has_pud(kvm)) { + phys_addr_t boundary =3D (addr + __S2_PMD_SIZE) & __S2_PMD_MASK; =20 - return (boundary - 1 < end - 1) ? boundary : end; + return (boundary - 1 < end - 1) ? boundary : end; + } + return end; } =20 -#endif /* STAGE2_PGTABLE_LEVELS > 2 */ +static inline int stage2_pud_huge(struct kvm *kvm, pud_t pud) +{ + return kvm_stage2_has_pud(kvm) ? pud_huge(pud) : 0; +} =20 #define stage2_pte_table_empty(kvm, ptep) kvm_page_empty(ptep) =20 -#if STAGE2_PGTABLE_LEVELS =3D=3D 2 -#include -#elif STAGE2_PGTABLE_LEVELS =3D=3D 3 -#include -#endif - -#define stage2_pgd_size(kvm) (PTRS_PER_S2_PGD * sizeof(pgd_t)) - -#define stage2_pgd_index(kvm, addr) \ - (((addr) >> S2_PGDIR_SHIFT) & (PTRS_PER_S2_PGD - 1)) +static inline unsigned long stage2_pgd_index(struct kvm *kvm, phys_addr_t = addr) +{ + return (addr >> stage2_pgdir_shift(kvm)) & (stage2_pgd_ptrs(kvm) - 1); +} =20 static inline phys_addr_t stage2_pgd_addr_end(struct kvm *kvm, phys_addr_t addr, phys_addr_t end) { - phys_addr_t boundary =3D (addr + S2_PGDIR_SIZE) & S2_PGDIR_MASK; + phys_addr_t boundary; =20 + boundary =3D (addr + stage2_pgdir_size(kvm)) & stage2_pgdir_mask(kvm); return (boundary - 1 < end - 1) ? boundary : end; } =20 --=20 2.7.4 From nobody Mon Feb 9 15:13:28 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530271312128136.9989244195043; Fri, 29 Jun 2018 04:21:52 -0700 (PDT) Received: from localhost ([::1]:41229 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYrTL-0003l9-A6 for importer@patchew.org; Fri, 29 Jun 2018 07:21:51 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36531) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYrON-0008WQ-LV for qemu-devel@nongnu.org; Fri, 29 Jun 2018 07:16:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fYrOL-0002Rf-2A for qemu-devel@nongnu.org; Fri, 29 Jun 2018 07:16:43 -0400 Received: from foss.arm.com ([217.140.101.70]:39372) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYrOK-0002R6-Q1 for qemu-devel@nongnu.org; Fri, 29 Jun 2018 07:16:40 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4B95B15AD; Fri, 29 Jun 2018 04:16:40 -0700 (PDT) Received: from en101.cambridge.arm.com (en101.cambridge.arm.com [10.1.206.73]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id E84103F266; Fri, 29 Jun 2018 04:16:37 -0700 (PDT) From: Suzuki K Poulose To: linux-arm-kernel@lists.infradead.org Date: Fri, 29 Jun 2018 12:15:30 +0100 Message-Id: <1530270944-11351-11-git-send-email-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1530270944-11351-1-git-send-email-suzuki.poulose@arm.com> References: <1530270944-11351-1-git-send-email-suzuki.poulose@arm.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 217.140.101.70 Subject: [Qemu-devel] [PATCH v3 10/20] kvm: arm64: Dynamic configuration of VTTBR mask X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cdall@kernel.org, kvm@vger.kernel.org, Suzuki K Poulose , marc.zyngier@arm.com, catalin.marinas@arm.com, punit.agrawal@arm.com, will.deacon@arm.com, linux-kernel@vger.kernel.org, qemu-devel@nongnu.org, eric.auger@redhat.com, julien.grall@arm.com, james.morse@arm.com, kvmarm@lists.cs.columbia.edu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" On arm64 VTTBR_EL2:BADDR holds the base address for the stage2 translation table. The Arm ARM mandates that the bits BADDR[x-1:0] should be 0, where 'x' is defined for a given IPA Size and the number of levels for a translation granule size. It is defined using some magical constants. This patch is a reverse engineered implementation to calculate the 'x' at runtime for a given ipa and number of page table levels. See patch for more details. Cc: Marc Zyngier Cc: Christoffer Dall Signed-off-by: Suzuki K Poulose --- Changes since V2: - Part 1 of spilt from VTCR & VTTBR dynamic configuration --- arch/arm64/include/asm/kvm_arm.h | 60 ++++++++++++++++++++++++++++++++++++= +--- arch/arm64/include/asm/kvm_mmu.h | 25 ++++++++++++++++- 2 files changed, 80 insertions(+), 5 deletions(-) diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_= arm.h index 3dffd38..c557f45 100644 --- a/arch/arm64/include/asm/kvm_arm.h +++ b/arch/arm64/include/asm/kvm_arm.h @@ -140,8 +140,6 @@ * Note that when using 4K pages, we concatenate two first level page tabl= es * together. With 16K pages, we concatenate 16 first level page tables. * - * The magic numbers used for VTTBR_X in this patch can be found in Tables - * D4-23 and D4-25 in ARM DDI 0487A.b. */ =20 #define VTCR_EL2_T0SZ_IPA VTCR_EL2_T0SZ_40B @@ -175,9 +173,63 @@ #endif =20 #define VTCR_EL2_FLAGS (VTCR_EL2_COMMON_BITS | VTCR_EL2_TGRAN_FLAGS) -#define VTTBR_X (VTTBR_X_TGRAN_MAGIC - VTCR_EL2_T0SZ_IPA) +/* + * ARM VMSAv8-64 defines an algorithm for finding the translation table + * descriptors in section D4.2.8 in ARM DDI 0487B.b. + * + * The algorithm defines the expectations on the BaseAddress (for the page + * table) bits resolved at each level based on the page size, entry level + * and T0SZ. The variable "x" in the algorithm also affects the VTTBR:BADDR + * for stage2 page table. + * + * The value of "x" is calculated as : + * x =3D Magic_N - T0SZ + * + * where Magic_N is an integer depending on the page size and the entry + * level of the page table as below: + * + * -------------------------------------------- + * | Entry level | 4K 16K 64K | + * -------------------------------------------- + * | Level: 0 (4 levels) | 28 | - | - | + * -------------------------------------------- + * | Level: 1 (3 levels) | 37 | 31 | 25 | + * -------------------------------------------- + * | Level: 2 (2 levels) | 46 | 42 | 38 | + * -------------------------------------------- + * | Level: 3 (1 level) | - | 53 | 51 | + * -------------------------------------------- + * + * We have a magic formula for the Magic_N below. + * + * Magic_N(PAGE_SIZE, Entry_Level) =3D 64 - ((PAGE_SHIFT - 3) * Number of= levels) + * + * where number of levels =3D (4 - Entry_Level). + * + * So, given that T0SZ =3D (64 - PA_SHIFT), we can compute 'x' as follows: + * + * x =3D (64 - ((PAGE_SHIFT - 3) * Number_of_levels)) - (64 - PA_SHIFT) + * =3D PA_SHIFT - ((PAGE_SHIFT - 3) * Number of levels) + * + * Here is one way to explain the Magic Formula: + * + * x =3D log2(Size_of_Entry_Level_Table) + * + * Since, we can resolve (PAGE_SHIFT - 3) bits at each level, and another + * PAGE_SHIFT bits in the PTE, we have : + * + * Bits_Entry_level =3D PA_SHIFT - ((PAGE_SHIFT - 3) * (n - 1) + PAGE_SHI= FT) + * =3D PA_SHIFT - (PAGE_SHIFT - 3) * n - 3 + * where n =3D number of levels, and since each pointer is 8bytes, we hav= e: + * + * x =3D Bits_Entry_Level + 3 + * =3D PA_SHIFT - (PAGE_SHIFT - 3) * n + * + * The only constraint here is that, we have to find the number of page ta= ble + * levels for a given IPA size (which we do, see stage2_pt_levels()) + */ +#define ARM64_VTTBR_X(ipa, levels) ((ipa) - ((levels) * (PAGE_SHIFT - 3))) =20 -#define VTTBR_BADDR_MASK (((UL(1) << (PHYS_MASK_SHIFT - VTTBR_X)) - 1) <<= VTTBR_X) #define VTTBR_VMID_SHIFT (UL(48)) #define VTTBR_VMID_MASK(size) (_AT(u64, (1 << size) - 1) << VTTBR_VMID_SHI= FT) =20 diff --git a/arch/arm64/include/asm/kvm_mmu.h b/arch/arm64/include/asm/kvm_= mmu.h index a351722..813a72a 100644 --- a/arch/arm64/include/asm/kvm_mmu.h +++ b/arch/arm64/include/asm/kvm_mmu.h @@ -146,7 +146,6 @@ static inline unsigned long __kern_hyp_va(unsigned long= v) #define kvm_phys_shift(kvm) KVM_PHYS_SHIFT #define kvm_phys_size(kvm) (_AC(1, ULL) << kvm_phys_shift(kvm)) #define kvm_phys_mask(kvm) (kvm_phys_size(kvm) - _AC(1, ULL)) -#define kvm_vttbr_baddr_mask(kvm) VTTBR_BADDR_MASK =20 static inline bool kvm_page_empty(void *ptr) { @@ -503,6 +502,30 @@ static inline int hyp_map_aux_data(void) =20 #define kvm_phys_to_vttbr(addr) phys_to_ttbr(addr) =20 +/* + * Get the magic number 'x' for VTTBR:BADDR of this KVM instance. + * With v8.2 LVA extensions, 'x' should be a minimum of 6 with + * 52bit IPS. + */ +static inline int arm64_vttbr_x(u32 ipa_shift, u32 levels) +{ + int x =3D ARM64_VTTBR_X(ipa_shift, levels); + + return (IS_ENABLED(CONFIG_ARM64_PA_BITS_52) && x < 6) ? 6 : x; +} + +static inline u64 vttbr_baddr_mask(u32 ipa_shift, u32 levels) +{ + unsigned int x =3D arm64_vttbr_x(ipa_shift, levels); + + return GENMASK_ULL(PHYS_MASK_SHIFT - 1, x); +} + +static inline u64 kvm_vttbr_baddr_mask(struct kvm *kvm) +{ + return vttbr_baddr_mask(kvm_phys_shift(kvm), kvm_stage2_levels(kvm)); +} + static inline void *stage2_alloc_pgd(struct kvm *kvm) { return alloc_pages_exact(stage2_pgd_size(kvm), --=20 2.7.4 From nobody Mon Feb 9 15:13:28 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530271481821876.637325837133; Fri, 29 Jun 2018 04:24:41 -0700 (PDT) Received: from localhost ([::1]:41242 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYrW4-00061L-Vh for importer@patchew.org; Fri, 29 Jun 2018 07:24:41 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36555) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYrOP-00005O-0U for qemu-devel@nongnu.org; Fri, 29 Jun 2018 07:16:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fYrON-0002TI-RY for qemu-devel@nongnu.org; Fri, 29 Jun 2018 07:16:44 -0400 Received: from foss.arm.com ([217.140.101.70]:39394) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYrON-0002Ss-K8 for qemu-devel@nongnu.org; Fri, 29 Jun 2018 07:16:43 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0EC2918A; Fri, 29 Jun 2018 04:16:43 -0700 (PDT) Received: from en101.cambridge.arm.com (en101.cambridge.arm.com [10.1.206.73]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 889DF3F266; Fri, 29 Jun 2018 04:16:40 -0700 (PDT) From: Suzuki K Poulose To: linux-arm-kernel@lists.infradead.org Date: Fri, 29 Jun 2018 12:15:31 +0100 Message-Id: <1530270944-11351-12-git-send-email-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1530270944-11351-1-git-send-email-suzuki.poulose@arm.com> References: <1530270944-11351-1-git-send-email-suzuki.poulose@arm.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 217.140.101.70 Subject: [Qemu-devel] [PATCH v3 11/20] kvm: arm64: Helper for computing VTCR_EL2.SL0 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cdall@kernel.org, kvm@vger.kernel.org, Suzuki K Poulose , marc.zyngier@arm.com, catalin.marinas@arm.com, punit.agrawal@arm.com, will.deacon@arm.com, linux-kernel@vger.kernel.org, qemu-devel@nongnu.org, eric.auger@redhat.com, julien.grall@arm.com, james.morse@arm.com, Christoffer Dall , kvmarm@lists.cs.columbia.edu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" VTCR_EL2 holds the following key stage2 translation table parameters: SL0 - Entry level in the page table lookup. T0SZ - Denotes the size of the memory addressed by the table. We have been using fixed values for the SL0 depending on the page size as we have a fixed IPA size. But since we are about to make it dynamic, we need to calculate the SL0 at runtime per VM. This patch adds a helper to comput the value of SL0 for a given IPA. Cc: Marc Zyngier Cc: Christoffer Dall Signed-off-by: Suzuki K Poulose Reviewed-by: Eric Auger --- Changes since v2: - Part 2 of split from VTCR & VTTBR dynamic configuration --- arch/arm64/include/asm/kvm_arm.h | 35 ++++++++++++++++++++++++++++++++--- 1 file changed, 32 insertions(+), 3 deletions(-) diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_= arm.h index c557f45..11a7db0 100644 --- a/arch/arm64/include/asm/kvm_arm.h +++ b/arch/arm64/include/asm/kvm_arm.h @@ -153,7 +153,8 @@ * 2 level page tables (SL =3D 1) */ #define VTCR_EL2_TGRAN_FLAGS (VTCR_EL2_TG0_64K | VTCR_EL2_SL0_LVL1) -#define VTTBR_X_TGRAN_MAGIC 38 +#define VTCR_EL2_TGRAN_SL0_BASE 3UL + #elif defined(CONFIG_ARM64_16K_PAGES) /* * Stage2 translation configuration: @@ -161,7 +162,7 @@ * 2 level page tables (SL =3D 1) */ #define VTCR_EL2_TGRAN_FLAGS (VTCR_EL2_TG0_16K | VTCR_EL2_SL0_LVL1) -#define VTTBR_X_TGRAN_MAGIC 42 +#define VTCR_EL2_TGRAN_SL0_BASE 3UL #else /* 4K */ /* * Stage2 translation configuration: @@ -169,11 +170,39 @@ * 3 level page tables (SL =3D 1) */ #define VTCR_EL2_TGRAN_FLAGS (VTCR_EL2_TG0_4K | VTCR_EL2_SL0_LVL1) -#define VTTBR_X_TGRAN_MAGIC 37 +#define VTCR_EL2_TGRAN_SL0_BASE 2UL #endif =20 #define VTCR_EL2_FLAGS (VTCR_EL2_COMMON_BITS | VTCR_EL2_TGRAN_FLAGS) /* + * VTCR_EL2:SL0 indicates the entry level for Stage2 translation. + * Interestingly, it depends on the page size. + * See D.10.2.110, VTCR_EL2, in ARM DDI 0487B.b + * + * ----------------------------------------- + * | Entry level | 4K | 16K/64K | + * ------------------------------------------ + * | Level: 0 | 2 | - | + * ------------------------------------------ + * | Level: 1 | 1 | 2 | + * ------------------------------------------ + * | Level: 2 | 0 | 1 | + * ------------------------------------------ + * | Level: 3 | - | 0 | + * ------------------------------------------ + * + * That table roughly translates to : + * + * SL0(PAGE_SIZE, Entry_level) =3D SL0_BASE(PAGE_SIZE) - Entry_Level + * + * Where SL0_BASE(4K) =3D 2 and SL0_BASE(16K) =3D 3, SL0_BASE(64K) =3D 3, = provided + * we take care of ruling out the unsupported cases and + * Entry_Level =3D 4 - Number_of_levels. + * + */ +#define VTCR_EL2_SL0(levels) \ + ((VTCR_EL2_TGRAN_SL0_BASE - (4 - (levels))) << VTCR_EL2_SL0_SHIFT) +/* * ARM VMSAv8-64 defines an algorithm for finding the translation table * descriptors in section D4.2.8 in ARM DDI 0487B.b. * --=20 2.7.4 From nobody Mon Feb 9 15:13:28 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530271471811822.1898085849201; Fri, 29 Jun 2018 04:24:31 -0700 (PDT) Received: from localhost ([::1]:41240 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYrVu-0005sV-Th for importer@patchew.org; Fri, 29 Jun 2018 07:24:31 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36577) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYrOR-000082-Lc for qemu-devel@nongnu.org; Fri, 29 Jun 2018 07:16:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fYrOQ-0002Vm-FU for qemu-devel@nongnu.org; Fri, 29 Jun 2018 07:16:47 -0400 Received: from foss.arm.com ([217.140.101.70]:39410) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYrOQ-0002VV-7w for qemu-devel@nongnu.org; Fri, 29 Jun 2018 07:16:46 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A40EB1682; Fri, 29 Jun 2018 04:16:45 -0700 (PDT) Received: from en101.cambridge.arm.com (en101.cambridge.arm.com [10.1.206.73]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 4CA813F266; Fri, 29 Jun 2018 04:16:43 -0700 (PDT) From: Suzuki K Poulose To: linux-arm-kernel@lists.infradead.org Date: Fri, 29 Jun 2018 12:15:32 +0100 Message-Id: <1530270944-11351-13-git-send-email-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1530270944-11351-1-git-send-email-suzuki.poulose@arm.com> References: <1530270944-11351-1-git-send-email-suzuki.poulose@arm.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 217.140.101.70 Subject: [Qemu-devel] [PATCH v3 12/20] kvm: arm64: Add helper for loading the stage2 setting for a VM X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cdall@kernel.org, kvm@vger.kernel.org, Suzuki K Poulose , marc.zyngier@arm.com, catalin.marinas@arm.com, punit.agrawal@arm.com, will.deacon@arm.com, linux-kernel@vger.kernel.org, qemu-devel@nongnu.org, eric.auger@redhat.com, julien.grall@arm.com, james.morse@arm.com, kvmarm@lists.cs.columbia.edu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We load the stage2 context of a guest for different operations, including running the guest and tlb maintenance on behalf of the guest. As of now only the vttbr is private to the guest, but this is about to change with IPA per VM. Add a helper to load the stage2 configuration for a VM, which could do the right thing with the future changes. Cc: Christoffer Dall Cc: Marc Zyngier Signed-off-by: Suzuki K Poulose Reviewed-by: Eric Auger --- Changes since v2: - New patch --- arch/arm64/include/asm/kvm_hyp.h | 6 ++++++ arch/arm64/kvm/hyp/switch.c | 2 +- arch/arm64/kvm/hyp/tlb.c | 4 ++-- 3 files changed, 9 insertions(+), 3 deletions(-) diff --git a/arch/arm64/include/asm/kvm_hyp.h b/arch/arm64/include/asm/kvm_= hyp.h index 384c343..82f9994 100644 --- a/arch/arm64/include/asm/kvm_hyp.h +++ b/arch/arm64/include/asm/kvm_hyp.h @@ -155,5 +155,11 @@ void deactivate_traps_vhe_put(void); u64 __guest_enter(struct kvm_vcpu *vcpu, struct kvm_cpu_context *host_ctxt= ); void __noreturn __hyp_do_panic(unsigned long, ...); =20 +/* Must be called from hyp code running at EL2 */ +static __always_inline void __hyp_text __load_guest_stage2(struct kvm *kvm) +{ + write_sysreg(kvm->arch.vttbr, vttbr_el2); +} + #endif /* __ARM64_KVM_HYP_H__ */ =20 diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp/switch.c index d496ef5..355fb25 100644 --- a/arch/arm64/kvm/hyp/switch.c +++ b/arch/arm64/kvm/hyp/switch.c @@ -195,7 +195,7 @@ void deactivate_traps_vhe_put(void) =20 static void __hyp_text __activate_vm(struct kvm *kvm) { - write_sysreg(kvm->arch.vttbr, vttbr_el2); + __load_guest_stage2(kvm); } =20 static void __hyp_text __deactivate_vm(struct kvm_vcpu *vcpu) diff --git a/arch/arm64/kvm/hyp/tlb.c b/arch/arm64/kvm/hyp/tlb.c index 131c777..4dbd9c6 100644 --- a/arch/arm64/kvm/hyp/tlb.c +++ b/arch/arm64/kvm/hyp/tlb.c @@ -30,7 +30,7 @@ static void __hyp_text __tlb_switch_to_guest_vhe(struct k= vm *kvm) * bits. Changing E2H is impossible (goodbye TTBR1_EL2), so * let's flip TGE before executing the TLB operation. */ - write_sysreg(kvm->arch.vttbr, vttbr_el2); + __load_guest_stage2(kvm); val =3D read_sysreg(hcr_el2); val &=3D ~HCR_TGE; write_sysreg(val, hcr_el2); @@ -39,7 +39,7 @@ static void __hyp_text __tlb_switch_to_guest_vhe(struct k= vm *kvm) =20 static void __hyp_text __tlb_switch_to_guest_nvhe(struct kvm *kvm) { - write_sysreg(kvm->arch.vttbr, vttbr_el2); + __load_guest_stage2(kvm); isb(); } =20 --=20 2.7.4 From nobody Mon Feb 9 15:13:28 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530271827110611.3728776642897; Fri, 29 Jun 2018 04:30:27 -0700 (PDT) Received: from localhost ([::1]:41274 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYrbe-0002oa-AN for importer@patchew.org; Fri, 29 Jun 2018 07:30:26 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36607) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYrOX-0000Da-S7 for qemu-devel@nongnu.org; Fri, 29 Jun 2018 07:16:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fYrOT-0002Yd-0w for qemu-devel@nongnu.org; Fri, 29 Jun 2018 07:16:53 -0400 Received: from foss.arm.com ([217.140.101.70]:39424) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYrOS-0002Xn-P8 for qemu-devel@nongnu.org; Fri, 29 Jun 2018 07:16:48 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 44AE11684; Fri, 29 Jun 2018 04:16:48 -0700 (PDT) Received: from en101.cambridge.arm.com (en101.cambridge.arm.com [10.1.206.73]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id E1B973F266; Fri, 29 Jun 2018 04:16:45 -0700 (PDT) From: Suzuki K Poulose To: linux-arm-kernel@lists.infradead.org Date: Fri, 29 Jun 2018 12:15:33 +0100 Message-Id: <1530270944-11351-14-git-send-email-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1530270944-11351-1-git-send-email-suzuki.poulose@arm.com> References: <1530270944-11351-1-git-send-email-suzuki.poulose@arm.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 217.140.101.70 Subject: [Qemu-devel] [PATCH v3 13/20] kvm: arm64: Configure VTCR per VM X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cdall@kernel.org, kvm@vger.kernel.org, Suzuki K Poulose , marc.zyngier@arm.com, catalin.marinas@arm.com, punit.agrawal@arm.com, will.deacon@arm.com, linux-kernel@vger.kernel.org, qemu-devel@nongnu.org, eric.auger@redhat.com, julien.grall@arm.com, james.morse@arm.com, kvmarm@lists.cs.columbia.edu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We set VTCR_EL2 very early during the stage2 init and don't touch it ever. This is fine as we had a fixed IPA size. This patch changes the behavior to set the VTCR for a given VM, depending on its stage2 table. The common configuration for VTCR is still performed during the early init as we have to retain the hardware access flag update bits (VTCR_EL2_HA) per CPU (as they are only set for the CPUs which are capabile). The bits defining the number of levels in the page table (SL0) and and the size of the Input address to the translation (T0SZ) are programmed for each VM upon entry to the guest. Cc: Marc Zyngier Cc: Christoffer Dall Signed-off-by: Suzuki K Poulose --- Change since V2: - Load VTCR for TLB operations --- arch/arm64/include/asm/kvm_arm.h | 19 +++++++++---------- arch/arm64/include/asm/kvm_asm.h | 2 +- arch/arm64/include/asm/kvm_host.h | 9 ++++++--- arch/arm64/include/asm/kvm_hyp.h | 11 +++++++++++ arch/arm64/kvm/hyp/s2-setup.c | 17 +---------------- 5 files changed, 28 insertions(+), 30 deletions(-) diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_= arm.h index 11a7db0..b02c316 100644 --- a/arch/arm64/include/asm/kvm_arm.h +++ b/arch/arm64/include/asm/kvm_arm.h @@ -120,9 +120,7 @@ #define VTCR_EL2_IRGN0_WBWA TCR_IRGN0_WBWA #define VTCR_EL2_SL0_SHIFT 6 #define VTCR_EL2_SL0_MASK (3 << VTCR_EL2_SL0_SHIFT) -#define VTCR_EL2_SL0_LVL1 (1 << VTCR_EL2_SL0_SHIFT) #define VTCR_EL2_T0SZ_MASK 0x3f -#define VTCR_EL2_T0SZ_40B 24 #define VTCR_EL2_VS_SHIFT 19 #define VTCR_EL2_VS_8BIT (0 << VTCR_EL2_VS_SHIFT) #define VTCR_EL2_VS_16BIT (1 << VTCR_EL2_VS_SHIFT) @@ -137,43 +135,44 @@ * VTCR_EL2.PS is extracted from ID_AA64MMFR0_EL1.PARange at boot time * (see hyp-init.S). * + * VTCR_EL2.SL0 and T0SZ are configured per VM at runtime before switching= to + * the VM. + * * Note that when using 4K pages, we concatenate two first level page tabl= es * together. With 16K pages, we concatenate 16 first level page tables. * */ =20 -#define VTCR_EL2_T0SZ_IPA VTCR_EL2_T0SZ_40B #define VTCR_EL2_COMMON_BITS (VTCR_EL2_SH0_INNER | VTCR_EL2_ORGN0_WBWA | \ VTCR_EL2_IRGN0_WBWA | VTCR_EL2_RES1) +#define VTCR_EL2_PRIVATE_MASK (VTCR_EL2_SL0_MASK | VTCR_EL2_T0SZ_MASK) =20 #ifdef CONFIG_ARM64_64K_PAGES /* * Stage2 translation configuration: * 64kB pages (TG0 =3D 1) - * 2 level page tables (SL =3D 1) */ -#define VTCR_EL2_TGRAN_FLAGS (VTCR_EL2_TG0_64K | VTCR_EL2_SL0_LVL1) +#define VTCR_EL2_TGRAN VTCR_EL2_TG0_64K #define VTCR_EL2_TGRAN_SL0_BASE 3UL =20 #elif defined(CONFIG_ARM64_16K_PAGES) /* * Stage2 translation configuration: * 16kB pages (TG0 =3D 2) - * 2 level page tables (SL =3D 1) */ -#define VTCR_EL2_TGRAN_FLAGS (VTCR_EL2_TG0_16K | VTCR_EL2_SL0_LVL1) +#define VTCR_EL2_TGRAN VTCR_EL2_TG0_16K #define VTCR_EL2_TGRAN_SL0_BASE 3UL #else /* 4K */ /* * Stage2 translation configuration: * 4kB pages (TG0 =3D 0) - * 3 level page tables (SL =3D 1) */ -#define VTCR_EL2_TGRAN_FLAGS (VTCR_EL2_TG0_4K | VTCR_EL2_SL0_LVL1) +#define VTCR_EL2_TGRAN VTCR_EL2_TG0_4K #define VTCR_EL2_TGRAN_SL0_BASE 2UL #endif =20 -#define VTCR_EL2_FLAGS (VTCR_EL2_COMMON_BITS | VTCR_EL2_TGRAN_FLAGS) +#define VTCR_EL2_FLAGS (VTCR_EL2_COMMON_BITS | VTCR_EL2_TGRAN) + /* * VTCR_EL2:SL0 indicates the entry level for Stage2 translation. * Interestingly, it depends on the page size. diff --git a/arch/arm64/include/asm/kvm_asm.h b/arch/arm64/include/asm/kvm_= asm.h index 102b5a5..91372eb 100644 --- a/arch/arm64/include/asm/kvm_asm.h +++ b/arch/arm64/include/asm/kvm_asm.h @@ -72,7 +72,7 @@ extern void __vgic_v3_init_lrs(void); =20 extern u32 __kvm_get_mdcr_el2(void); =20 -extern u32 __init_stage2_translation(void); +extern void __init_stage2_translation(void); =20 /* Home-grown __this_cpu_{ptr,read} variants that always work at HYP */ #define __hyp_this_cpu_ptr(sym) \ diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index fe8777b..328f472 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -442,10 +442,13 @@ int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu, =20 static inline void __cpu_init_stage2(void) { - u32 parange =3D kvm_call_hyp(__init_stage2_translation); + u32 ps; =20 - WARN_ONCE(parange < 40, - "PARange is %d bits, unsupported configuration!", parange); + kvm_call_hyp(__init_stage2_translation); + /* Sanity check for minimum IPA size support */ + ps =3D id_aa64mmfr0_parange_to_phys_shift(read_sysreg(id_aa64mmfr0_el1) &= 0x7); + WARN_ONCE(ps < 40, + "PARange is %d bits, unsupported configuration!", ps); } =20 /* Guest/host FPSIMD coordination helpers */ diff --git a/arch/arm64/include/asm/kvm_hyp.h b/arch/arm64/include/asm/kvm_= hyp.h index 82f9994..3e8052d1 100644 --- a/arch/arm64/include/asm/kvm_hyp.h +++ b/arch/arm64/include/asm/kvm_hyp.h @@ -20,6 +20,7 @@ =20 #include #include +#include #include =20 #define __hyp_text __section(.hyp.text) notrace @@ -158,6 +159,16 @@ void __noreturn __hyp_do_panic(unsigned long, ...); /* Must be called from hyp code running at EL2 */ static __always_inline void __hyp_text __load_guest_stage2(struct kvm *kvm) { + /* + * Configure the VTCR translation control bits + * for this VM. + */ + u64 vtcr =3D read_sysreg(vtcr_el2); + + vtcr &=3D ~VTCR_EL2_PRIVATE_MASK; + vtcr |=3D VTCR_EL2_SL0(kvm_stage2_levels(kvm)) | + VTCR_EL2_T0SZ(kvm_phys_shift(kvm)); + write_sysreg(vtcr, vtcr_el2); write_sysreg(kvm->arch.vttbr, vttbr_el2); } =20 diff --git a/arch/arm64/kvm/hyp/s2-setup.c b/arch/arm64/kvm/hyp/s2-setup.c index 81094f1..6567315 100644 --- a/arch/arm64/kvm/hyp/s2-setup.c +++ b/arch/arm64/kvm/hyp/s2-setup.c @@ -19,13 +19,11 @@ #include #include #include -#include =20 -u32 __hyp_text __init_stage2_translation(void) +void __hyp_text __init_stage2_translation(void) { u64 val =3D VTCR_EL2_FLAGS; u64 parange; - u32 phys_shift; u64 tmp; =20 /* @@ -38,17 +36,6 @@ u32 __hyp_text __init_stage2_translation(void) parange =3D ID_AA64MMFR0_PARANGE_MAX; val |=3D parange << VTCR_EL2_PS_SHIFT; =20 - /* Compute the actual PARange... */ - phys_shift =3D id_aa64mmfr0_parange_to_phys_shift(parange); - - /* - * ... and clamp it to 40 bits, unless we have some braindead - * HW that implements less than that. In all cases, we'll - * return that value for the rest of the kernel to decide what - * to do. - */ - val |=3D VTCR_EL2_T0SZ(phys_shift > 40 ? 40 : phys_shift); - /* * Check the availability of Hardware Access Flag / Dirty Bit * Management in ID_AA64MMFR1_EL1 and enable the feature in VTCR_EL2. @@ -67,6 +54,4 @@ u32 __hyp_text __init_stage2_translation(void) VTCR_EL2_VS_8BIT; =20 write_sysreg(val, vtcr_el2); - - return phys_shift; } --=20 2.7.4 From nobody Mon Feb 9 15:13:28 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 153027164382891.62662892050207; Fri, 29 Jun 2018 04:27:23 -0700 (PDT) Received: from localhost ([::1]:41258 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYrYb-000093-Ou for importer@patchew.org; Fri, 29 Jun 2018 07:27:17 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36609) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYrOY-0000Di-05 for qemu-devel@nongnu.org; Fri, 29 Jun 2018 07:16:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fYrOV-0002d7-TC for qemu-devel@nongnu.org; Fri, 29 Jun 2018 07:16:53 -0400 Received: from foss.arm.com ([217.140.101.70]:39448) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYrOV-0002br-K3 for qemu-devel@nongnu.org; Fri, 29 Jun 2018 07:16:51 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 097EB16A3; Fri, 29 Jun 2018 04:16:51 -0700 (PDT) Received: from en101.cambridge.arm.com (en101.cambridge.arm.com [10.1.206.73]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 835BB3F266; Fri, 29 Jun 2018 04:16:48 -0700 (PDT) From: Suzuki K Poulose To: linux-arm-kernel@lists.infradead.org Date: Fri, 29 Jun 2018 12:15:34 +0100 Message-Id: <1530270944-11351-15-git-send-email-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1530270944-11351-1-git-send-email-suzuki.poulose@arm.com> References: <1530270944-11351-1-git-send-email-suzuki.poulose@arm.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 217.140.101.70 Subject: [Qemu-devel] [PATCH v3 14/20] kvm: arm/arm64: Expose supported physical address limit for VM X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydel , cdall@kernel.org, kvm@vger.kernel.org, Suzuki K Poulose , marc.zyngier@arm.com, catalin.marinas@arm.com, punit.agrawal@arm.com, will.deacon@arm.com, linux-kernel@vger.kernel.org, qemu-devel@nongnu.org, eric.auger@redhat.com, julien.grall@arm.com, james.morse@arm.com, kvmarm@lists.cs.columbia.edu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Expose the maximum physical address size supported by the host for a VM. This could be later used by the userspace to choose the appropriate size for a given VM. The limit is determined as the minimum of actual CPU limit, the kernel limit (i.e, either 48 or 52) and the stage2 page table support limit (which is 40bits at the moment). For backward compatibility, we support a minimum of 40bits. The limit will be lifted as we add support for the stage2 to support the host kernel PA limit. This value may be different from what is exposed to the VM via CPU ID registers. The limit only applies to the stage2 page table. Cc: Christoffer Dall Cc: Marc Zyngier Cc: Peter Maydel Signed-off-by: Suzuki K Poulose --- Changes since V2: - Bump the ioctl number --- Documentation/virtual/kvm/api.txt | 15 +++++++++++++++ arch/arm/include/asm/kvm_mmu.h | 5 +++++ arch/arm64/include/asm/kvm_mmu.h | 5 +++++ include/uapi/linux/kvm.h | 6 ++++++ virt/kvm/arm/arm.c | 6 ++++++ 5 files changed, 37 insertions(+) diff --git a/Documentation/virtual/kvm/api.txt b/Documentation/virtual/kvm/= api.txt index d10944e..662374b 100644 --- a/Documentation/virtual/kvm/api.txt +++ b/Documentation/virtual/kvm/api.txt @@ -3561,6 +3561,21 @@ Returns: 0 on success, -ENOENT on deassign if the conn_id isn't registered -EEXIST on assign if the conn_id is already registered =20 +4.113 KVM_ARM_GET_MAX_VM_PHYS_SHIFT +Capability: basic +Architectures: arm, arm64 +Type: system ioctl +Parameters: none +Returns: log2(Maximum Guest physical address space size) supported by the +hypervisor. + +This ioctl can be used to identify the maximum guest physical address +space size supported by the hypervisor. The returned value indicates the +maximum size of the address that can be resolved by the stage2 +translation table on arm/arm64. On arm64, the value is decided based +on the host kernel configuration and the system wide safe value of +ID_AA64MMFR0_EL1:PARange. This may not match the value exposed to the +VM in CPU ID registers. =20 5. The kvm_run structure ------------------------ diff --git a/arch/arm/include/asm/kvm_mmu.h b/arch/arm/include/asm/kvm_mmu.h index b2da5a4..d86f8dd 100644 --- a/arch/arm/include/asm/kvm_mmu.h +++ b/arch/arm/include/asm/kvm_mmu.h @@ -380,6 +380,11 @@ static inline void *stage2_alloc_pgd(struct kvm *kvm) =20 #define kvm_phys_to_vttbr(addr) (addr) =20 +static inline u32 kvm_get_ipa_limit(void) +{ + return KVM_PHYS_SHIFT; +} + #endif /* !__ASSEMBLY__ */ =20 #endif /* __ARM_KVM_MMU_H__ */ diff --git a/arch/arm64/include/asm/kvm_mmu.h b/arch/arm64/include/asm/kvm_= mmu.h index 813a72a..b4564d8 100644 --- a/arch/arm64/include/asm/kvm_mmu.h +++ b/arch/arm64/include/asm/kvm_mmu.h @@ -532,5 +532,10 @@ static inline void *stage2_alloc_pgd(struct kvm *kvm) GFP_KERNEL | __GFP_ZERO); } =20 +static inline u32 kvm_get_ipa_limit(void) +{ + return KVM_PHYS_SHIFT; +} + #endif /* __ASSEMBLY__ */ #endif /* __ARM64_KVM_MMU_H__ */ diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h index b6270a3..4df9bb6 100644 --- a/include/uapi/linux/kvm.h +++ b/include/uapi/linux/kvm.h @@ -775,6 +775,12 @@ struct kvm_ppc_resize_hpt { #define KVM_GET_MSR_FEATURE_INDEX_LIST _IOWR(KVMIO, 0x0a, struct kvm_ms= r_list) =20 /* + * Get the maximum physical address size supported by the host. + * Returns log2(Max-Physical-Address-Size) + */ +#define KVM_ARM_GET_MAX_VM_PHYS_SHIFT _IO(KVMIO, 0x0b) + +/* * Extension capability list. */ #define KVM_CAP_IRQCHIP 0 diff --git a/virt/kvm/arm/arm.c b/virt/kvm/arm/arm.c index d2637bb..0d99e67 100644 --- a/virt/kvm/arm/arm.c +++ b/virt/kvm/arm/arm.c @@ -66,6 +66,7 @@ static atomic64_t kvm_vmid_gen =3D ATOMIC64_INIT(1); static u32 kvm_next_vmid; static unsigned int kvm_vmid_bits __read_mostly; static DEFINE_RWLOCK(kvm_vmid_lock); +static u32 kvm_ipa_limit; =20 static bool vgic_present; =20 @@ -248,6 +249,9 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long = ext) long kvm_arch_dev_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg) { + if (ioctl =3D=3D KVM_ARM_GET_MAX_VM_PHYS_SHIFT) + return kvm_ipa_limit; + return -EINVAL; } =20 @@ -1361,6 +1365,8 @@ static int init_common_resources(void) kvm_vmid_bits =3D kvm_get_vmid_bits(); kvm_info("%d-bit VMID\n", kvm_vmid_bits); =20 + kvm_ipa_limit =3D kvm_get_ipa_limit(); + return 0; } =20 --=20 2.7.4 From nobody Mon Feb 9 15:13:28 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530271650287165.0607121877896; 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Fri, 29 Jun 2018 04:16:51 -0700 (PDT) From: Suzuki K Poulose To: linux-arm-kernel@lists.infradead.org Date: Fri, 29 Jun 2018 12:15:35 +0100 Message-Id: <1530270944-11351-16-git-send-email-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1530270944-11351-1-git-send-email-suzuki.poulose@arm.com> References: <1530270944-11351-1-git-send-email-suzuki.poulose@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 217.140.101.70 Subject: [Qemu-devel] [PATCH v3 15/20] kvm: arm/arm64: Allow tuning the physical address size for VM X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydel , =?UTF-8?q?Radim=20Kr=C4=8Dm=C3=A1=C5=99?= , cdall@kernel.org, kvm@vger.kernel.org, Suzuki K Poulose , marc.zyngier@arm.com, catalin.marinas@arm.com, punit.agrawal@arm.com, will.deacon@arm.com, linux-kernel@vger.kernel.org, qemu-devel@nongnu.org, eric.auger@redhat.com, julien.grall@arm.com, james.morse@arm.com, Paolo Bonzini , kvmarm@lists.cs.columbia.edu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Allow specifying the physical address size for a new VM via the kvm_type argument for KVM_CREATE_VM ioctl. This allows us to finalise the stage2 page table format as early as possible and hence perform the right checks on the memory slots without complication. The size is encoded as Log2(PA_Size) in the bits[7:0] of the type field and can encode more information in the future if required. The IPA size is still capped at 40bits. Cc: Marc Zyngier Cc: Christoffer Dall Cc: Peter Maydel Cc: Paolo Bonzini Cc: Radim Kr=C4=8Dm=C3=A1=C5=99 Signed-off-by: Suzuki K Poulose --- arch/arm/include/asm/kvm_mmu.h | 2 ++ arch/arm64/include/asm/kvm_arm.h | 10 +++------- arch/arm64/include/asm/kvm_mmu.h | 2 ++ include/uapi/linux/kvm.h | 10 ++++++++++ virt/kvm/arm/arm.c | 24 ++++++++++++++++++++++-- 5 files changed, 39 insertions(+), 9 deletions(-) diff --git a/arch/arm/include/asm/kvm_mmu.h b/arch/arm/include/asm/kvm_mmu.h index d86f8dd..bcc3dd9 100644 --- a/arch/arm/include/asm/kvm_mmu.h +++ b/arch/arm/include/asm/kvm_mmu.h @@ -385,6 +385,8 @@ static inline u32 kvm_get_ipa_limit(void) return KVM_PHYS_SHIFT; } =20 +static inline void kvm_config_stage2(struct kvm *kvm, u32 ipa_shift) {} + #endif /* !__ASSEMBLY__ */ =20 #endif /* __ARM_KVM_MMU_H__ */ diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_= arm.h index b02c316..2e90942 100644 --- a/arch/arm64/include/asm/kvm_arm.h +++ b/arch/arm64/include/asm/kvm_arm.h @@ -128,19 +128,15 @@ #define VTCR_EL2_T0SZ(x) TCR_T0SZ(x) =20 /* - * We configure the Stage-2 page tables to always restrict the IPA space t= o be - * 40 bits wide (T0SZ =3D 24). Systems with a PARange smaller than 40 bit= s are - * not known to exist and will break with this configuration. + * We configure the Stage-2 page tables based on the requested size of + * IPA for each VM. The default size is set to 40bits and is not allowed + * go below that limit (for backward compatibility). * * VTCR_EL2.PS is extracted from ID_AA64MMFR0_EL1.PARange at boot time * (see hyp-init.S). * * VTCR_EL2.SL0 and T0SZ are configured per VM at runtime before switching= to * the VM. - * - * Note that when using 4K pages, we concatenate two first level page tabl= es - * together. With 16K pages, we concatenate 16 first level page tables. - * */ =20 #define VTCR_EL2_COMMON_BITS (VTCR_EL2_SH0_INNER | VTCR_EL2_ORGN0_WBWA | \ diff --git a/arch/arm64/include/asm/kvm_mmu.h b/arch/arm64/include/asm/kvm_= mmu.h index b4564d8..f3fb05a3 100644 --- a/arch/arm64/include/asm/kvm_mmu.h +++ b/arch/arm64/include/asm/kvm_mmu.h @@ -537,5 +537,7 @@ static inline u32 kvm_get_ipa_limit(void) return KVM_PHYS_SHIFT; } =20 +static inline void kvm_config_stage2(struct kvm *kvm, u32 ipa_shift) {} + #endif /* __ASSEMBLY__ */ #endif /* __ARM64_KVM_MMU_H__ */ diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h index 4df9bb6..fa4cab0 100644 --- a/include/uapi/linux/kvm.h +++ b/include/uapi/linux/kvm.h @@ -751,6 +751,16 @@ struct kvm_ppc_resize_hpt { #define KVM_S390_SIE_PAGE_OFFSET 1 =20 /* + * On arm/arm64, machine type can be used to request the physical + * address size for the VM. Bits [7-0] have been reserved for the + * PA size shift (i.e, log2(PA_Size)). For backward compatibility, + * value 0 implies the default IPA size, which is 40bits. + */ +#define KVM_VM_TYPE_ARM_PHYS_SHIFT_MASK 0xff +#define KVM_VM_TYPE_ARM_PHYS_SHIFT(x) \ + ((x) & KVM_VM_TYPE_ARM_PHYS_SHIFT_MASK) + +/* * ioctls for /dev/kvm fds: */ #define KVM_GET_API_VERSION _IO(KVMIO, 0x00) diff --git a/virt/kvm/arm/arm.c b/virt/kvm/arm/arm.c index 0d99e67..1085761 100644 --- a/virt/kvm/arm/arm.c +++ b/virt/kvm/arm/arm.c @@ -112,6 +112,25 @@ void kvm_arch_check_processor_compat(void *rtn) } =20 =20 +static int kvm_arch_config_vm(struct kvm *kvm, unsigned long type) +{ + u32 ipa_shift =3D KVM_VM_TYPE_ARM_PHYS_SHIFT(type); + + /* + * Make sure the size, if specified, is within the range of + * default size and supported maximum limit. + */ + if (ipa_shift) { + if (ipa_shift < KVM_PHYS_SHIFT || ipa_shift > kvm_ipa_limit) + return -EINVAL; + } else { + ipa_shift =3D KVM_PHYS_SHIFT; + } + + kvm_config_stage2(kvm, ipa_shift); + return 0; +} + /** * kvm_arch_init_vm - initializes a VM data structure * @kvm: pointer to the KVM struct @@ -120,8 +139,9 @@ int kvm_arch_init_vm(struct kvm *kvm, unsigned long typ= e) { int ret, cpu; =20 - if (type) - return -EINVAL; + ret =3D kvm_arch_config_vm(kvm, type); + if (ret) + return ret; =20 kvm->arch.last_vcpu_ran =3D alloc_percpu(typeof(*kvm->arch.last_vcpu_ran)= ); if (!kvm->arch.last_vcpu_ran) --=20 2.7.4 From nobody Mon Feb 9 15:13:28 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530272013384184.19339864259712; Fri, 29 Jun 2018 04:33:33 -0700 (PDT) Received: from localhost ([::1]:41292 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYree-0005n6-Kh for importer@patchew.org; Fri, 29 Jun 2018 07:33:32 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36643) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYrOc-0000GD-SD for qemu-devel@nongnu.org; Fri, 29 Jun 2018 07:17:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fYrOb-0002m7-Ei for qemu-devel@nongnu.org; Fri, 29 Jun 2018 07:16:58 -0400 Received: from foss.arm.com ([217.140.101.70]:39472) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYrOb-0002lp-64 for qemu-devel@nongnu.org; Fri, 29 Jun 2018 07:16:57 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A9FB61993; Fri, 29 Jun 2018 04:16:56 -0700 (PDT) Received: from en101.cambridge.arm.com (en101.cambridge.arm.com [10.1.206.73]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 52CAF3F266; Fri, 29 Jun 2018 04:16:54 -0700 (PDT) From: Suzuki K Poulose To: linux-arm-kernel@lists.infradead.org Date: Fri, 29 Jun 2018 12:15:36 +0100 Message-Id: <1530270944-11351-17-git-send-email-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1530270944-11351-1-git-send-email-suzuki.poulose@arm.com> References: <1530270944-11351-1-git-send-email-suzuki.poulose@arm.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 217.140.101.70 Subject: [Qemu-devel] [PATCH v3 16/20] kvm: arm64: Switch to per VM IPA limit X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cdall@kernel.org, kvm@vger.kernel.org, Suzuki K Poulose , marc.zyngier@arm.com, catalin.marinas@arm.com, punit.agrawal@arm.com, will.deacon@arm.com, linux-kernel@vger.kernel.org, qemu-devel@nongnu.org, eric.auger@redhat.com, julien.grall@arm.com, james.morse@arm.com, kvmarm@lists.cs.columbia.edu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Now that we can manage the stage2 page table per VM, switch the configuration details to per VM instance. We keep track of the IPA bits, number of page table levels and the VTCR bits (which depends on the IPA and the number of levels). While at it, remove unused pgd_lock field from kvm_arch for arm64. Cc: Marc Zyngier Cc: Christoffer Dall Signed-off-by: Suzuki K Poulose --- arch/arm64/include/asm/kvm_host.h | 14 ++++++++++++-- arch/arm64/include/asm/kvm_hyp.h | 3 +-- arch/arm64/include/asm/kvm_mmu.h | 20 ++++++++++++++++++-- arch/arm64/include/asm/stage2_pgtable.h | 1 - virt/kvm/arm/mmu.c | 4 ++++ 5 files changed, 35 insertions(+), 7 deletions(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index 328f472..9a15860 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -61,13 +61,23 @@ struct kvm_arch { u64 vmid_gen; u32 vmid; =20 - /* 1-level 2nd stage table and lock */ - spinlock_t pgd_lock; + /* stage-2 page table */ pgd_t *pgd; =20 /* VTTBR value associated with above pgd and vmid */ u64 vttbr; =20 + /* Private bits of VTCR_EL2 for this VM */ + u64 vtcr_private; + /* Size of the PA size for this guest */ + u8 phys_shift; + /* + * Number of levels in page table. We could always calculate + * it from phys_shift above. We cache it for faster switches + * in stage2 page table helpers. + */ + u8 s2_levels; + /* The last vcpu id that ran on each physical CPU */ int __percpu *last_vcpu_ran; =20 diff --git a/arch/arm64/include/asm/kvm_hyp.h b/arch/arm64/include/asm/kvm_= hyp.h index 3e8052d1..699f678 100644 --- a/arch/arm64/include/asm/kvm_hyp.h +++ b/arch/arm64/include/asm/kvm_hyp.h @@ -166,8 +166,7 @@ static __always_inline void __hyp_text __load_guest_sta= ge2(struct kvm *kvm) u64 vtcr =3D read_sysreg(vtcr_el2); =20 vtcr &=3D ~VTCR_EL2_PRIVATE_MASK; - vtcr |=3D VTCR_EL2_SL0(kvm_stage2_levels(kvm)) | - VTCR_EL2_T0SZ(kvm_phys_shift(kvm)); + vtcr |=3D kvm->arch.vtcr_private; write_sysreg(vtcr, vtcr_el2); write_sysreg(kvm->arch.vttbr, vttbr_el2); } diff --git a/arch/arm64/include/asm/kvm_mmu.h b/arch/arm64/include/asm/kvm_= mmu.h index f3fb05a3..a291cdc 100644 --- a/arch/arm64/include/asm/kvm_mmu.h +++ b/arch/arm64/include/asm/kvm_mmu.h @@ -143,9 +143,10 @@ static inline unsigned long __kern_hyp_va(unsigned lon= g v) */ #define KVM_PHYS_SHIFT (40) =20 -#define kvm_phys_shift(kvm) KVM_PHYS_SHIFT +#define kvm_phys_shift(kvm) (kvm->arch.phys_shift) #define kvm_phys_size(kvm) (_AC(1, ULL) << kvm_phys_shift(kvm)) #define kvm_phys_mask(kvm) (kvm_phys_size(kvm) - _AC(1, ULL)) +#define kvm_stage2_levels(kvm) (kvm->arch.s2_levels) =20 static inline bool kvm_page_empty(void *ptr) { @@ -528,6 +529,18 @@ static inline u64 kvm_vttbr_baddr_mask(struct kvm *kvm) =20 static inline void *stage2_alloc_pgd(struct kvm *kvm) { + u32 ipa, lvls; + + /* + * Stage2 page table can support concatenation of (upto 16) tables + * at the entry level, thereby reducing the number of levels. + */ + ipa =3D kvm_phys_shift(kvm); + lvls =3D stage2_pt_levels(ipa); + + kvm->arch.s2_levels =3D lvls; + kvm->arch.vtcr_private =3D VTCR_EL2_SL0(lvls) | TCR_T0SZ(ipa); + return alloc_pages_exact(stage2_pgd_size(kvm), GFP_KERNEL | __GFP_ZERO); } @@ -537,7 +550,10 @@ static inline u32 kvm_get_ipa_limit(void) return KVM_PHYS_SHIFT; } =20 -static inline void kvm_config_stage2(struct kvm *kvm, u32 ipa_shift) {} +static inline void kvm_config_stage2(struct kvm *kvm, u32 ipa_shift) +{ + kvm->arch.phys_shift =3D ipa_shift; +} =20 #endif /* __ASSEMBLY__ */ #endif /* __ARM64_KVM_MMU_H__ */ diff --git a/arch/arm64/include/asm/stage2_pgtable.h b/arch/arm64/include/a= sm/stage2_pgtable.h index ffc37cc..91d7936 100644 --- a/arch/arm64/include/asm/stage2_pgtable.h +++ b/arch/arm64/include/asm/stage2_pgtable.h @@ -65,7 +65,6 @@ #define __s2_pgd_ptrs(pa, lvls) (1 << ((pa) - pt_levels_pgdir_shift((lvls)= ))) #define __s2_pgd_size(pa, lvls) (__s2_pgd_ptrs((pa), (lvls)) * sizeof(pgd_= t)) =20 -#define kvm_stage2_levels(kvm) stage2_pt_levels(kvm_phys_shift(kvm)) #define stage2_pgdir_shift(kvm) \ pt_levels_pgdir_shift(kvm_stage2_levels(kvm)) #define stage2_pgdir_size(kvm) (_AC(1, UL) << stage2_pgdir_shift((kvm))) diff --git a/virt/kvm/arm/mmu.c b/virt/kvm/arm/mmu.c index a339e00..d7822e1 100644 --- a/virt/kvm/arm/mmu.c +++ b/virt/kvm/arm/mmu.c @@ -867,6 +867,10 @@ int kvm_alloc_stage2_pgd(struct kvm *kvm) return -EINVAL; } =20 + /* Make sure we have the stage2 configured for this VM */ + if (WARN_ON(!kvm_phys_shift(kvm))) + return -EINVAL; + /* Allocate the HW PGD, making sure that each page gets its own refcount = */ pgd =3D stage2_alloc_pgd(kvm); if (!pgd) --=20 2.7.4 From nobody Mon Feb 9 15:13:28 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530271652080204.49709732062058; Fri, 29 Jun 2018 04:27:32 -0700 (PDT) Received: from localhost ([::1]:41260 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYrYm-0000JL-8D for importer@patchew.org; Fri, 29 Jun 2018 07:27:28 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36662) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYrOh-0000KC-Tu for qemu-devel@nongnu.org; Fri, 29 Jun 2018 07:17:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fYrOe-0002px-9E for qemu-devel@nongnu.org; Fri, 29 Jun 2018 07:17:03 -0400 Received: from foss.arm.com ([217.140.101.70]:39494) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYrOd-0002p1-WB for qemu-devel@nongnu.org; Fri, 29 Jun 2018 07:17:00 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6ECE518A; Fri, 29 Jun 2018 04:16:59 -0700 (PDT) Received: from en101.cambridge.arm.com (en101.cambridge.arm.com [10.1.206.73]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id E83683F266; Fri, 29 Jun 2018 04:16:56 -0700 (PDT) From: Suzuki K Poulose To: linux-arm-kernel@lists.infradead.org Date: Fri, 29 Jun 2018 12:15:37 +0100 Message-Id: <1530270944-11351-18-git-send-email-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1530270944-11351-1-git-send-email-suzuki.poulose@arm.com> References: <1530270944-11351-1-git-send-email-suzuki.poulose@arm.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 217.140.101.70 Subject: [Qemu-devel] [PATCH v3 17/20] vgic: Add support for 52bit guest physical address X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cdall@kernel.org, kvm@vger.kernel.org, Suzuki K Poulose , marc.zyngier@arm.com, catalin.marinas@arm.com, punit.agrawal@arm.com, will.deacon@arm.com, linux-kernel@vger.kernel.org, Kristina Martsenko , qemu-devel@nongnu.org, eric.auger@redhat.com, julien.grall@arm.com, james.morse@arm.com, kvmarm@lists.cs.columbia.edu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Kristina Martsenko Add support for handling 52bit guest physical address to the VGIC layer. So far we have limited the guest physical address to 48bits, by explicitly masking the upper bits. This patch removes the restriction. We do not have to check if the host supports 52bit as the gpa is always validated during an access. (e.g, kvm_{read/write}_guest, kvm_is_visible_gfn()). Also, the ITS table save-restore is also not affected with the enhancement. The DTE entries already store the bits[51:8] of the ITT_addr (with a 256byte alignment). Cc: Marc Zyngier Cc: Christoffer Dall Signed-off-by: Kristina Martsenko [ Macro clean ups, fix PROPBASER and PENDBASER accesses ] Signed-off-by: Suzuki K Poulose --- include/linux/irqchip/arm-gic-v3.h | 5 +++++ virt/kvm/arm/vgic/vgic-its.c | 36 ++++++++++------------------------= -- virt/kvm/arm/vgic/vgic-mmio-v3.c | 2 -- 3 files changed, 15 insertions(+), 28 deletions(-) diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm= -gic-v3.h index cbb872c..bc4b95b 100644 --- a/include/linux/irqchip/arm-gic-v3.h +++ b/include/linux/irqchip/arm-gic-v3.h @@ -346,6 +346,8 @@ #define GITS_CBASER_RaWaWt GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWa= Wt) #define GITS_CBASER_RaWaWb GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWa= Wb) =20 +#define GITS_CBASER_ADDRESS(cbaser) ((cbaser) & GENMASK_ULL(52, 12)) + #define GITS_BASER_NR_REGS 8 =20 #define GITS_BASER_VALID (1ULL << 63) @@ -377,6 +379,9 @@ #define GITS_BASER_ENTRY_SIZE_MASK GENMASK_ULL(52, 48) #define GITS_BASER_PHYS_52_to_48(phys) \ (((phys) & GENMASK_ULL(47, 16)) | (((phys) >> 48) & 0xf) << 12) +#define GITS_BASER_ADDR_48_to_52(baser) \ + (((baser) & GENMASK_ULL(47, 16)) | (((baser) >> 12) & 0xf) << 48) + #define GITS_BASER_SHAREABILITY_SHIFT (10) #define GITS_BASER_InnerShareable \ GIC_BASER_SHAREABILITY(GITS_BASER, InnerShareable) diff --git a/virt/kvm/arm/vgic/vgic-its.c b/virt/kvm/arm/vgic/vgic-its.c index 4ed79c9..c6eb390 100644 --- a/virt/kvm/arm/vgic/vgic-its.c +++ b/virt/kvm/arm/vgic/vgic-its.c @@ -234,13 +234,6 @@ static struct its_ite *find_ite(struct vgic_its *its, = u32 device_id, list_for_each_entry(dev, &(its)->device_list, dev_list) \ list_for_each_entry(ite, &(dev)->itt_head, ite_list) =20 -/* - * We only implement 48 bits of PA at the moment, although the ITS - * supports more. Let's be restrictive here. - */ -#define BASER_ADDRESS(x) ((x) & GENMASK_ULL(47, 16)) -#define CBASER_ADDRESS(x) ((x) & GENMASK_ULL(47, 12)) - #define GIC_LPI_OFFSET 8192 =20 #define VITS_TYPER_IDBITS 16 @@ -752,6 +745,7 @@ static bool vgic_its_check_id(struct vgic_its *its, u64= baser, u32 id, { int l1_tbl_size =3D GITS_BASER_NR_PAGES(baser) * SZ_64K; u64 indirect_ptr, type =3D GITS_BASER_TYPE(baser); + phys_addr_t base =3D GITS_BASER_ADDR_48_to_52(baser); int esz =3D GITS_BASER_ENTRY_SIZE(baser); int index; gfn_t gfn; @@ -776,7 +770,7 @@ static bool vgic_its_check_id(struct vgic_its *its, u64= baser, u32 id, if (id >=3D (l1_tbl_size / esz)) return false; =20 - addr =3D BASER_ADDRESS(baser) + id * esz; + addr =3D base + id * esz; gfn =3D addr >> PAGE_SHIFT; =20 if (eaddr) @@ -791,7 +785,7 @@ static bool vgic_its_check_id(struct vgic_its *its, u64= baser, u32 id, =20 /* Each 1st level entry is represented by a 64-bit value. */ if (kvm_read_guest_lock(its->dev->kvm, - BASER_ADDRESS(baser) + index * sizeof(indirect_ptr), + base + index * sizeof(indirect_ptr), &indirect_ptr, sizeof(indirect_ptr))) return false; =20 @@ -801,11 +795,7 @@ static bool vgic_its_check_id(struct vgic_its *its, u6= 4 baser, u32 id, if (!(indirect_ptr & BIT_ULL(63))) return false; =20 - /* - * Mask the guest physical address and calculate the frame number. - * Any address beyond our supported 48 bits of PA will be caught - * by the actual check in the final step. - */ + /* Mask the guest physical address and calculate the frame number. */ indirect_ptr &=3D GENMASK_ULL(51, 16); =20 /* Find the address of the actual entry */ @@ -1297,9 +1287,6 @@ static u64 vgic_sanitise_its_baser(u64 reg) GITS_BASER_OUTER_CACHEABILITY_SHIFT, vgic_sanitise_outer_cacheability); =20 - /* Bits 15:12 contain bits 51:48 of the PA, which we don't support. */ - reg &=3D ~GENMASK_ULL(15, 12); - /* We support only one (ITS) page size: 64K */ reg =3D (reg & ~GITS_BASER_PAGE_SIZE_MASK) | GITS_BASER_PAGE_SIZE_64K; =20 @@ -1318,11 +1305,8 @@ static u64 vgic_sanitise_its_cbaser(u64 reg) GITS_CBASER_OUTER_CACHEABILITY_SHIFT, vgic_sanitise_outer_cacheability); =20 - /* - * Sanitise the physical address to be 64k aligned. - * Also limit the physical addresses to 48 bits. - */ - reg &=3D ~(GENMASK_ULL(51, 48) | GENMASK_ULL(15, 12)); + /* Sanitise the physical address to be 64k aligned. */ + reg &=3D ~GENMASK_ULL(15, 12); =20 return reg; } @@ -1368,7 +1352,7 @@ static void vgic_its_process_commands(struct kvm *kvm= , struct vgic_its *its) if (!its->enabled) return; =20 - cbaser =3D CBASER_ADDRESS(its->cbaser); + cbaser =3D GITS_CBASER_ADDRESS(its->cbaser); =20 while (its->cwriter !=3D its->creadr) { int ret =3D kvm_read_guest_lock(kvm, cbaser + its->creadr, @@ -2226,7 +2210,7 @@ static int vgic_its_restore_device_tables(struct vgic= _its *its) if (!(baser & GITS_BASER_VALID)) return 0; =20 - l1_gpa =3D BASER_ADDRESS(baser); + l1_gpa =3D GITS_BASER_ADDR_48_to_52(baser); =20 if (baser & GITS_BASER_INDIRECT) { l1_esz =3D GITS_LVL1_ENTRY_SIZE; @@ -2298,7 +2282,7 @@ static int vgic_its_save_collection_table(struct vgic= _its *its) { const struct vgic_its_abi *abi =3D vgic_its_get_abi(its); u64 baser =3D its->baser_coll_table; - gpa_t gpa =3D BASER_ADDRESS(baser); + gpa_t gpa =3D GITS_BASER_ADDR_48_to_52(baser); struct its_collection *collection; u64 val; size_t max_size, filled =3D 0; @@ -2347,7 +2331,7 @@ static int vgic_its_restore_collection_table(struct v= gic_its *its) if (!(baser & GITS_BASER_VALID)) return 0; =20 - gpa =3D BASER_ADDRESS(baser); + gpa =3D GITS_BASER_ADDR_48_to_52(baser); =20 max_size =3D GITS_BASER_NR_PAGES(baser) * SZ_64K; =20 diff --git a/virt/kvm/arm/vgic/vgic-mmio-v3.c b/virt/kvm/arm/vgic/vgic-mmio= -v3.c index 2877840..64647be 100644 --- a/virt/kvm/arm/vgic/vgic-mmio-v3.c +++ b/virt/kvm/arm/vgic/vgic-mmio-v3.c @@ -338,7 +338,6 @@ static u64 vgic_sanitise_pendbaser(u64 reg) vgic_sanitise_outer_cacheability); =20 reg &=3D ~PENDBASER_RES0_MASK; - reg &=3D ~GENMASK_ULL(51, 48); =20 return reg; } @@ -356,7 +355,6 @@ static u64 vgic_sanitise_propbaser(u64 reg) vgic_sanitise_outer_cacheability); =20 reg &=3D ~PROPBASER_RES0_MASK; - reg &=3D ~GENMASK_ULL(51, 48); return reg; } =20 --=20 2.7.4 From nobody Mon Feb 9 15:13:28 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530271811388553.3406821635211; Fri, 29 Jun 2018 04:30:11 -0700 (PDT) Received: from localhost ([::1]:41273 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYrbO-0002bS-Hu for importer@patchew.org; Fri, 29 Jun 2018 07:30:10 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36664) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYrOi-0000KD-4G for qemu-devel@nongnu.org; Fri, 29 Jun 2018 07:17:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fYrOh-0002tv-4I for qemu-devel@nongnu.org; Fri, 29 Jun 2018 07:17:04 -0400 Received: from foss.arm.com ([217.140.101.70]:39506) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYrOg-0002sj-UT for qemu-devel@nongnu.org; Fri, 29 Jun 2018 07:17:03 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 33F7919BF; Fri, 29 Jun 2018 04:17:02 -0700 (PDT) Received: from en101.cambridge.arm.com (en101.cambridge.arm.com [10.1.206.73]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id AD47D3F266; Fri, 29 Jun 2018 04:16:59 -0700 (PDT) From: Suzuki K Poulose To: linux-arm-kernel@lists.infradead.org Date: Fri, 29 Jun 2018 12:15:38 +0100 Message-Id: <1530270944-11351-19-git-send-email-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1530270944-11351-1-git-send-email-suzuki.poulose@arm.com> References: <1530270944-11351-1-git-send-email-suzuki.poulose@arm.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 217.140.101.70 Subject: [Qemu-devel] [PATCH v3 18/20] kvm: arm64: Add support for handling 52bit IPA X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cdall@kernel.org, kvm@vger.kernel.org, Suzuki K Poulose , marc.zyngier@arm.com, catalin.marinas@arm.com, punit.agrawal@arm.com, will.deacon@arm.com, linux-kernel@vger.kernel.org, Kristina Martsenko , qemu-devel@nongnu.org, eric.auger@redhat.com, julien.grall@arm.com, james.morse@arm.com, kvmarm@lists.cs.columbia.edu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add support for handling the 52bit IPA. 52bit IPA support needs changes to the following : 1) Page-table entries - We use kernel page table helpers for setting up the stage2. Hence we don't explicit changes here 2) VTTBR:BADDR - This is already supported with : commit 529c4b05a3cb2f324aa ("arm64: handle 52-bit addresses in TTBR") 3) VGIC support for 52bit: Supported with a patch in this series. That leaves us with the handling for PAR and HPAR. This patch adds support for handling the 52bit addresses in PAR and HPFAR, which are used while handling the permission faults in stage1. Cc: Marc Zyngier Cc: Kristina Martsenko Cc: Christoffer Dall Signed-off-by: Suzuki K Poulose Acked-by: Marc Zyngier --- arch/arm64/include/asm/kvm_arm.h | 7 +++++++ arch/arm64/kvm/hyp/switch.c | 2 +- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_= arm.h index 2e90942..cb6a2ee 100644 --- a/arch/arm64/include/asm/kvm_arm.h +++ b/arch/arm64/include/asm/kvm_arm.h @@ -301,6 +301,13 @@ =20 /* Hyp Prefetch Fault Address Register (HPFAR/HDFAR) */ #define HPFAR_MASK (~UL(0xf)) +/* + * We have + * PAR [PA_Shift - 1 : 12] =3D PA [PA_Shift - 1 : 12] + * HPFAR [PA_Shift - 9 : 4] =3D FIPA [PA_Shift - 1 : 12] + */ +#define PAR_TO_HPFAR(par) \ + (((par) & GENMASK_ULL(PHYS_MASK_SHIFT - 1, 12)) >> 8) =20 #define kvm_arm_exception_type \ {0, "IRQ" }, \ diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp/switch.c index 355fb25..fb66320 100644 --- a/arch/arm64/kvm/hyp/switch.c +++ b/arch/arm64/kvm/hyp/switch.c @@ -260,7 +260,7 @@ static bool __hyp_text __translate_far_to_hpfar(u64 far= , u64 *hpfar) return false; /* Translation failed, back to guest */ =20 /* Convert PAR to HPFAR format */ - *hpfar =3D ((tmp >> 12) & ((1UL << 36) - 1)) << 4; + *hpfar =3D PAR_TO_HPFAR(tmp); return true; } =20 --=20 2.7.4 From nobody Mon Feb 9 15:13:28 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530271998521660.7494512158984; Fri, 29 Jun 2018 04:33:18 -0700 (PDT) Received: from localhost ([::1]:41291 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYreK-0005aC-3R for importer@patchew.org; Fri, 29 Jun 2018 07:33:12 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36705) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYrOl-0000OQ-1J for qemu-devel@nongnu.org; Fri, 29 Jun 2018 07:17:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fYrOj-0002zB-PB for qemu-devel@nongnu.org; Fri, 29 Jun 2018 07:17:07 -0400 Received: from foss.arm.com ([217.140.101.70]:39524) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYrOj-0002xZ-Es for qemu-devel@nongnu.org; Fri, 29 Jun 2018 07:17:05 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C94261529; Fri, 29 Jun 2018 04:17:04 -0700 (PDT) Received: from en101.cambridge.arm.com (en101.cambridge.arm.com [10.1.206.73]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 71C453F266; Fri, 29 Jun 2018 04:17:02 -0700 (PDT) From: Suzuki K Poulose To: linux-arm-kernel@lists.infradead.org Date: Fri, 29 Jun 2018 12:15:39 +0100 Message-Id: <1530270944-11351-20-git-send-email-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1530270944-11351-1-git-send-email-suzuki.poulose@arm.com> References: <1530270944-11351-1-git-send-email-suzuki.poulose@arm.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 217.140.101.70 Subject: [Qemu-devel] [PATCH v3 19/20] kvm: arm64: Allow IPA size supported by the system X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cdall@kernel.org, kvm@vger.kernel.org, Suzuki K Poulose , marc.zyngier@arm.com, catalin.marinas@arm.com, punit.agrawal@arm.com, will.deacon@arm.com, linux-kernel@vger.kernel.org, qemu-devel@nongnu.org, eric.auger@redhat.com, julien.grall@arm.com, james.morse@arm.com, kvmarm@lists.cs.columbia.edu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" So far we have restricted the IPA size of the VM to the default value (40bits). Now that we can manage the IPA size per VM and support dynamic stage2 page tables, allow VMs to have larger IPA. This is done by setting the IPA limit to the one supported by the hardware and kernel. This patch also moves the check for the default IPA size support to kvm_get_ipa_limit(). Since the stage2 page table code is dependent on the stage1 page table, we always ensure that : Number of Levels at Stage1 >=3D Number of Levels at Stage2 So we limit the IPA to make sure that the above condition is satisfied. This will affect the following combinations of VA_BITS and IPA for different page sizes. 39bit VA, 4K - IPA > 43 (Upto 48) 36bit VA, 16K - IPA > 40 (Upto 48) 42bit VA, 64K - IPA > 46 (Upto 52) Supporting the above combinations need independent stage2 page table manipulation code, which would need substantial changes. We could purse the solution independently and switch the page table code once we have it ready. Cc: Catalin Marinas Cc: Marc Zyngier Cc: Christoffer Dall Signed-off-by: Suzuki K Poulose --- Changes since V2: - Restrict the IPA size to limit the number of page table levels in stage2 to that of stage1 or less. --- arch/arm64/include/asm/kvm_host.h | 6 ------ arch/arm64/include/asm/kvm_mmu.h | 37 +++++++++++++++++++++++++++++++++++= +- 2 files changed, 36 insertions(+), 7 deletions(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index 9a15860..e858e49 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -452,13 +452,7 @@ int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu, =20 static inline void __cpu_init_stage2(void) { - u32 ps; - kvm_call_hyp(__init_stage2_translation); - /* Sanity check for minimum IPA size support */ - ps =3D id_aa64mmfr0_parange_to_phys_shift(read_sysreg(id_aa64mmfr0_el1) &= 0x7); - WARN_ONCE(ps < 40, - "PARange is %d bits, unsupported configuration!", ps); } =20 /* Guest/host FPSIMD coordination helpers */ diff --git a/arch/arm64/include/asm/kvm_mmu.h b/arch/arm64/include/asm/kvm_= mmu.h index a291cdc..d38f395 100644 --- a/arch/arm64/include/asm/kvm_mmu.h +++ b/arch/arm64/include/asm/kvm_mmu.h @@ -547,7 +547,42 @@ static inline void *stage2_alloc_pgd(struct kvm *kvm) =20 static inline u32 kvm_get_ipa_limit(void) { - return KVM_PHYS_SHIFT; + unsigned int ipa_max, va_max, parange; + + parange =3D read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1) & 0x7; + ipa_max =3D id_aa64mmfr0_parange_to_phys_shift(parange); + + /* Raise the limit to the default size for backward compatibility */ + if (ipa_max < KVM_PHYS_SHIFT) { + WARN_ONCE(1, + "PARange is %d bits, unsupported configuration!", + ipa_max); + ipa_max =3D KVM_PHYS_SHIFT; + } + + /* Clamp it to the PA size supported by the kernel */ + ipa_max =3D (ipa_max > PHYS_MASK_SHIFT) ? PHYS_MASK_SHIFT : ipa_max; + /* + * Since our stage2 table is dependent on the stage1 page table code, + * we must always honor the following condition: + * + * Number of levels in Stage1 >=3D Number of levels in Stage2. + * + * So clamp the ipa limit further down to limit the number of levels. + * Since we can concatenate upto 16 tables at entry level, we could + * go upto 4bits above the maximum VA addressible with the current + * number of levels. + */ + va_max =3D PGDIR_SHIFT + PAGE_SHIFT - 3; + va_max +=3D 4; + + if (va_max < ipa_max) { + kvm_info("Limiting IPA limit to %dbytes due to host VA bits limitation\n= ", + va_max); + ipa_max =3D va_max; + } + + return ipa_max; } =20 static inline void kvm_config_stage2(struct kvm *kvm, u32 ipa_shift) --=20 2.7.4 From nobody Mon Feb 9 15:13:28 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530271809986915.316641804035; Fri, 29 Jun 2018 04:30:09 -0700 (PDT) Received: from localhost ([::1]:41272 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYrbN-0002Zl-3i for importer@patchew.org; Fri, 29 Jun 2018 07:30:09 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36723) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYrOn-0000Qa-I7 for qemu-devel@nongnu.org; Fri, 29 Jun 2018 07:17:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fYrOm-00032A-94 for qemu-devel@nongnu.org; Fri, 29 Jun 2018 07:17:09 -0400 Received: from foss.arm.com ([217.140.101.70]:39544) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYrOl-00031d-Vc for qemu-devel@nongnu.org; Fri, 29 Jun 2018 07:17:08 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 69DB415AD; Fri, 29 Jun 2018 04:17:07 -0700 (PDT) Received: from en101.cambridge.arm.com (en101.cambridge.arm.com [10.1.206.73]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 12B433F266; Fri, 29 Jun 2018 04:17:04 -0700 (PDT) From: Suzuki K Poulose To: linux-arm-kernel@lists.infradead.org Date: Fri, 29 Jun 2018 12:15:40 +0100 Message-Id: <1530270944-11351-21-git-send-email-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1530270944-11351-1-git-send-email-suzuki.poulose@arm.com> References: <1530270944-11351-1-git-send-email-suzuki.poulose@arm.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 217.140.101.70 Subject: [Qemu-devel] [PATCH v3 20/20] kvm: arm64: Fall back to normal stage2 entry level X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cdall@kernel.org, kvm@vger.kernel.org, Suzuki K Poulose , marc.zyngier@arm.com, catalin.marinas@arm.com, punit.agrawal@arm.com, will.deacon@arm.com, linux-kernel@vger.kernel.org, qemu-devel@nongnu.org, eric.auger@redhat.com, julien.grall@arm.com, james.morse@arm.com, kvmarm@lists.cs.columbia.edu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We use concatenated entry level page tables (upto 16tables) for stage2. If we don't have sufficient contiguous pages (e.g, 16 * 64K), fallback to the normal page table format, by going one level deeper if permitted. Cc: Marc Zyngier Cc: Christoffer Dall Signed-off-by: Suzuki K Poulose --- New in v3 --- arch/arm64/include/asm/kvm_arm.h | 7 +++++++ arch/arm64/include/asm/kvm_mmu.h | 18 +---------------- arch/arm64/kvm/guest.c | 42 ++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 50 insertions(+), 17 deletions(-) diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_= arm.h index cb6a2ee..42eb528 100644 --- a/arch/arm64/include/asm/kvm_arm.h +++ b/arch/arm64/include/asm/kvm_arm.h @@ -137,6 +137,8 @@ * * VTCR_EL2.SL0 and T0SZ are configured per VM at runtime before switching= to * the VM. + * + * With 16k/64k, the maximum number of levels supported at Stage2 is 3. */ =20 #define VTCR_EL2_COMMON_BITS (VTCR_EL2_SH0_INNER | VTCR_EL2_ORGN0_WBWA | \ @@ -150,6 +152,7 @@ */ #define VTCR_EL2_TGRAN VTCR_EL2_TG0_64K #define VTCR_EL2_TGRAN_SL0_BASE 3UL +#define ARM64_TGRAN_STAGE2_MAX_LEVELS 3 =20 #elif defined(CONFIG_ARM64_16K_PAGES) /* @@ -158,6 +161,8 @@ */ #define VTCR_EL2_TGRAN VTCR_EL2_TG0_16K #define VTCR_EL2_TGRAN_SL0_BASE 3UL +#define ARM64_TGRAN_STAGE2_MAX_LEVELS 3 + #else /* 4K */ /* * Stage2 translation configuration: @@ -165,6 +170,8 @@ */ #define VTCR_EL2_TGRAN VTCR_EL2_TG0_4K #define VTCR_EL2_TGRAN_SL0_BASE 2UL +#define ARM64_TGRAN_STAGE2_MAX_LEVELS 4 + #endif =20 #define VTCR_EL2_FLAGS (VTCR_EL2_COMMON_BITS | VTCR_EL2_TGRAN) diff --git a/arch/arm64/include/asm/kvm_mmu.h b/arch/arm64/include/asm/kvm_= mmu.h index d38f395..50f632e 100644 --- a/arch/arm64/include/asm/kvm_mmu.h +++ b/arch/arm64/include/asm/kvm_mmu.h @@ -527,23 +527,7 @@ static inline u64 kvm_vttbr_baddr_mask(struct kvm *kvm) return vttbr_baddr_mask(kvm_phys_shift(kvm), kvm_stage2_levels(kvm)); } =20 -static inline void *stage2_alloc_pgd(struct kvm *kvm) -{ - u32 ipa, lvls; - - /* - * Stage2 page table can support concatenation of (upto 16) tables - * at the entry level, thereby reducing the number of levels. - */ - ipa =3D kvm_phys_shift(kvm); - lvls =3D stage2_pt_levels(ipa); - - kvm->arch.s2_levels =3D lvls; - kvm->arch.vtcr_private =3D VTCR_EL2_SL0(lvls) | TCR_T0SZ(ipa); - - return alloc_pages_exact(stage2_pgd_size(kvm), - GFP_KERNEL | __GFP_ZERO); -} +extern void *stage2_alloc_pgd(struct kvm *kvm); =20 static inline u32 kvm_get_ipa_limit(void) { diff --git a/arch/arm64/kvm/guest.c b/arch/arm64/kvm/guest.c index 56a0260..5a3a687 100644 --- a/arch/arm64/kvm/guest.c +++ b/arch/arm64/kvm/guest.c @@ -31,6 +31,8 @@ #include #include #include +#include +#include =20 #include "trace.h" =20 @@ -458,3 +460,43 @@ int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu, =20 return ret; } + +void *stage2_alloc_pgd(struct kvm *kvm) +{ + u32 ipa, s2_lvls, lvls; + u64 pgd_size; + void *pgd; + + /* + * Stage2 page table can support concatenation of (upto 16) tables + * at the entry level, thereby reducing the number of levels. We try + * to use concatenation wherever possible. If we fail, fallback to + * normal levels if possible. + */ + ipa =3D kvm_phys_shift(kvm); + lvls =3D s2_lvls =3D stage2_pt_levels(ipa); + +retry: + pgd_size =3D __s2_pgd_size(ipa, lvls); + pgd =3D alloc_pages_exact(pgd_size, GFP_KERNEL | __GFP_ZERO); + + /* Check if the PGD meets the alignment requirements */ + if (pgd && (virt_to_phys(pgd) & ~vttbr_baddr_mask(ipa, lvls))) { + free_pages_exact(pgd, pgd_size); + pgd =3D NULL; + } + + if (pgd) { + kvm->arch.s2_levels =3D lvls; + kvm->arch.vtcr_private =3D VTCR_EL2_SL0(lvls) | TCR_T0SZ(ipa); + } else { + /* Check if we can use an entry level without concatenation */ + lvls =3D ARM64_HW_PGTABLE_LEVELS(ipa); + if ((lvls > s2_lvls) && + (lvls <=3D CONFIG_PGTABLE_LEVELS) && + (lvls <=3D ARM64_TGRAN_STAGE2_MAX_LEVELS)) + goto retry; + } + + return pgd; +} --=20 2.7.4 From nobody Mon Feb 9 15:13:28 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530272189425774.9011050664905; Fri, 29 Jun 2018 04:36:29 -0700 (PDT) Received: from localhost ([::1]:41309 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYrhU-0008UI-ML for importer@patchew.org; Fri, 29 Jun 2018 07:36:28 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36787) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYrOs-0000TK-I4 for qemu-devel@nongnu.org; Fri, 29 Jun 2018 07:17:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fYrOo-00034P-US for qemu-devel@nongnu.org; Fri, 29 Jun 2018 07:17:14 -0400 Received: from foss.arm.com ([217.140.101.70]:39564) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYrOo-00033s-N7 for qemu-devel@nongnu.org; Fri, 29 Jun 2018 07:17:10 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1339A1684; Fri, 29 Jun 2018 04:17:10 -0700 (PDT) Received: from en101.cambridge.arm.com (en101.cambridge.arm.com [10.1.206.73]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id A78903F266; Fri, 29 Jun 2018 04:17:07 -0700 (PDT) From: Suzuki K Poulose To: linux-arm-kernel@lists.infradead.org Date: Fri, 29 Jun 2018 12:15:41 +0100 Message-Id: <1530270944-11351-22-git-send-email-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1530270944-11351-1-git-send-email-suzuki.poulose@arm.com> References: <1530270944-11351-1-git-send-email-suzuki.poulose@arm.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 217.140.101.70 Subject: [Qemu-devel] [kvmtool test PATCH 21/24] kvmtool: Allow backends to run checks on the KVM device fd X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cdall@kernel.org, kvm@vger.kernel.org, Suzuki K Poulose , marc.zyngier@arm.com, catalin.marinas@arm.com, punit.agrawal@arm.com, will.deacon@arm.com, linux-kernel@vger.kernel.org, qemu-devel@nongnu.org, eric.auger@redhat.com, julien.grall@arm.com, james.morse@arm.com, kvmarm@lists.cs.columbia.edu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Allow architectures to perform initialisation based on the KVM device fd ioctls, even before the VM is created. Signed-off-by: Suzuki K Poulose --- include/kvm/kvm.h | 4 ++++ kvm.c | 2 ++ 2 files changed, 6 insertions(+) diff --git a/include/kvm/kvm.h b/include/kvm/kvm.h index 90463b8..a036dd2 100644 --- a/include/kvm/kvm.h +++ b/include/kvm/kvm.h @@ -103,6 +103,10 @@ int kvm__get_sock_by_instance(const char *name); int kvm__enumerate_instances(int (*callback)(const char *name, int pid)); void kvm__remove_socket(const char *name); =20 +#ifndef kvm__arch_init_hyp +static inline void kvm__arch_init_hyp(struct kvm *kvm) {} +#endif + void kvm__arch_set_cmdline(char *cmdline, bool video); void kvm__arch_init(struct kvm *kvm, const char *hugetlbfs_path, u64 ram_s= ize); void kvm__arch_delete_ram(struct kvm *kvm); diff --git a/kvm.c b/kvm.c index f8f2fdc..b992e74 100644 --- a/kvm.c +++ b/kvm.c @@ -304,6 +304,8 @@ int kvm__init(struct kvm *kvm) goto err_sys_fd; } =20 + kvm__arch_init_hyp(kvm); + kvm->vm_fd =3D ioctl(kvm->sys_fd, KVM_CREATE_VM, KVM_VM_TYPE); if (kvm->vm_fd < 0) { pr_err("KVM_CREATE_VM ioctl"); --=20 2.7.4 From nobody Mon Feb 9 15:13:28 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530271867666486.5322772752703; Fri, 29 Jun 2018 04:31:07 -0700 (PDT) Received: from localhost ([::1]:41280 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYrcI-0003S0-Pa for importer@patchew.org; Fri, 29 Jun 2018 07:31:06 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36789) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYrOs-0000TL-J1 for qemu-devel@nongnu.org; Fri, 29 Jun 2018 07:17:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fYrOr-00036N-FD for qemu-devel@nongnu.org; Fri, 29 Jun 2018 07:17:14 -0400 Received: from foss.arm.com ([217.140.101.70]:39578) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYrOr-00035m-98 for qemu-devel@nongnu.org; Fri, 29 Jun 2018 07:17:13 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id AA68915AD; Fri, 29 Jun 2018 04:17:12 -0700 (PDT) Received: from en101.cambridge.arm.com (en101.cambridge.arm.com [10.1.206.73]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 535DB3F266; Fri, 29 Jun 2018 04:17:10 -0700 (PDT) From: Suzuki K Poulose To: linux-arm-kernel@lists.infradead.org Date: Fri, 29 Jun 2018 12:15:42 +0100 Message-Id: <1530270944-11351-23-git-send-email-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1530270944-11351-1-git-send-email-suzuki.poulose@arm.com> References: <1530270944-11351-1-git-send-email-suzuki.poulose@arm.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 217.140.101.70 Subject: [Qemu-devel] [kvmtool test PATCH 22/24] kvmtool: arm64: Add support for guest physical address size X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cdall@kernel.org, kvm@vger.kernel.org, Suzuki K Poulose , marc.zyngier@arm.com, catalin.marinas@arm.com, punit.agrawal@arm.com, will.deacon@arm.com, linux-kernel@vger.kernel.org, qemu-devel@nongnu.org, eric.auger@redhat.com, julien.grall@arm.com, james.morse@arm.com, kvmarm@lists.cs.columbia.edu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add an option to specify the physical address size used by this VM. Signed-off-by: Suzuki K Poulose --- arm/aarch64/include/kvm/kvm-config-arch.h | 5 ++++- arm/include/arm-common/kvm-config-arch.h | 1 + 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/arm/aarch64/include/kvm/kvm-config-arch.h b/arm/aarch64/includ= e/kvm/kvm-config-arch.h index 04be43d..dabd22c 100644 --- a/arm/aarch64/include/kvm/kvm-config-arch.h +++ b/arm/aarch64/include/kvm/kvm-config-arch.h @@ -8,7 +8,10 @@ "Create PMUv3 device"), \ OPT_U64('\0', "kaslr-seed", &(cfg)->kaslr_seed, \ "Specify random seed for Kernel Address Space " \ - "Layout Randomization (KASLR)"), + "Layout Randomization (KASLR)"), \ + OPT_INTEGER('\0', "phys-shift", &(cfg)->phys_shift, \ + "Specify maximum physical address size (not " \ + "the amount of memory)"), =20 #include "arm-common/kvm-config-arch.h" =20 diff --git a/arm/include/arm-common/kvm-config-arch.h b/arm/include/arm-com= mon/kvm-config-arch.h index 6a196f1..e0b531e 100644 --- a/arm/include/arm-common/kvm-config-arch.h +++ b/arm/include/arm-common/kvm-config-arch.h @@ -11,6 +11,7 @@ struct kvm_config_arch { bool has_pmuv3; u64 kaslr_seed; enum irqchip_type irqchip; + int phys_shift; }; =20 int irqchip_parser(const struct option *opt, const char *arg, int unset); --=20 2.7.4 From nobody Mon Feb 9 15:13:28 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530272171062815.3255969582514; Fri, 29 Jun 2018 04:36:11 -0700 (PDT) Received: from localhost ([::1]:41307 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYrhC-0008H1-6G for importer@patchew.org; Fri, 29 Jun 2018 07:36:10 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36813) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYrOv-0000TN-0C for qemu-devel@nongnu.org; Fri, 29 Jun 2018 07:17:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fYrOt-00038p-W4 for qemu-devel@nongnu.org; Fri, 29 Jun 2018 07:17:16 -0400 Received: from foss.arm.com ([217.140.101.70]:39596) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYrOt-00037x-PD for qemu-devel@nongnu.org; Fri, 29 Jun 2018 07:17:15 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4B9CF15AD; Fri, 29 Jun 2018 04:17:15 -0700 (PDT) Received: from en101.cambridge.arm.com (en101.cambridge.arm.com [10.1.206.73]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id E808F3F266; Fri, 29 Jun 2018 04:17:12 -0700 (PDT) From: Suzuki K Poulose To: linux-arm-kernel@lists.infradead.org Date: Fri, 29 Jun 2018 12:15:43 +0100 Message-Id: <1530270944-11351-24-git-send-email-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1530270944-11351-1-git-send-email-suzuki.poulose@arm.com> References: <1530270944-11351-1-git-send-email-suzuki.poulose@arm.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 217.140.101.70 Subject: [Qemu-devel] [kvmtool test PATCH 23/24] kvmtool: arm64: Switch memory layout X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cdall@kernel.org, kvm@vger.kernel.org, Suzuki K Poulose , marc.zyngier@arm.com, catalin.marinas@arm.com, punit.agrawal@arm.com, will.deacon@arm.com, linux-kernel@vger.kernel.org, qemu-devel@nongnu.org, eric.auger@redhat.com, julien.grall@arm.com, james.morse@arm.com, kvmarm@lists.cs.columbia.edu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" If the guest wants to use a larger physical address space place the RAM at upper half of the address space. Otherwise, it uses the default layout. Signed-off-by: Suzuki K Poulose --- arm/aarch32/include/kvm/kvm-arch.h | 6 ++++-- arm/aarch64/include/kvm/kvm-arch.h | 15 ++++++++++++--- arm/include/arm-common/kvm-arch.h | 11 ++++++----- arm/kvm.c | 2 +- 4 files changed, 23 insertions(+), 11 deletions(-) diff --git a/arm/aarch32/include/kvm/kvm-arch.h b/arm/aarch32/include/kvm/k= vm-arch.h index cd31e72..bcd382b 100644 --- a/arm/aarch32/include/kvm/kvm-arch.h +++ b/arm/aarch32/include/kvm/kvm-arch.h @@ -3,8 +3,10 @@ =20 #define ARM_KERN_OFFSET(...) 0x8000 =20 -#define ARM_MAX_MEMORY(...) ARM_LOMAP_MAX_MEMORY - #include "arm-common/kvm-arch.h" =20 +#define ARM_MAX_MEMORY(...) ARM32_MAX_MEMORY +#define ARM_MEMORY_AREA(...) ARM32_MEMORY_AREA + + #endif /* KVM__KVM_ARCH_H */ diff --git a/arm/aarch64/include/kvm/kvm-arch.h b/arm/aarch64/include/kvm/k= vm-arch.h index 9de623a..bad35b9 100644 --- a/arm/aarch64/include/kvm/kvm-arch.h +++ b/arm/aarch64/include/kvm/kvm-arch.h @@ -1,14 +1,23 @@ #ifndef KVM__KVM_ARCH_H #define KVM__KVM_ARCH_H =20 +#include "arm-common/kvm-arch.h" + +#define ARM64_MEMORY_AREA(phys_shift) (1UL << (phys_shift - 1)) +#define ARM64_MAX_MEMORY(phys_shift) \ + ((1ULL << (phys_shift)) - ARM64_MEMORY_AREA(phys_shift)) + +#define ARM_MEMORY_AREA(kvm) ((kvm)->cfg.arch.aarch32_guest ? \ + ARM32_MEMORY_AREA : \ + ARM64_MEMORY_AREA(kvm->cfg.arch.phys_shift)) + #define ARM_KERN_OFFSET(kvm) ((kvm)->cfg.arch.aarch32_guest ? \ 0x8000 : \ 0x80000) =20 #define ARM_MAX_MEMORY(kvm) ((kvm)->cfg.arch.aarch32_guest ? \ - ARM_LOMAP_MAX_MEMORY : \ - ARM_HIMAP_MAX_MEMORY) + ARM32_MAX_MEMORY : \ + ARM64_MAX_MEMORY(kvm->cfg.arch.phys_shift)) =20 -#include "arm-common/kvm-arch.h" =20 #endif /* KVM__KVM_ARCH_H */ diff --git a/arm/include/arm-common/kvm-arch.h b/arm/include/arm-common/kvm= -arch.h index b9d486d..b29b4b1 100644 --- a/arm/include/arm-common/kvm-arch.h +++ b/arm/include/arm-common/kvm-arch.h @@ -6,14 +6,15 @@ #include =20 #include "arm-common/gic.h" - #define ARM_IOPORT_AREA _AC(0x0000000000000000, UL) #define ARM_MMIO_AREA _AC(0x0000000000010000, UL) #define ARM_AXI_AREA _AC(0x0000000040000000, UL) -#define ARM_MEMORY_AREA _AC(0x0000000080000000, UL) =20 -#define ARM_LOMAP_MAX_MEMORY ((1ULL << 32) - ARM_MEMORY_AREA) -#define ARM_HIMAP_MAX_MEMORY ((1ULL << 40) - ARM_MEMORY_AREA) +#define ARM32_MEMORY_AREA _AC(0x0000000080000000, UL) +#define ARM32_MAX_MEMORY ((1ULL << 32) - ARM32_MEMORY_AREA) + +#define ARM_IOMEM_AREA_END ARM32_MEMORY_AREA + =20 #define ARM_GIC_DIST_BASE (ARM_AXI_AREA - ARM_GIC_DIST_SIZE) #define ARM_GIC_CPUI_BASE (ARM_GIC_DIST_BASE - ARM_GIC_CPUI_SIZE) @@ -24,7 +25,7 @@ #define ARM_IOPORT_SIZE (ARM_MMIO_AREA - ARM_IOPORT_AREA) #define ARM_VIRTIO_MMIO_SIZE (ARM_AXI_AREA - (ARM_MMIO_AREA + ARM_GIC_SIZE= )) #define ARM_PCI_CFG_SIZE (1ULL << 24) -#define ARM_PCI_MMIO_SIZE (ARM_MEMORY_AREA - \ +#define ARM_PCI_MMIO_SIZE (ARM_IOMEM_AREA_END - \ (ARM_AXI_AREA + ARM_PCI_CFG_SIZE)) =20 #define KVM_IOPORT_AREA ARM_IOPORT_AREA diff --git a/arm/kvm.c b/arm/kvm.c index 2ab436e..5701d41 100644 --- a/arm/kvm.c +++ b/arm/kvm.c @@ -30,7 +30,7 @@ void kvm__init_ram(struct kvm *kvm) u64 phys_start, phys_size; void *host_mem; =20 - phys_start =3D ARM_MEMORY_AREA; + phys_start =3D ARM_MEMORY_AREA(kvm); phys_size =3D kvm->ram_size; host_mem =3D kvm->ram_start; =20 --=20 2.7.4 From nobody Mon Feb 9 15:13:28 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530272000571611.7428687031339; Fri, 29 Jun 2018 04:33:20 -0700 (PDT) Received: from localhost ([::1]:41290 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYreI-0005Yi-M9 for importer@patchew.org; Fri, 29 Jun 2018 07:33:10 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36847) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYrOx-0000VU-PM for qemu-devel@nongnu.org; Fri, 29 Jun 2018 07:17:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fYrOw-0003CV-PX for qemu-devel@nongnu.org; Fri, 29 Jun 2018 07:17:19 -0400 Received: from foss.arm.com ([217.140.101.70]:39614) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYrOw-0003Br-Ih for qemu-devel@nongnu.org; Fri, 29 Jun 2018 07:17:18 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E1E91168F; Fri, 29 Jun 2018 04:17:17 -0700 (PDT) Received: from en101.cambridge.arm.com (en101.cambridge.arm.com [10.1.206.73]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 8ADA13F266; Fri, 29 Jun 2018 04:17:15 -0700 (PDT) From: Suzuki K Poulose To: linux-arm-kernel@lists.infradead.org Date: Fri, 29 Jun 2018 12:15:44 +0100 Message-Id: <1530270944-11351-25-git-send-email-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1530270944-11351-1-git-send-email-suzuki.poulose@arm.com> References: <1530270944-11351-1-git-send-email-suzuki.poulose@arm.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 217.140.101.70 Subject: [Qemu-devel] [kvmtool test PATCH 24/24] kvmtool: arm: Add support for creating VM with PA size X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cdall@kernel.org, kvm@vger.kernel.org, Suzuki K Poulose , marc.zyngier@arm.com, catalin.marinas@arm.com, punit.agrawal@arm.com, will.deacon@arm.com, linux-kernel@vger.kernel.org, qemu-devel@nongnu.org, eric.auger@redhat.com, julien.grall@arm.com, james.morse@arm.com, kvmarm@lists.cs.columbia.edu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Specify the physical size for the VM encoded in the vm type. Signed-off-by: Suzuki K Poulose --- arm/include/arm-common/kvm-arch.h | 6 +++++- arm/kvm.c | 22 ++++++++++++++++++++++ 2 files changed, 27 insertions(+), 1 deletion(-) diff --git a/arm/include/arm-common/kvm-arch.h b/arm/include/arm-common/kvm= -arch.h index b29b4b1..d77f3ac 100644 --- a/arm/include/arm-common/kvm-arch.h +++ b/arm/include/arm-common/kvm-arch.h @@ -44,7 +44,11 @@ =20 #define KVM_IRQ_OFFSET GIC_SPI_IRQ_BASE =20 -#define KVM_VM_TYPE 0 +extern unsigned long kvm_arm_type; +extern void kvm__arch_init_hyp(struct kvm *kvm); + +#define KVM_VM_TYPE kvm_arm_type +#define kvm__arch_init_hyp kvm__arch_init_hyp =20 #define VIRTIO_DEFAULT_TRANS(kvm) \ ((kvm)->cfg.arch.virtio_trans_pci ? VIRTIO_PCI : VIRTIO_MMIO) diff --git a/arm/kvm.c b/arm/kvm.c index 5701d41..b1969be 100644 --- a/arm/kvm.c +++ b/arm/kvm.c @@ -11,6 +11,8 @@ #include #include =20 +unsigned long kvm_arm_type; + struct kvm_ext kvm_req_ext[] =3D { { DEFINE_KVM_EXT(KVM_CAP_IRQCHIP) }, { DEFINE_KVM_EXT(KVM_CAP_ONE_REG) }, @@ -18,6 +20,26 @@ struct kvm_ext kvm_req_ext[] =3D { { 0, 0 }, }; =20 +#ifndef KVM_ARM_GET_MAX_VM_PHYS_SHIFT +#define KVM_ARM_GET_MAX_VM_PHYS_SHIFT _IO(KVMIO, 0x0b) +#endif + +void kvm__arch_init_hyp(struct kvm *kvm) +{ + int max_ipa; + + max_ipa =3D ioctl(kvm->sys_fd, KVM_ARM_GET_MAX_VM_PHYS_SHIFT); + if (max_ipa < 0) + max_ipa =3D 40; + if (!kvm->cfg.arch.phys_shift) + kvm->cfg.arch.phys_shift =3D 40; + if (kvm->cfg.arch.phys_shift > max_ipa) + die("Requested PA size (%u) is not supported by the host (%ubits)\n", + kvm->cfg.arch.phys_shift, max_ipa); + if (kvm->cfg.arch.phys_shift !=3D 40) + kvm_arm_type =3D kvm->cfg.arch.phys_shift; +} + bool kvm__arch_cpu_supports_vm(void) { /* The KVM capability check is enough. */ --=20 2.7.4