From nobody Tue Nov 4 15:13:15 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1530177680281618.7976062462747; Thu, 28 Jun 2018 02:21:20 -0700 (PDT) Received: from localhost ([::1]:35216 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYT79-0007nl-Ir for importer@patchew.org; Thu, 28 Jun 2018 05:21:19 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47291) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYT3v-0005vo-DP for qemu-devel@nongnu.org; Thu, 28 Jun 2018 05:18:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fYT3u-0006G5-3R for qemu-devel@nongnu.org; Thu, 28 Jun 2018 05:17:59 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:2629 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fYT3p-00062Z-80; Thu, 28 Jun 2018 05:17:53 -0400 Received: from DGGEMS413-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 6C5095C7C38EF; Thu, 28 Jun 2018 17:17:33 +0800 (CST) Received: from localhost.localdomain (10.143.28.90) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.382.0; Thu, 28 Jun 2018 17:17:25 +0800 From: Dongjiu Geng To: , , , , , , Date: Fri, 29 Jun 2018 01:22:41 +0800 Message-ID: <1530206561-22348-3-git-send-email-gengdongjiu@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1530206561-22348-1-git-send-email-gengdongjiu@huawei.com> References: <1530206561-22348-1-git-send-email-gengdongjiu@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.143.28.90] X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 45.249.212.190 Subject: [Qemu-devel] [PATCH v4 RFC 2/2] target: arm: Add support for VCPU event states X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This patch extends the qemu-kvm state sync logic with support for KVM_GET/SET_VCPU_EVENTS, giving access to yet missing SError exception. And also it can support the exception state migration. Signed-off-by: Dongjiu Geng --- change since v3: 1. Add a new new subsection with a suitable 'ras_needed' function controlling whether it is present 2. Add a ARM_FEATURE_RAS feature bit for CPUARMState The corresponding kernel patch is here: https://lkml.org/lkml/2018/6/25/374 --- target/arm/cpu.h | 6 ++++++ target/arm/kvm64.c | 59 ++++++++++++++++++++++++++++++++++++++++++++++++= ++++ target/arm/machine.c | 22 ++++++++++++++++++++ 3 files changed, 87 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 8488273..575c46c 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -645,6 +645,11 @@ typedef struct CPUARMState { const struct arm_boot_info *boot_info; /* Store GICv3CPUState to access from this struct */ void *gicv3state; + struct { + uint32_t pending; + uint32_t has_esr; + uint64_t esr; + } serror; } CPUARMState; =20 /** @@ -1482,6 +1487,7 @@ enum arm_features { ARM_FEATURE_V8_RDM, /* implements v8.1 simd round multiply */ ARM_FEATURE_V8_FP16, /* implements v8.2 half-precision float */ ARM_FEATURE_V8_FCMA, /* has complex number part of v8.3 extensions. */ + ARM_FEATURE_RAS, /* has RAS Extension */ }; =20 static inline int arm_feature(CPUARMState *env, int feature) diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index e0b8246..660b358 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -527,6 +527,10 @@ int kvm_arch_init_vcpu(CPUState *cs) unset_feature(&env->features, ARM_FEATURE_PMU); } =20 + if (kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_INJECT_SERROR_ESR))= { + set_feature(&env->features, ARM_FEATURE_RAS); + } + /* Do KVM_ARM_VCPU_INIT ioctl */ ret =3D kvm_arm_vcpu_init(cs); if (ret) { @@ -600,6 +604,50 @@ int kvm_arm_cpreg_level(uint64_t regidx) #define AARCH64_SIMD_CTRL_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U32 | \ KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x)) =20 +static int kvm_put_vcpu_events(ARMCPU *cpu) +{ + CPUARMState *env =3D &cpu->env; + struct kvm_vcpu_events events =3D {}; + + if (!kvm_has_vcpu_events()) { + return 0; + } + + memset(&events, 0, sizeof(events)); + events.exception.serror_pending =3D env->serror.pending; + + if (arm_feature(env, ARM_FEATURE_RAS)) { + events.exception.serror_has_esr =3D env->serror.has_esr; + events.exception.serror_esr =3D env->serror.esr; + } + + return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events); +} + +static int kvm_get_vcpu_events(ARMCPU *cpu) +{ + CPUARMState *env =3D &cpu->env; + struct kvm_vcpu_events events; + int ret; + + if (!kvm_has_vcpu_events()) { + return 0; + } + + memset(&events, 0, sizeof(events)); + ret =3D kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events); + + if (ret < 0) { + return ret; + } + + env->serror.pending =3D events.exception.serror_pending; + env->serror.has_esr =3D events.exception.serror_has_esr; + env->serror.esr =3D events.exception.serror_esr; + + return 0; +} + int kvm_arch_put_registers(CPUState *cs, int level) { struct kvm_one_reg reg; @@ -727,6 +775,12 @@ int kvm_arch_put_registers(CPUState *cs, int level) return ret; } =20 + ret =3D kvm_put_vcpu_events(cpu); + if (ret) { + printf("return error kvm_put_vcpu_events: %d\n", ret); + return ret; + } + if (!write_list_to_kvmstate(cpu, level)) { return EINVAL; } @@ -863,6 +917,11 @@ int kvm_arch_get_registers(CPUState *cs) } vfp_set_fpcr(env, fpr); =20 + ret =3D kvm_get_vcpu_events(cpu); + if (ret) { + return ret; + } + if (!write_kvmstate_to_list(cpu)) { return EINVAL; } diff --git a/target/arm/machine.c b/target/arm/machine.c index 2e28d08..22f2d89 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -172,6 +172,27 @@ static const VMStateDescription vmstate_sve =3D { }; #endif /* AARCH64 */ =20 +static bool ras_needed(void *opaque) +{ + ARMCPU *cpu =3D opaque; + CPUARMState *env =3D &cpu->env; + + return arm_feature(env, ARM_FEATURE_RAS); +} + +static const VMStateDescription vmstate_ras =3D { + .name =3D "cpu/ras", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D ras_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32(env.serror.pending, ARMCPU), + VMSTATE_UINT32(env.serror.has_esr, ARMCPU), + VMSTATE_UINT64(env.serror.esr, ARMCPU), + VMSTATE_END_OF_LIST() + } +}; + static bool m_needed(void *opaque) { ARMCPU *cpu =3D opaque; @@ -723,6 +744,7 @@ const VMStateDescription vmstate_arm_cpu =3D { #ifdef TARGET_AARCH64 &vmstate_sve, #endif + &vmstate_ras, NULL } }; --=20 1.8.3.1