From nobody Sun Nov 2 12:05:23 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1527738148891528.2993380628369; Wed, 30 May 2018 20:42:28 -0700 (PDT) Received: from localhost ([::1]:41837 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fOETs-0005d8-63 for importer@patchew.org; Wed, 30 May 2018 23:42:28 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54745) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fOEQH-00032Y-Kp for qemu-devel@nongnu.org; Wed, 30 May 2018 23:38:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fOEQG-0007Fs-Mv for qemu-devel@nongnu.org; Wed, 30 May 2018 23:38:45 -0400 Received: from [45.249.212.32] (port=33525 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fOEQE-0007Cc-2m; Wed, 30 May 2018 23:38:42 -0400 Received: from DGGEMS412-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id BB41B2A7F5F79; Thu, 31 May 2018 11:38:37 +0800 (CST) Received: from localhost.localdomain (10.143.28.90) by DGGEMS412-HUB.china.huawei.com (10.3.19.212) with Microsoft SMTP Server id 14.3.382.0; Thu, 31 May 2018 11:38:29 +0800 From: Dongjiu Geng To: , , , Date: Thu, 31 May 2018 19:43:57 +0800 Message-ID: <1527767037-6105-4-git-send-email-gengdongjiu@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1527767037-6105-1-git-send-email-gengdongjiu@huawei.com> References: <1527767037-6105-1-git-send-email-gengdongjiu@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.143.28.90] X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 45.249.212.32 Subject: [Qemu-devel] [PATCH v1 3/3] target: arm: Add support for VCPU event states X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This patch extends the qemu-kvm state sync logic with support for KVM_GET/SET_VCPU_EVENTS, giving access to yet missing SError exception. And also it can support the exception state migration. Signed-off-by: Dongjiu Geng --- target/arm/cpu.h | 5 ++++ target/arm/kvm64.c | 64 ++++++++++++++++++++++++++++++++++++++++++++++++= ++++ target/arm/machine.c | 3 +++ 3 files changed, 72 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 8488273..b3d6682 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -645,6 +645,11 @@ typedef struct CPUARMState { const struct arm_boot_info *boot_info; /* Store GICv3CPUState to access from this struct */ void *gicv3state; + struct { + uint32_t pending; + uint32_t has_esr; + uint64_t esr; + } serror; } CPUARMState; =20 /** diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index e0b8246..45b6911 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -600,6 +600,59 @@ int kvm_arm_cpreg_level(uint64_t regidx) #define AARCH64_SIMD_CTRL_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U32 | \ KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x)) =20 +static bool kvm_can_set_vcpu_esr(ARMCPU *cpu) +{ + CPUState *cs =3D CPU(cpu); + + int ret =3D kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_INJECT_SERR= OR_ESR); + return (ret) ? true : false; +} + + +static int kvm_put_vcpu_events(ARMCPU *cpu) +{ + CPUARMState *env =3D &cpu->env; + struct kvm_vcpu_events events =3D {}; + + if (!kvm_has_vcpu_events()) { + return 0; + } + + memset(&events, 0, sizeof(events)); + events.exception.serror_pending =3D env->serror.pending; + + if (kvm_can_set_vcpu_esr(cpu)) { + events.exception.serror_has_esr =3D env->serror.has_esr; + events.exception.serror_esr =3D env->serror.esr; + } + + return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events); +} + +static int kvm_get_vcpu_events(ARMCPU *cpu) +{ + CPUARMState *env =3D &cpu->env; + struct kvm_vcpu_events events; + int ret; + + if (!kvm_has_vcpu_events()) { + return 0; + } + + memset(&events, 0, sizeof(events)); + ret =3D kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events); + + if (ret < 0) { + return ret; + } + + env->serror.pending =3D events.exception.serror_pending; + env->serror.has_esr =3D events.exception.serror_has_esr; + env->serror.esr =3D events.exception.serror_esr; + + return 0; +} + int kvm_arch_put_registers(CPUState *cs, int level) { struct kvm_one_reg reg; @@ -727,6 +780,12 @@ int kvm_arch_put_registers(CPUState *cs, int level) return ret; } =20 + ret =3D kvm_put_vcpu_events(cpu); + if (ret) { + printf("return error kvm_put_vcpu_events: %d\n", ret); + return ret; + } + if (!write_list_to_kvmstate(cpu, level)) { return EINVAL; } @@ -863,6 +922,11 @@ int kvm_arch_get_registers(CPUState *cs) } vfp_set_fpcr(env, fpr); =20 + ret =3D kvm_get_vcpu_events(cpu); + if (ret) { + return ret; + } + if (!write_kvmstate_to_list(cpu)) { return EINVAL; } diff --git a/target/arm/machine.c b/target/arm/machine.c index 2e28d08..5a359f4 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -695,6 +695,9 @@ const VMStateDescription vmstate_arm_cpu =3D { VMSTATE_UINT32(env.exception.syndrome, ARMCPU), VMSTATE_UINT32(env.exception.fsr, ARMCPU), VMSTATE_UINT64(env.exception.vaddress, ARMCPU), + VMSTATE_UINT32(env.serror.pending, ARMCPU), + VMSTATE_UINT32(env.serror.has_esr, ARMCPU), + VMSTATE_UINT64(env.serror.esr, ARMCPU), VMSTATE_TIMER_PTR(gt_timer[GTIMER_PHYS], ARMCPU), VMSTATE_TIMER_PTR(gt_timer[GTIMER_VIRT], ARMCPU), { --=20 2.7.4