From nobody Sat Nov 1 22:27:51 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1527736722522862.778348178604; Wed, 30 May 2018 20:18:42 -0700 (PDT) Received: from localhost ([::1]:41762 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fOE6n-0005UZ-2I for importer@patchew.org; Wed, 30 May 2018 23:18:37 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50580) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fOE56-0004Oj-9O for qemu-devel@nongnu.org; Wed, 30 May 2018 23:16:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fOE55-0004ZP-9R for qemu-devel@nongnu.org; Wed, 30 May 2018 23:16:52 -0400 Received: from [45.249.212.35] (port=40702 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fOE4z-0004Us-Kp; Wed, 30 May 2018 23:16:45 -0400 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id B5F6920FF1A53; Thu, 31 May 2018 11:16:39 +0800 (CST) Received: from HGHY1Z002260041.china.huawei.com (10.177.16.142) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.382.0; Thu, 31 May 2018 11:16:32 +0800 From: Shannon Zhao To: Date: Thu, 31 May 2018 11:15:56 +0800 Message-ID: <1527736557-11084-2-git-send-email-zhaoshenglong@huawei.com> X-Mailer: git-send-email 1.9.0.msysgit.0 In-Reply-To: <1527736557-11084-1-git-send-email-zhaoshenglong@huawei.com> References: <1527736557-11084-1-git-send-email-zhaoshenglong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.16.142] X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 45.249.212.35 Subject: [Qemu-devel] [PATCH v5 1/2] arm_gicv3_kvm: kvm_dist_get/put_priority: skip the registers banked by GICR_IPRIORITYR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, eric.auger@redhat.com, qemu-stable@nongnu.org, qemu-devel@nongnu.org, shannon.zhaosl@gmail.com, Shannon Zhao Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" While for_each_dist_irq_reg loop starts from GIC_INTERNAL, it forgot to offset the date array and index. This will overlap the GICR registers value and leave the last GIC_INTERNAL irq's registers out of update. Fixes: 367b9f527becdd20ddf116e17a3c0c2bbc486920 Cc: qemu-stable@nongnu.org Reviewed-by: Peter Maydell Signed-off-by: Shannon Zhao Reviewed-by: Eric Auger --- hw/intc/arm_gicv3_kvm.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c index 3536795..147e691 100644 --- a/hw/intc/arm_gicv3_kvm.c +++ b/hw/intc/arm_gicv3_kvm.c @@ -135,7 +135,14 @@ static void kvm_dist_get_priority(GICv3State *s, uint3= 2_t offset, uint8_t *bmp) uint32_t reg, *field; int irq; =20 - field =3D (uint32_t *)bmp; + /* For the KVM GICv3, affinity routing is always enabled, and the firs= t 8 + * GICD_IPRIORITYR registers are always RAZ/WI. The corresponding + * functionality is replaced by GICR_IPRIORITYR. It doesn't need to + * sync them. So it needs to skip the field of GIC_INTERNAL irqs in bm= p and + * offset. + */ + field =3D (uint32_t *)(bmp + GIC_INTERNAL); + offset +=3D (GIC_INTERNAL * 8) / 8; for_each_dist_irq_reg(irq, s->num_irq, 8) { kvm_gicd_access(s, offset, ®, false); *field =3D reg; @@ -149,7 +156,14 @@ static void kvm_dist_put_priority(GICv3State *s, uint3= 2_t offset, uint8_t *bmp) uint32_t reg, *field; int irq; =20 - field =3D (uint32_t *)bmp; + /* For the KVM GICv3, affinity routing is always enabled, and the firs= t 8 + * GICD_IPRIORITYR registers are always RAZ/WI. The corresponding + * functionality is replaced by GICR_IPRIORITYR. It doesn't need to + * sync them. So it needs to skip the field of GIC_INTERNAL irqs in bm= p and + * offset. + */ + field =3D (uint32_t *)(bmp + GIC_INTERNAL); + offset +=3D (GIC_INTERNAL * 8) / 8; for_each_dist_irq_reg(irq, s->num_irq, 8) { reg =3D *field; kvm_gicd_access(s, offset, ®, true); --=20 2.0.4 From nobody Sat Nov 1 22:27:51 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 15277367293459.797853245981742; Wed, 30 May 2018 20:18:49 -0700 (PDT) Received: from localhost ([::1]:41763 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fOE6u-0005ab-Hs for importer@patchew.org; Wed, 30 May 2018 23:18:44 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50617) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fOE58-0004Qx-CH for qemu-devel@nongnu.org; Wed, 30 May 2018 23:16:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fOE56-0004aZ-NP for qemu-devel@nongnu.org; Wed, 30 May 2018 23:16:54 -0400 Received: from [45.249.212.35] (port=40701 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fOE4z-0004Uu-LQ; Wed, 30 May 2018 23:16:46 -0400 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id D2FB980A5756E; Thu, 31 May 2018 11:16:39 +0800 (CST) Received: from HGHY1Z002260041.china.huawei.com (10.177.16.142) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.382.0; Thu, 31 May 2018 11:16:33 +0800 From: Shannon Zhao To: Date: Thu, 31 May 2018 11:15:57 +0800 Message-ID: <1527736557-11084-3-git-send-email-zhaoshenglong@huawei.com> X-Mailer: git-send-email 1.9.0.msysgit.0 In-Reply-To: <1527736557-11084-1-git-send-email-zhaoshenglong@huawei.com> References: <1527736557-11084-1-git-send-email-zhaoshenglong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.16.142] X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 45.249.212.35 Subject: [Qemu-devel] [PATCH v5 2/2] arm_gicv3_kvm: kvm_dist_get/put: skip the registers banked by GICR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, eric.auger@redhat.com, qemu-stable@nongnu.org, qemu-devel@nongnu.org, shannon.zhaosl@gmail.com, Shannon Zhao Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" While we skip the GIC_INTERNAL irqs, we don't change the register offset accordingly. This will overlap the GICR registers value and leave the last GIC_INTERNAL irq's registers out of update. Fix this by skipping the registers banked by GICR. Also for migration compatibility if the migration source (old version qemu) doesn't send gicd_no_migration_shift_bug =3D 1 to destination, then we shift the data of PPI to get the right data for SPI. Fixes: 367b9f527becdd20ddf116e17a3c0c2bbc486920 Cc: qemu-stable@nongnu.org Signed-off-by: Shannon Zhao Reviewed-by: Eric Auger Reviewed-by: Peter Maydell --- hw/intc/arm_gicv3_common.c | 79 ++++++++++++++++++++++++++++++++++= ++++ hw/intc/arm_gicv3_kvm.c | 38 ++++++++++++++++++ include/hw/intc/arm_gicv3_common.h | 1 + 3 files changed, 118 insertions(+) diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c index 7b54d52..68211a2 100644 --- a/hw/intc/arm_gicv3_common.c +++ b/hw/intc/arm_gicv3_common.c @@ -27,6 +27,7 @@ #include "hw/intc/arm_gicv3_common.h" #include "gicv3_internal.h" #include "hw/arm/linux-boot-if.h" +#include "sysemu/kvm.h" =20 static int gicv3_pre_save(void *opaque) { @@ -141,6 +142,79 @@ static const VMStateDescription vmstate_gicv3_cpu =3D { } }; =20 +static int gicv3_gicd_no_migration_shift_bug_pre_load(void *opaque) +{ + GICv3State *cs =3D opaque; + + /* + * The gicd_no_migration_shift_bug flag is used for migration compatibi= lty + * for old version QEMU which may have the GICD bmp shift bug under KVM= mode. + * Strictly, what we want to know is whether the migration source is us= ing + * KVM. Since we don't have any way to determine that, we look at wheth= er the + * destination is using KVM; this is close enough because for the older= QEMU + * versions with this bug KVM -> TCG migration didn't work anyway. If t= he + * source is a newer QEMU without this bug it will transmit the migrati= on + * subsection which sets the flag to true; otherwise it will remain set= to + * the value we select here. + */ + if (kvm_enabled()) { + cs->gicd_no_migration_shift_bug =3D false; + } + + return 0; +} + +static int gicv3_gicd_no_migration_shift_bug_post_load(void *opaque, + int version_id) +{ + GICv3State *cs =3D opaque; + + if (cs->gicd_no_migration_shift_bug) { + return 0; + } + + /* Older versions of QEMU had a bug in the handling of state save/rest= ore + * to the KVM GICv3: they got the offset in the bitmap arrays wrong, + * so that instead of the data for external interrupts 32 and up + * starting at bit position 32 in the bitmap, it started at bit + * position 64. If we're receiving data from a QEMU with that bug, + * we must move the data down into the right place. + */ + memmove(cs->group, (uint8_t *)cs->group + GIC_INTERNAL / 8, + sizeof(cs->group) - GIC_INTERNAL / 8); + memmove(cs->grpmod, (uint8_t *)cs->grpmod + GIC_INTERNAL / 8, + sizeof(cs->grpmod) - GIC_INTERNAL / 8); + memmove(cs->enabled, (uint8_t *)cs->enabled + GIC_INTERNAL / 8, + sizeof(cs->enabled) - GIC_INTERNAL / 8); + memmove(cs->pending, (uint8_t *)cs->pending + GIC_INTERNAL / 8, + sizeof(cs->pending) - GIC_INTERNAL / 8); + memmove(cs->active, (uint8_t *)cs->active + GIC_INTERNAL / 8, + sizeof(cs->active) - GIC_INTERNAL / 8); + memmove(cs->edge_trigger, (uint8_t *)cs->edge_trigger + GIC_INTERNAL /= 8, + sizeof(cs->edge_trigger) - GIC_INTERNAL / 8); + + /* + * While this new version QEMU doesn't have this kind of bug as we fix= it, + * so it's need to set the flag to true to indicate that and it's necc= essary + * for next migration to work from this new version QEMU. + */ + cs->gicd_no_migration_shift_bug =3D true; + + return 0; +} + +const VMStateDescription vmstate_gicv3_gicd_no_migration_shift_bug =3D { + .name =3D "arm_gicv3/gicd_no_migration_shift_bug", + .version_id =3D 1, + .minimum_version_id =3D 1, + .pre_load =3D gicv3_gicd_no_migration_shift_bug_pre_load, + .post_load =3D gicv3_gicd_no_migration_shift_bug_post_load, + .fields =3D (VMStateField[]) { + VMSTATE_BOOL(gicd_no_migration_shift_bug, GICv3State), + VMSTATE_END_OF_LIST() + } +}; + static const VMStateDescription vmstate_gicv3 =3D { .name =3D "arm_gicv3", .version_id =3D 1, @@ -165,6 +239,10 @@ static const VMStateDescription vmstate_gicv3 =3D { VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, GICv3State, num_cpu, vmstate_gicv3_cpu, GICv3CPUSt= ate), VMSTATE_END_OF_LIST() + }, + .subsections =3D (const VMStateDescription * []) { + &vmstate_gicv3_gicd_no_migration_shift_bug, + NULL } }; =20 @@ -364,6 +442,7 @@ static void arm_gicv3_common_reset(DeviceState *dev) gicv3_gicd_group_set(s, i); } } + s->gicd_no_migration_shift_bug =3D true; } =20 static void arm_gic_common_linux_init(ARMLinuxBootIf *obj, diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c index 147e691..001d82b 100644 --- a/hw/intc/arm_gicv3_kvm.c +++ b/hw/intc/arm_gicv3_kvm.c @@ -178,6 +178,14 @@ static void kvm_dist_get_edge_trigger(GICv3State *s, u= int32_t offset, uint32_t reg; int irq; =20 + /* For the KVM GICv3, affinity routing is always enabled, and the firs= t 2 + * GICD_ICFGR registers are always RAZ/WI. The corresponding + * functionality is replaced by GICR_ICFGR. It doesn't need to sync + * them. So it should increase the offset to skip GIC_INTERNAL irqs. + * This matches the for_each_dist_irq_reg() macro which also skips the + * first GIC_INTERNAL irqs. + */ + offset +=3D (GIC_INTERNAL * 2) / 8; for_each_dist_irq_reg(irq, s->num_irq, 2) { kvm_gicd_access(s, offset, ®, false); reg =3D half_unshuffle32(reg >> 1); @@ -195,6 +203,14 @@ static void kvm_dist_put_edge_trigger(GICv3State *s, u= int32_t offset, uint32_t reg; int irq; =20 + /* For the KVM GICv3, affinity routing is always enabled, and the firs= t 2 + * GICD_ICFGR registers are always RAZ/WI. The corresponding + * functionality is replaced by GICR_ICFGR. It doesn't need to sync + * them. So it should increase the offset to skip GIC_INTERNAL irqs. + * This matches the for_each_dist_irq_reg() macro which also skips the + * first GIC_INTERNAL irqs. + */ + offset +=3D (GIC_INTERNAL * 2) / 8; for_each_dist_irq_reg(irq, s->num_irq, 2) { reg =3D *gic_bmp_ptr32(bmp, irq); if (irq % 32 !=3D 0) { @@ -236,6 +252,15 @@ static void kvm_dist_getbmp(GICv3State *s, uint32_t of= fset, uint32_t *bmp) uint32_t reg; int irq; =20 + /* For the KVM GICv3, affinity routing is always enabled, and the + * GICD_IGROUPR0/GICD_IGRPMODR0/GICD_ISENABLER0/GICD_ISPENDR0/ + * GICD_ISACTIVER0 registers are always RAZ/WI. The corresponding + * functionality is replaced by the GICR registers. It doesn't need to= sync + * them. So it should increase the offset to skip GIC_INTERNAL irqs. + * This matches the for_each_dist_irq_reg() macro which also skips the + * first GIC_INTERNAL irqs. + */ + offset +=3D (GIC_INTERNAL * 1) / 8; for_each_dist_irq_reg(irq, s->num_irq, 1) { kvm_gicd_access(s, offset, ®, false); *gic_bmp_ptr32(bmp, irq) =3D reg; @@ -249,6 +274,19 @@ static void kvm_dist_putbmp(GICv3State *s, uint32_t of= fset, uint32_t reg; int irq; =20 + /* For the KVM GICv3, affinity routing is always enabled, and the + * GICD_IGROUPR0/GICD_IGRPMODR0/GICD_ISENABLER0/GICD_ISPENDR0/ + * GICD_ISACTIVER0 registers are always RAZ/WI. The corresponding + * functionality is replaced by the GICR registers. It doesn't need to= sync + * them. So it should increase the offset to skip GIC_INTERNAL irqs. + * This matches the for_each_dist_irq_reg() macro which also skips the + * first GIC_INTERNAL irqs. + */ + offset +=3D (GIC_INTERNAL * 1) / 8; + if (clroffset !=3D 0) { + clroffset +=3D (1 * sizeof(uint32_t)); + } + for_each_dist_irq_reg(irq, s->num_irq, 1) { /* If this bitmap is a set/clear register pair, first write to the * clear-reg to clear all bits before using the set-reg to write diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3= _common.h index bccdfe1..d75b49d 100644 --- a/include/hw/intc/arm_gicv3_common.h +++ b/include/hw/intc/arm_gicv3_common.h @@ -217,6 +217,7 @@ struct GICv3State { uint32_t revision; bool security_extn; bool irq_reset_nonsecure; + bool gicd_no_migration_shift_bug; =20 int dev_fd; /* kvm device fd if backed by kvm vgic support */ Error *migration_blocker; --=20 2.0.4