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X-Received-From: 2607:f8b0:400e:c05::232 Subject: [Qemu-devel] [PATCH v1 06/30] RISC-V: Move non-ops from op_helper to cpu_helper X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Bastian Koppelmann , Palmer Dabbelt , Michael Clark , Alistair Francis , patches@groups.riscv.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This patch makes op_helper.c contain only instruction operation helpers used by translate.c and moves any unrelated cpu helpers into cpu_helper.c. No logic is changed by this patch. Cc: Sagar Karandikar Cc: Bastian Koppelmann Cc: Palmer Dabbelt Cc: Alistair Francis Signed-off-by: Michael Clark Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/riscv/Makefile.objs | 2 +- target/riscv/{helper.c =3D> cpu_helper.c} | 35 +++++++++++++++++++++++++++= +++++- target/riscv/op_helper.c | 34 -----------------------------= --- 3 files changed, 35 insertions(+), 36 deletions(-) rename target/riscv/{helper.c =3D> cpu_helper.c} (95%) diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs index abd0a7cde333..fcc5d34c1f2e 100644 --- a/target/riscv/Makefile.objs +++ b/target/riscv/Makefile.objs @@ -1 +1 @@ -obj-y +=3D translate.o op_helper.o helper.o cpu.o fpu_helper.o gdbstub.o p= mp.o +obj-y +=3D translate.o op_helper.o cpu_helper.o cpu.o fpu_helper.o gdbstub= .o pmp.o diff --git a/target/riscv/helper.c b/target/riscv/cpu_helper.c similarity index 95% rename from target/riscv/helper.c rename to target/riscv/cpu_helper.c index 47d116e9c13f..6c886e99055a 100644 --- a/target/riscv/helper.c +++ b/target/riscv/cpu_helper.c @@ -1,5 +1,5 @@ /* - * RISC-V emulation helpers for qemu. + * RISC-V CPU helpers for qemu. * * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu * Copyright (c) 2017-2018 SiFive, Inc. @@ -72,6 +72,39 @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int interrup= t_request) =20 #if !defined(CONFIG_USER_ONLY) =20 +/* iothread_mutex must be held */ +uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value) +{ + CPURISCVState *env =3D &cpu->env; + uint32_t old, new, cmp =3D atomic_read(&env->mip); + + do { + old =3D cmp; + new =3D (old & ~mask) | (value & mask); + cmp =3D atomic_cmpxchg(&env->mip, old, new); + } while (old !=3D cmp); + + if (new && !old) { + cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD); + } else if (!new && old) { + cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_HARD); + } + + return old; +} + +void riscv_set_mode(CPURISCVState *env, target_ulong newpriv) +{ + if (newpriv > PRV_M) { + g_assert_not_reached(); + } + if (newpriv =3D=3D PRV_H) { + newpriv =3D PRV_U; + } + /* tlb_flush is unnecessary as mode is contained in mmu_idx */ + env->priv =3D newpriv; +} + /* get_physical_address - get the physical address for this virtual address * * Do a page table walk to obtain the physical address corresponding to a diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 5a02795bf931..2b9dd9da6486 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -652,39 +652,6 @@ target_ulong helper_csrrc(CPURISCVState *env, target_u= long src, =20 #ifndef CONFIG_USER_ONLY =20 -/* iothread_mutex must be held */ -uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value) -{ - CPURISCVState *env =3D &cpu->env; - uint32_t old, new, cmp =3D atomic_read(&env->mip); - - do { - old =3D cmp; - new =3D (old & ~mask) | (value & mask); - cmp =3D atomic_cmpxchg(&env->mip, old, new); - } while (old !=3D cmp); - - if (new && !old) { - cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD); - } else if (!new && old) { - cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_HARD); - } - - return old; -} - -void riscv_set_mode(CPURISCVState *env, target_ulong newpriv) -{ - if (newpriv > PRV_M) { - g_assert_not_reached(); - } - if (newpriv =3D=3D PRV_H) { - newpriv =3D PRV_U; - } - /* tlb_flush is unnecessary as mode is contained in mmu_idx */ - env->priv =3D newpriv; -} - target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb) { if (!(env->priv >=3D PRV_S)) { @@ -735,7 +702,6 @@ target_ulong helper_mret(CPURISCVState *env, target_ulo= ng cpu_pc_deb) return retpc; } =20 - void helper_wfi(CPURISCVState *env) { CPUState *cs =3D CPU(riscv_env_get_cpu(env)); --=20 2.7.0