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X-Received-From: 2607:f8b0:400e:c05::234 Subject: [Qemu-devel] [PATCH v1 04/30] RISC-V: Simplify riscv_cpu_local_irqs_pending X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Bastian Koppelmann , Palmer Dabbelt , Michael Clark , Alistair Francis , patches@groups.riscv.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This commit is intended to improve readability. There is no change to the logic. Cc: Sagar Karandikar Cc: Bastian Koppelmann Cc: Palmer Dabbelt Cc: Alistair Francis Signed-off-by: Michael Clark Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/helper.c | 34 ++++++++++++---------------------- 1 file changed, 12 insertions(+), 22 deletions(-) diff --git a/target/riscv/helper.c b/target/riscv/helper.c index 3b57e1360549..47d116e9c13f 100644 --- a/target/riscv/helper.c +++ b/target/riscv/helper.c @@ -35,28 +35,18 @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) } =20 #ifndef CONFIG_USER_ONLY -/* - * Return RISC-V IRQ number if an interrupt should be taken, else -1. - * Used in cpu-exec.c - * - * Adapted from Spike's processor_t::take_interrupt() - */ -static int riscv_cpu_hw_interrupts_pending(CPURISCVState *env) +static int riscv_cpu_local_irq_pending(CPURISCVState *env) { - target_ulong pending_interrupts =3D atomic_read(&env->mip) & env->mie; - - target_ulong mie =3D get_field(env->mstatus, MSTATUS_MIE); - target_ulong m_enabled =3D env->priv < PRV_M || (env->priv =3D=3D PRV_= M && mie); - target_ulong enabled_interrupts =3D pending_interrupts & - ~env->mideleg & -m_enabled; - - target_ulong sie =3D get_field(env->mstatus, MSTATUS_SIE); - target_ulong s_enabled =3D env->priv < PRV_S || (env->priv =3D=3D PRV_= S && sie); - enabled_interrupts |=3D pending_interrupts & env->mideleg & - -s_enabled; - - if (enabled_interrupts) { - return ctz64(enabled_interrupts); /* since non-zero */ + target_ulong mstatus_mie =3D get_field(env->mstatus, MSTATUS_MIE); + target_ulong mstatus_sie =3D get_field(env->mstatus, MSTATUS_SIE); + target_ulong pending =3D atomic_read(&env->mip) & env->mie; + target_ulong mie =3D env->priv < PRV_M || (env->priv =3D=3D PRV_M && m= status_mie); + target_ulong sie =3D env->priv < PRV_S || (env->priv =3D=3D PRV_S && m= status_sie); + target_ulong irqs =3D (pending & ~env->mideleg & -mie) | + (pending & env->mideleg & -sie); + + if (irqs) { + return ctz64(irqs); /* since non-zero */ } else { return EXCP_NONE; /* indicates no pending interrupt */ } @@ -69,7 +59,7 @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt= _request) if (interrupt_request & CPU_INTERRUPT_HARD) { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; - int interruptno =3D riscv_cpu_hw_interrupts_pending(env); + int interruptno =3D riscv_cpu_local_irq_pending(env); if (interruptno >=3D 0) { cs->exception_index =3D RISCV_EXCP_INT_FLAG | interruptno; riscv_cpu_do_interrupt(cs); --=20 2.7.0