From nobody Mon Feb 9 12:14:54 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1527035051038877.8332091357672; Tue, 22 May 2018 17:24:11 -0700 (PDT) Received: from localhost ([::1]:58527 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fLHZR-0004km-DC for importer@patchew.org; Tue, 22 May 2018 20:24:01 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41990) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fLHSe-0007q6-Q3 for qemu-devel@nongnu.org; Tue, 22 May 2018 20:17:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fLHSb-0000Xt-Hy for qemu-devel@nongnu.org; Tue, 22 May 2018 20:17:00 -0400 Received: from mail-pl0-x241.google.com ([2607:f8b0:400e:c01::241]:34853) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fLHSb-0000Wb-9l for qemu-devel@nongnu.org; Tue, 22 May 2018 20:16:57 -0400 Received: by mail-pl0-x241.google.com with SMTP id i5-v6so11868393plt.2 for ; Tue, 22 May 2018 17:16:57 -0700 (PDT) Received: from localhost.localdomain (122-58-167-22-fibre.bb.spark.co.nz. [122.58.167.22]) by smtp.gmail.com with ESMTPSA id j1-v6sm28935626pfh.95.2018.05.22.17.16.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 22 May 2018 17:16:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=BPOMjDXwagOBIoQMJUzyDoTLheTQeqD6qWY2YD5A1Rk=; b=LnsO99vyian9eA8HgbDAdqT2WcOiDSIuNA3eDLg0BckDnsRre358kimXWBz3MspLnK +blEFKqJU/ZZvtEEYuNNsizdA8erN+3xbtU4amqo2Dm8GJhD5VhWjqmgkky89igb5kR+ tpc7vCnzzb21Hrfv9iWEyQe51deY6r+nYbDV+Z7c6ILcjuIhYN3i4bCjRSgD3UGgEh5h meYgrZbV5Ful4pBVTwPaEu9tKA2DjJr4i/VTVGPzwlm4Wc48CxcGhvEbv/EwaodqVe0A gV4TcAAVvEHw8elBbn34m6P9mDhO0ESB+Bb705hvI96jn58LuTLSm+3NU7xzhVKTzbLp MUwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=BPOMjDXwagOBIoQMJUzyDoTLheTQeqD6qWY2YD5A1Rk=; b=HEVfY7n6jCyN7WZVowaEu+J+aQc2CpyZi4uGK6qhwyo/K2UXZJskK8LKiOuHJCoZu/ oI77+v2HcZBz/nki8vXVUrH/oWPniqJyNjgQyp/4fGRKVV+v2ksg5wQlUf8ALz4VlVLv IlFGKOYtkKpUKTNTA9ZatwlIBHoI27oskQMv2fFcmBp0HW+LAIFFMq8B7cZ0E7vniNSO 6HF1vU/KSqeiIyhSe6K74EiGVeyogOfNNg/5P03qFRqoxugfaCYqMluWeazkHusdD+0p oeR+0/5mOKiggdihTW6nxnxTLseLfFVwHiX7ZJQL98Vl9WZt1UpvVXqpw0Jx9zUbYCFO GWNw== X-Gm-Message-State: ALKqPweqe+G1l4GuLvEEvIv6RLA3aoxnXOZEbro0gIsTecY5pmR4KUiN DlyWjf1Hj6gtSTGiueyDFw4/YtZB66E= X-Google-Smtp-Source: AB8JxZpTE4G+Rf9avM3xbtPqveGgm2yIxtYn6ykDN1fUObPU8rVjp6jkNmo2vVvu2sZKSUvn9rRC4g== X-Received: by 2002:a17:902:2702:: with SMTP id c2-v6mr576154plb.297.1527034616379; Tue, 22 May 2018 17:16:56 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Wed, 23 May 2018 12:14:50 +1200 Message-Id: <1527034517-7851-4-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1527034517-7851-1-git-send-email-mjc@sifive.com> References: <1527034517-7851-1-git-send-email-mjc@sifive.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::241 Subject: [Qemu-devel] [PATCH v1 03/30] RISC-V: Use atomic_cmpxchg to update PLIC bitmaps X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Bastian Koppelmann , Palmer Dabbelt , Michael Clark , Alistair Francis , patches@groups.riscv.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The PLIC previously used a mutex to protect against concurrent access to the claimed and pending bitfields. Instead of using a mutex, we update the bitfields using atomic_cmpxchg. Rename sifive_plic_num_irqs_pending to sifive_plic_irqs_pending and add an early out if any interrupts are pending as the count of pending interrupts is not used. Cc: Sagar Karandikar Cc: Bastian Koppelmann Cc: Palmer Dabbelt Cc: Alistair Francis Signed-off-by: Michael Clark Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- hw/riscv/sifive_plic.c | 49 +++++++++++++++++++-------------------= ---- include/hw/riscv/sifive_plic.h | 1 - 2 files changed, 22 insertions(+), 28 deletions(-) diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c index 874de2ebaf77..1af23c76e603 100644 --- a/hw/riscv/sifive_plic.c +++ b/hw/riscv/sifive_plic.c @@ -81,36 +81,32 @@ static void sifive_plic_print_state(SiFivePLICState *pl= ic) } } =20 -static -void sifive_plic_set_pending(SiFivePLICState *plic, int irq, bool pending) +static uint32_t atomic_set_masked(uint32_t *a, uint32_t mask, uint32_t val= ue) { - qemu_mutex_lock(&plic->lock); - uint32_t word =3D irq >> 5; - if (pending) { - plic->pending[word] |=3D (1 << (irq & 31)); - } else { - plic->pending[word] &=3D ~(1 << (irq & 31)); - } - qemu_mutex_unlock(&plic->lock); + uint32_t old, new, cmp =3D atomic_read(a); + + do { + old =3D cmp; + new =3D (old & ~mask) | (value & mask); + cmp =3D atomic_cmpxchg(a, old, new); + } while (old !=3D cmp); + + return old; } =20 -static -void sifive_plic_set_claimed(SiFivePLICState *plic, int irq, bool claimed) +static void sifive_plic_set_pending(SiFivePLICState *plic, int irq, bool l= evel) { - qemu_mutex_lock(&plic->lock); - uint32_t word =3D irq >> 5; - if (claimed) { - plic->claimed[word] |=3D (1 << (irq & 31)); - } else { - plic->claimed[word] &=3D ~(1 << (irq & 31)); - } - qemu_mutex_unlock(&plic->lock); + atomic_set_masked(&plic->pending[irq >> 5], 1 << (irq & 31), -!!level); } =20 -static -int sifive_plic_num_irqs_pending(SiFivePLICState *plic, uint32_t addrid) +static void sifive_plic_set_claimed(SiFivePLICState *plic, int irq, bool l= evel) { - int i, j, count =3D 0; + atomic_set_masked(&plic->claimed[irq >> 5], 1 << (irq & 31), -!!level); +} + +static int sifive_plic_irqs_pending(SiFivePLICState *plic, uint32_t addrid) +{ + int i, j; for (i =3D 0; i < plic->bitfield_words; i++) { uint32_t pending_enabled_not_claimed =3D (plic->pending[i] & ~plic->claimed[i]) & @@ -123,11 +119,11 @@ int sifive_plic_num_irqs_pending(SiFivePLICState *pli= c, uint32_t addrid) uint32_t prio =3D plic->source_priority[irq]; int enabled =3D pending_enabled_not_claimed & (1 << j); if (enabled && prio > plic->target_priority[addrid]) { - count++; + return 1; } } } - return count; + return 0; } =20 static void sifive_plic_update(SiFivePLICState *plic) @@ -143,7 +139,7 @@ static void sifive_plic_update(SiFivePLICState *plic) if (!env) { continue; } - int level =3D sifive_plic_num_irqs_pending(plic, addrid) > 0; + int level =3D sifive_plic_irqs_pending(plic, addrid); switch (mode) { case PLICMode_M: riscv_set_local_interrupt(RISCV_CPU(cpu), MIP_MEIP, level); @@ -440,7 +436,6 @@ static void sifive_plic_realize(DeviceState *dev, Error= **errp) memory_region_init_io(&plic->mmio, OBJECT(dev), &sifive_plic_ops, plic, TYPE_SIFIVE_PLIC, plic->aperture_size); parse_hart_config(plic); - qemu_mutex_init(&plic->lock); plic->bitfield_words =3D (plic->num_sources + 31) >> 5; plic->source_priority =3D g_new0(uint32_t, plic->num_sources); plic->target_priority =3D g_new(uint32_t, plic->num_addrs); diff --git a/include/hw/riscv/sifive_plic.h b/include/hw/riscv/sifive_plic.h index 11a5a98df1f9..ff09a288261e 100644 --- a/include/hw/riscv/sifive_plic.h +++ b/include/hw/riscv/sifive_plic.h @@ -55,7 +55,6 @@ typedef struct SiFivePLICState { uint32_t *pending; uint32_t *claimed; uint32_t *enable; - QemuMutex lock; qemu_irq *irqs; =20 /* config */ --=20 2.7.0