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[122.58.167.22]) by smtp.gmail.com with ESMTPSA id j1-v6sm28935626pfh.95.2018.05.22.17.17.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 22 May 2018 17:17:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=PsYCGi0NE7aT7jGlIh0c4jG4H/aJWAoE3l/ywa09YRM=; b=LyUHjEGhiCd8ayPXXnhPm/Jl0+DQJYd3GK4ArudWTsWpdTtKHmRjodH2qsrc/td8aD Tboy8VCkotD7vYndDJC+nq86l7L3hiFEgGgbFFdyzlwc7wloKmNeHh9ZdM2WoEPJmnPl x/mqPVBPIPUfBh8nBCjdTir5PPwl3522/4uk6zm4rS5p83rtxjpDB4ISuuTwjp+q8f1O 1+p8aKi4P0LkX5BWzkInDfCWSznWX4wpHwBMJOqlq3gsMRSFUBgWIyrfjuANz/Ekq9Ms vmnr1VHCqieqJTyOHaY9/E9lXF+wsM5rNg7MMl8G8dQlflk1UaWitDLkEkY5Pcy7ph5A X1gg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=PsYCGi0NE7aT7jGlIh0c4jG4H/aJWAoE3l/ywa09YRM=; b=lKTXcvwvunRGUMC+w4NmfGEbskUnuz5f1FyRXo+heCluRliTfCYWD9YizLvPEfaxyb jST7eX2pe54rShBbMkpgzZqHnoQGDTIfUPc6hpdvcMat/YlCHqbfcjdpRDQeTNKU7v34 N+Rut6+Vs4tehV4fMMeJx4ZywVLtOQhCjci+7qHpZekJmUlaOAVkwZ1mV2TvjYHEuMQI zyrpnym6MlGOWoy9WrLCCbMGRtTMWUNWDGfJ7+PeU6DR+ZDV/We38oLep/P45n7FXDAy 9n/1rMkvG7ZUMfdq05Lrpe20yCPtdL3LExNvMH3Ymrr0o//pA38ksqf3x6BqDYxd0Us0 B8tA== X-Gm-Message-State: ALKqPwdajppYKyokyuQ6uhjQdBuGOKBQFfZCwNwWsAxEyrMMuBRApXOU DWEuul+/W7OGDJbuKeNq3HmKpLL2KhM= X-Google-Smtp-Source: AB8JxZrIUwJK50Jm/ZO1SLyi+l9WFqRFBsh/M4RDMkuCuDwHeO3XOsVGaEvOzQynmVBxJAed4fXaCg== X-Received: by 2002:a17:902:82c3:: with SMTP id u3-v6mr592155plz.83.1527034676320; Tue, 22 May 2018 17:17:56 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Wed, 23 May 2018 12:15:06 +1200 Message-Id: <1527034517-7851-20-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1527034517-7851-1-git-send-email-mjc@sifive.com> References: <1527034517-7851-1-git-send-email-mjc@sifive.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::244 Subject: [Qemu-devel] [PATCH v1 19/30] RISC-V: Allow interrupt controllers to claim interrupts X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Bastian Koppelmann , Palmer Dabbelt , Michael Clark , Alistair Francis , patches@groups.riscv.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We can't allow the supervisor to control SEIP as this would allow the supervisor to clear a pending external interrupt which will result in lost a interrupt in the case a PLIC is attached. The SEIP bit must be hardware controlled when a PLIC is attached. This logic was previously hard-coded so SEIP was always masked even if no PLIC was attached. This patch adds riscv_cpu_claim_interrupts so that the PLIC can register control of SEIP. In the case of models without a PLIC (spike), the SEIP bit remains software controlled. This interface allows for hardware control of supervisor timer and software interrupts by other interrupt controller models. Cc: Palmer Dabbelt Cc: Sagar Karandikar Cc: Bastian Koppelmann Cc: Alistair Francis Signed-off-by: Michael Clark --- hw/riscv/sifive_plic.c | 13 +++++++++++++ target/riscv/cpu.h | 2 ++ target/riscv/cpu_helper.c | 11 +++++++++++ target/riscv/csr.c | 12 ++++-------- 4 files changed, 30 insertions(+), 8 deletions(-) diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c index dc6f4924e282..28e28d932f7c 100644 --- a/hw/riscv/sifive_plic.c +++ b/hw/riscv/sifive_plic.c @@ -23,6 +23,7 @@ #include "qemu/error-report.h" #include "hw/sysbus.h" #include "target/riscv/cpu.h" +#include "sysemu/sysemu.h" #include "hw/riscv/sifive_plic.h" =20 #define RISCV_DEBUG_PLIC 0 @@ -447,6 +448,18 @@ static void sifive_plic_realize(DeviceState *dev, Erro= r **errp) for (i =3D 0; i <=3D plic->num_sources; i++) { plic->irqs[i] =3D qemu_allocate_irq(sifive_plic_irq_request, plic,= i); } + + /* We can't allow the supervisor to control SEIP as this would allow t= he + * supervisor to clear a pending external interrupt which will result = in + * lost a interrupt in the case a PLIC is attached. The SEIP bit must = be + * hardware controlled when a PLIC is attached. */ + for (i =3D 0; i < smp_cpus; i++) { + RISCVCPU *cpu =3D RISCV_CPU(qemu_get_cpu(i)); + if (riscv_cpu_claim_interrupts(cpu, MIP_SEIP) < 0) { + error_report("sifive_plic_realize: SEIP already claimed"); + exit(1); + } + } } =20 static void sifive_plic_class_init(ObjectClass *klass, void *data) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index d6bb3136db18..ae0e3f6a544d 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -138,6 +138,7 @@ struct CPURISCVState { * mip is 32-bits to allow atomic_read on 32-bit hosts. */ uint32_t mip; + uint32_t miclaim; =20 target_ulong mie; target_ulong mideleg; @@ -262,6 +263,7 @@ void riscv_cpu_list(FILE *f, fprintf_function cpu_fprin= tf); #define cpu_mmu_index riscv_cpu_mmu_index =20 #ifndef CONFIG_USER_ONLY +int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts); uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value= ); #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value = */ #endif diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index b4bbf7a9fa0a..7c9f6c46c75a 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -72,6 +72,17 @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int interrup= t_request) =20 #if !defined(CONFIG_USER_ONLY) =20 +int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts) +{ + CPURISCVState *env =3D &cpu->env; + if (env->miclaim & interrupts) { + return -1; + } else { + env->miclaim |=3D interrupts; + return 0; + } +} + /* iothread_mutex must be held */ uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value) { diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 45e33d876034..9bbe81a110a5 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -502,15 +502,11 @@ static int rmw_mip(CPURISCVState *env, int csrno, tar= get_ulong *ret_value, target_ulong new_value, target_ulong write_mask) { RISCVCPU *cpu =3D riscv_env_get_cpu(env); - target_ulong mask =3D write_mask & delegable_ints; - uint32_t old_mip; =20 - /* We can't allow the supervisor to control SEIP as this would allow t= he - * supervisor to clear a pending external interrupt which will result = in - * lost a interrupt in the case a PLIC is attached. The SEIP bit must = be - * hardware controlled when a PLIC is attached. This should be an opti= on - * for CPUs with software-delegated Supervisor External Interrupts. */ - mask &=3D ~MIP_SEIP; + /* Allow software control of delegable interrupts not claimed by hardw= are */ + target_ulong mask =3D write_mask & delegable_ints & ~env->miclaim; + + uint32_t old_mip; =20 if (mask) { qemu_mutex_lock_iothread(); --=20 2.7.0