From nobody Mon Feb 9 13:59:01 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1527035192028963.9872202612812; Tue, 22 May 2018 17:26:32 -0700 (PDT) Received: from localhost ([::1]:58542 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fLHbr-0006ot-6Q for importer@patchew.org; Tue, 22 May 2018 20:26:31 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42299) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fLHTH-0008K1-N4 for qemu-devel@nongnu.org; Tue, 22 May 2018 20:17:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fLHTG-0000vX-Hx for qemu-devel@nongnu.org; Tue, 22 May 2018 20:17:39 -0400 Received: from mail-pf0-x243.google.com ([2607:f8b0:400e:c00::243]:40692) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fLHTG-0000vA-BN for qemu-devel@nongnu.org; Tue, 22 May 2018 20:17:38 -0400 Received: by mail-pf0-x243.google.com with SMTP id f189-v6so9564049pfa.7 for ; Tue, 22 May 2018 17:17:38 -0700 (PDT) Received: from localhost.localdomain (122-58-167-22-fibre.bb.spark.co.nz. [122.58.167.22]) by smtp.gmail.com with ESMTPSA id j1-v6sm28935626pfh.95.2018.05.22.17.17.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 22 May 2018 17:17:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=/SjfesHXbs8d25Z6pjFleXAP2nPA54RfioXWDpjohz8=; b=hf70wHhzn6GPdhNMKOzC1T8fDfq4KrgUQI0Am46okTb7nkOJ6/XUAy7McfRWwuuJvf NWYGvtDQNUZBK4tfC1vGzQOK6TDgn4Sb1WmL8fNq6RFu0QiplzkL+Rffx3VEjKU6UXrc bs3ahAF7LBoNHcgQkptKaR0lOm8ncf9Q0wh0g6jaQZSURi8VLeG7oLO7nEPAN9ORgEG7 A0h40t5FgFcE1ZUAYXvLhvIWz21WsT6H7Rla2kZGBivq4jItiB6+9OlJXo+S9loWW0vJ F+Rst89Utgh8WvNfBdfymuztK9hv9DflaAEKCKiC89mTkfuIzK6jgvMG4ryVv4VV/+Ra AZ5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=/SjfesHXbs8d25Z6pjFleXAP2nPA54RfioXWDpjohz8=; b=Ea71tykxDPGc5RB8X+RYLtVbmPMq2WeJROAG74N77Wn+Zj/2MJ4hGDPSESM8ZxoO6v vif5Sxj5dcUbVn83yrNztAasE3DbmNu+e6MO+FZbFiazHDF55V8qDw9bm5FqHd2OJz50 kpIR8N/z4z7qBclUXzBS0O2Q2fDQeNARNO57iPdC2A/10s8fuELp80szTwZVcXYP3w0M H9jMTruvs5m/3LXaBEMaFsZzOWQBgvx1IP1k6YqihQ5tjWzipOdWIoJ4wUUBbvI3X7V8 nNUXaYQPuq2ldKGc23UaBQWPkiFFtxdcKnh2M8uOp11nh848AgZoqAHmJGQruRb9QNmD 2lWQ== X-Gm-Message-State: ALKqPwenzT0L45KUxOKC6CkrqUnVCPP+VUDSz9JHlvbLdFYPbSvFme9H TyEzpI0zDAhJNlvlUc6rSsOGLCVM870= X-Google-Smtp-Source: AB8JxZpv59pCUwWMU39Sn9/AfoMoH7jUrwh/ACTFLaXPulDcU9qUfmzUOjqXk86bpWjvPZSli4P18A== X-Received: by 2002:a62:d044:: with SMTP id p65-v6mr605654pfg.64.1527034657413; Tue, 22 May 2018 17:17:37 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Wed, 23 May 2018 12:15:01 +1200 Message-Id: <1527034517-7851-15-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1527034517-7851-1-git-send-email-mjc@sifive.com> References: <1527034517-7851-1-git-send-email-mjc@sifive.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [PATCH v1 14/30] RISC-V: Add public API for the CSR dispatch table X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Bastian Koppelmann , Palmer Dabbelt , Michael Clark , Alistair Francis , patches@groups.riscv.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This allows hardware and/or derived cpu instances to override or implement new CSR operations. Cc: Sagar Karandikar Cc: Bastian Koppelmann Cc: Palmer Dabbelt Cc: Alistair Francis Signed-off-by: Michael Clark --- target/riscv/cpu.h | 18 ++++++++++++++++++ target/riscv/csr.c | 35 ++++++++++++++++++----------------- 2 files changed, 36 insertions(+), 17 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 242a8fcbe180..1ade90d23bbc 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -307,6 +307,24 @@ static inline target_ulong csr_read_helper(CPURISCVSta= te *env, int csrno) return val; } =20 +typedef int (*riscv_csr_predicate_fn)(CPURISCVState *env, int csrno); +typedef int (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, + target_ulong *ret_value); +typedef int (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, + target_ulong new_value); +typedef int (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, + target_ulong *ret_value, target_ulong new_value, target_ulong write_ma= sk); + +typedef struct { + riscv_csr_predicate_fn predicate; + riscv_csr_read_fn read; + riscv_csr_write_fn write; + riscv_csr_op_fn op; +} riscv_csr_operations; + +void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); +void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); + #include "exec/cpu-all.h" =20 #endif /* RISCV_CPU_H */ diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 509215327243..0f886e04b130 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -23,28 +23,29 @@ #include "qemu/main-loop.h" #include "exec/exec-all.h" =20 +/* CSR function table */ =20 -/* Control and Status Register function table forward declaration */ +static riscv_csr_operations csr_ops[]; =20 -typedef int (*riscv_csr_predicate_fn)(CPURISCVState *env, int csrno); -typedef int (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, - target_ulong *ret_value); -typedef int (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, - target_ulong new_value); -typedef int (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, - target_ulong *ret_value, target_ulong new_value, target_ulong write_ma= sk); +/* CSR function table constants */ =20 -typedef struct { - riscv_csr_predicate_fn predicate; - riscv_csr_read_fn read; - riscv_csr_write_fn write; - riscv_csr_op_fn op; -} riscv_csr_operations; +enum { + CSR_TABLE_SIZE =3D 0xfff +}; + +/* CSR function table public API */ =20 -static const riscv_csr_operations csr_ops[]; +void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops) +{ + *ops =3D csr_ops[csrno & CSR_TABLE_SIZE]; +} =20 +void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops) +{ + csr_ops[csrno & CSR_TABLE_SIZE] =3D *ops; +} =20 -/* Predicates */ +/* CSR function table predicates (private) */ =20 static int fs(CPURISCVState *env, int csrno) { @@ -784,7 +785,7 @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_u= long *ret_value, =20 /* Control and Status Register function table */ =20 -static const riscv_csr_operations csr_ops[0xfff] =3D { +static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { /* User Floating-Point CSRs */ [CSR_FFLAGS] =3D { fs, read_fflags, write_fflags = }, [CSR_FRM] =3D { fs, read_frm, write_frm = }, --=20 2.7.0