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X-Received-From: 2607:f8b0:400e:c01::244 Subject: [Qemu-devel] [PATCH v1 09/30] RISC-V: Implement atomic mip/sip CSR updates X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Bastian Koppelmann , Palmer Dabbelt , Michael Clark , Alistair Francis , patches@groups.riscv.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Use the new CSR read/modify/write interface to implement atomic updates to mip/sip. Cc: Sagar Karandikar Cc: Bastian Koppelmann Cc: Palmer Dabbelt Cc: Alistair Francis Signed-off-by: Michael Clark Acked-by: Alistair Francis --- target/riscv/csr.c | 56 +++++++++++++++++++++++++++-----------------------= ---- 1 file changed, 28 insertions(+), 28 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index e08f3523d854..631a5ff9f7d8 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -493,25 +493,31 @@ static int write_mbadaddr(CPURISCVState *env, int csr= no, target_ulong val) return 0; } =20 -static int read_mip(CPURISCVState *env, int csrno, target_ulong *val) -{ - *val =3D atomic_read(&env->mip); - return 0; -} - -static int write_mip(CPURISCVState *env, int csrno, target_ulong val) +static int rmw_mip(CPURISCVState *env, int csrno, target_ulong *ret_value, + target_ulong new_value, target_ulong write_mask) { RISCVCPU *cpu =3D riscv_env_get_cpu(env); + target_ulong mask =3D write_mask & delegable_ints; + uint32_t old_mip; + + /* We can't allow the supervisor to control SEIP as this would allow t= he + * supervisor to clear a pending external interrupt which will result = in + * lost a interrupt in the case a PLIC is attached. The SEIP bit must = be + * hardware controlled when a PLIC is attached. This should be an opti= on + * for CPUs with software-delegated Supervisor External Interrupts. */ + mask &=3D ~MIP_SEIP; + + if (mask) { + qemu_mutex_lock_iothread(); + old_mip =3D riscv_cpu_update_mip(cpu, mask, (new_value & mask)); + qemu_mutex_unlock_iothread(); + } else { + old_mip =3D atomic_read(&env->mip); + } =20 - /* - * csrs, csrc on mip.SEIP is not decomposable into separate read and - * write steps, so a different implementation is needed - */ - - qemu_mutex_lock_iothread(); - riscv_cpu_update_mip(cpu, MIP_SSIP | MIP_STIP, - (val & (MIP_SSIP | MIP_STIP))); - qemu_mutex_unlock_iothread(); + if (ret_value) { + *ret_value =3D old_mip; + } =20 return 0; } @@ -631,17 +637,11 @@ static int write_sbadaddr(CPURISCVState *env, int csr= no, target_ulong val) return 0; } =20 -static int read_sip(CPURISCVState *env, int csrno, target_ulong *val) -{ - *val =3D atomic_read(&env->mip) & env->mideleg; - return 0; -} - -static int write_sip(CPURISCVState *env, int csrno, target_ulong val) +static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value, + target_ulong new_value, target_ulong write_mask) { - target_ulong newval =3D (atomic_read(&env->mip) & ~env->mideleg) - | (val & env->mideleg); - return write_mip(env, CSR_MIP, newval); + return rmw_mip(env, CSR_MSTATUS, ret_value, new_value, + write_mask & env->mideleg); } =20 /* Supervisor Protection and Translation */ @@ -823,7 +823,7 @@ static const riscv_csr_operations csr_ops[0xfff] =3D { [CSR_MEPC] =3D { read_mepc, write_mepc }, [CSR_MCAUSE] =3D { read_mcause, write_mcause }, [CSR_MBADADDR] =3D { read_mbadaddr, write_mbadaddr }, - [CSR_MIP] =3D { read_mip, write_mip }, + [CSR_MIP] =3D { NULL, NULL, rmw_mip }, =20 /* Supervisor Trap Setup */ [CSR_SSTATUS] =3D { read_sstatus, write_sstatus }, @@ -836,7 +836,7 @@ static const riscv_csr_operations csr_ops[0xfff] =3D { [CSR_SEPC] =3D { read_sepc, write_sepc }, [CSR_SCAUSE] =3D { read_scause, write_scause }, [CSR_SBADADDR] =3D { read_sbadaddr, write_sbadaddr }, - [CSR_SIP] =3D { read_sip, write_sip }, + [CSR_SIP] =3D { NULL, NULL, rmw_sip }, =20 /* Supervisor Protection and Translation */ [CSR_SATP] =3D { read_satp, write_satp }, --=20 2.7.0