From nobody Sun Apr 28 21:14:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526801505356882.6809591900438; Sun, 20 May 2018 00:31:45 -0700 (PDT) Received: from localhost ([::1]:45531 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fKIoX-0002zS-8w for importer@patchew.org; Sun, 20 May 2018 03:31:33 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52328) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fKImN-0000nQ-VI for qemu-devel@nongnu.org; Sun, 20 May 2018 03:29:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fKImM-0006vh-Gk for qemu-devel@nongnu.org; Sun, 20 May 2018 03:29:19 -0400 Received: from mail-pf0-x22a.google.com ([2607:f8b0:400e:c00::22a]:39142) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fKImM-0006vR-8z for qemu-devel@nongnu.org; Sun, 20 May 2018 03:29:18 -0400 Received: by mail-pf0-x22a.google.com with SMTP id a22-v6so5605041pfn.6 for ; Sun, 20 May 2018 00:29:18 -0700 (PDT) Received: from biggerfish-TM1701.lan ([203.69.105.4]) by smtp.gmail.com with ESMTPSA id j3-v6sm17338975pgs.76.2018.05.20.00.29.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 20 May 2018 00:29:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=N36BuP71NBMRr6iBuz5bSASyjIFYKdsi+77E9kfMQWE=; b=m62BBdBonyD1JFamqm17oTH2foEd4A7JoeXBhgQLEKqXlMk3MMoNS4ICweORy0TMqX 5NOoi6aoWZ14kIfnNfFluHWSnH3EqNVnOuUMsh8Y92wYq1HXV95Z1+7Q4XdfP4eQhOB1 MKXbEVK5fs6OMSBI4CGgkGJCbsisJCDvcCsJwtbCAsrXB0r7/QHSFmOO9+4m6uZFzdTt GUJUhPel6HKJV6xzVgYzFRLP0OPphQvFMWmnOY6eiw/BeKdFu2uHOiDUgrxyetY0AY/j deOdeD0WcfN2zcE1gm+3xiZ1JMR6DWkYnb/u2Q4GEMtGOYG80pbXZkFGgx1EOzHeBrmF thag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=N36BuP71NBMRr6iBuz5bSASyjIFYKdsi+77E9kfMQWE=; b=ix7iNjbPLP0hT6HwEFCyZ9tZ6L5Gg9csiK7iuXaYypbabMJbap18cLX0HAqK1MUhRC M2insYVPTf3lQ/Cdjm1PXGk9gKQI0bUR4GDIXc8Q5bLyafEqeUBhlin4c0c9ULQhcQWE IMIIbSpUKlU/732no4qozxBivPC4fOe0b2AV3DYGk3P8JduLmMgz5WLLhmEFvMT98Mhg UNenBaj5fA6GAA2LPzAPKoeNkKbt0aRYFd5Ga37bTWHNlUdrbdYGj6ayjDc5qiUBPGKx Qq3olvGXPmcBXVDy1vI1tLtgcYub6NnTZOaECMJznqILRf3k+g8loqtgraFojfu+HWf1 rwdQ== X-Gm-Message-State: ALKqPwffi6Fck3j9PorerO2htCT5sFgwf2Mn+E+t5r8/7K1FYQIk8OIY Fg9iTn33K/va16u6pafOda655+Da X-Google-Smtp-Source: AB8JxZp/llrysxAHIShoHFJTetPHA6ApadnsLPa1ctyM3ceXMQATMbG2W2EEPeDNotN1trZeuV790Q== X-Received: by 2002:a63:18a:: with SMTP id 132-v6mr12516098pgb.344.1526801356898; Sun, 20 May 2018 00:29:16 -0700 (PDT) From: Zihan Yang To: qemu-devel@nongnu.org Date: Sun, 20 May 2018 15:28:51 +0800 Message-Id: <1526801333-30613-2-git-send-email-whois.zihan.yang@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1526801333-30613-1-git-send-email-whois.zihan.yang@gmail.com> References: <1526801333-30613-1-git-send-email-whois.zihan.yang@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22a Subject: [Qemu-devel] [RFC 1/3] pci_expander_bridge: reserve enough mcfg space for pxb host X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , Zihan Yang , "Michael S. Tsirkin" , Paolo Bonzini , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" To put each pxb into separate pci domain, we need to reserve enough MCFG sp= ace for each pxb host in the main memory. First try to put them under 4G, before pci_hole_start, if there are too many hosts, try to put them into main memo= ry above 4G, before pci_hole64_start. We should check if there is enough memory to reserve for them Signed-off-by: Zihan Yang --- hw/i386/pc.c | 5 ++ hw/pci-bridge/pci_expander_bridge.c | 96 +++++++++++++++++++++++++= +++- include/hw/pci-bridge/pci_expander_bridge.h | 7 +++ 3 files changed, 107 insertions(+), 1 deletion(-) create mode 100644 include/hw/pci-bridge/pci_expander_bridge.h diff --git a/hw/i386/pc.c b/hw/i386/pc.c index d768930..98097fd 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -34,6 +34,7 @@ #include "hw/ide.h" #include "hw/pci/pci.h" #include "hw/pci/pci_bus.h" +#include "hw/pci-bridge/pci_expander_bridge.h" #include "hw/nvram/fw_cfg.h" #include "hw/timer/hpet.h" #include "hw/smbios/smbios.h" @@ -1466,6 +1467,7 @@ uint64_t pc_pci_hole64_start(void) PCMachineClass *pcmc =3D PC_MACHINE_GET_CLASS(pcms); MachineState *ms =3D MACHINE(pcms); uint64_t hole64_start =3D 0; + int pxb_hosts; =20 if (pcmc->has_reserved_memory && ms->device_memory->base) { hole64_start =3D ms->device_memory->base; @@ -1473,6 +1475,9 @@ uint64_t pc_pci_hole64_start(void) hole64_start +=3D memory_region_size(&ms->device_memory->mr); } } else { + /* make sure enough space is left for pxb host, otherwise fail */ + pxb_hosts =3D pxb_get_expander_hosts(); + g_assert (pxb_hosts <=3D 0 || pcms->above_4g_mem_size >=3D (pxb_ho= sts << 28ULL)); hole64_start =3D 0x100000000ULL + pcms->above_4g_mem_size; } =20 diff --git a/hw/pci-bridge/pci_expander_bridge.c b/hw/pci-bridge/pci_expand= er_bridge.c index e62de42..8409c87 100644 --- a/hw/pci-bridge/pci_expander_bridge.c +++ b/hw/pci-bridge/pci_expander_bridge.c @@ -12,10 +12,13 @@ =20 #include "qemu/osdep.h" #include "qapi/error.h" +#include "qapi/visitor.h" #include "hw/pci/pci.h" #include "hw/pci/pci_bus.h" #include "hw/pci/pci_host.h" #include "hw/pci/pci_bridge.h" +#include "hw/pci-host/q35.h" +#include "hw/pci-bridge/pci_expander_bridge.h" #include "qemu/range.h" #include "qemu/error-report.h" #include "sysemu/numa.h" @@ -57,7 +60,13 @@ static PXBDev *convert_to_pxb(PCIDevice *dev) =20 static GList *pxb_dev_list; =20 +typedef struct PXBPCIHost { + PCIExpressHost parent_obj; +} PXBPCIHost; + #define TYPE_PXB_HOST "pxb-host" +#define PXB_HOST_DEVICE(obj) \ + OBJECT_CHECK(PXBPCIHost, (obj), TYPE_PXB_HOST) =20 static int pxb_bus_num(PCIBus *bus) { @@ -111,6 +120,14 @@ static const char *pxb_host_root_bus_path(PCIHostState= *host_bridge, return bus->bus_path; } =20 +static void pxb_host_get_mmcfg_size(Object *obj, Visitor *v, const char *n= ame, + void *opaque, Error **errp) +{ + PCIExpressHost *e =3D PCIE_HOST_BRIDGE(obj); + + visit_type_uint64(v, name, &e->size, errp); +} + static char *pxb_host_ofw_unit_address(const SysBusDevice *dev) { const PCIHostState *pxb_host; @@ -142,6 +159,80 @@ static char *pxb_host_ofw_unit_address(const SysBusDev= ice *dev) return NULL; } =20 +static Object *pxb_get_i386_pci_host(void) +{ + PCIHostState *host; + + host =3D OBJECT_CHECK(PCIHostState, + object_resolve_path("/machine/i440fx", NULL), + TYPE_PCI_HOST_BRIDGE); + if (!host) { + host =3D OBJECT_CHECK(PCIHostState, + object_resolve_path("/machine/q35", NULL), + TYPE_PCI_HOST_BRIDGE); + } + + return OBJECT(host); +} + +int pxhb_cnt =3D 0; + +/* -1 means to exclude q35 host */ +#define MCFG_IN_PCI_HOLE (((IO_APIC_DEFAULT_ADDRESS - MCH_HOST_BRIDGE_PCIE= XBAR_DEFAULT) >> 28) - 1) + +int pxb_get_expander_hosts(void) +{ + return pxhb_cnt - MCFG_IN_PCI_HOLE; +} + +/* Dirty workaround */ +static void modify_q35_pci_hole(void) +{ + Object *pci_host; + Q35PCIHost *s; + + pci_host =3D pxb_get_i386_pci_host(); + g_assert(pci_host); + s =3D Q35_HOST_DEVICE(pci_host); + + ++pxhb_cnt; + if (pxhb_cnt <=3D MCFG_IN_PCI_HOLE) { + range_set_bounds(&s->mch.pci_hole, + MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT + ((1 + pxhb_cnt) << 28), + IO_APIC_DEFAULT_ADDRESS - 1); + } + + // leave pci hole64 to acpi build part +} + +static void pxb_host_initfn(Object *obj) +{ + PCIHostState *phb =3D PCI_HOST_BRIDGE(obj); + + memory_region_init_io(&phb->conf_mem, obj, &pci_host_conf_le_ops, phb, + "pci-conf-idx", 4); + memory_region_init_io(&phb->data_mem, obj, &pci_host_data_le_ops, phb, + "pci-conf-data", 4); + + object_property_add(obj, PCIE_HOST_MCFG_SIZE, "uint64", + pxb_host_get_mmcfg_size, + NULL, NULL, NULL, NULL); + + /* Leave enough space for the biggest MCFG BAR */ + /* TODO. Since pxb host is just an expander bridge without an mch, + * we modify the range in q35 host. It should be workable as it is + * before acpi build, although it is dirty + */ + modify_q35_pci_hole(); +} + +/* default value does not matter as guest firmware will overwrite it */ +static Property pxb_host_props[] =3D { + DEFINE_PROP_UINT64(PCIE_HOST_MCFG_BASE, PXBPCIHost, parent_obj.base_ad= dr, + MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT), + DEFINE_PROP_END_OF_LIST(), +}; + static void pxb_host_class_init(ObjectClass *class, void *data) { DeviceClass *dc =3D DEVICE_CLASS(class); @@ -149,6 +240,7 @@ static void pxb_host_class_init(ObjectClass *class, voi= d *data) PCIHostBridgeClass *hc =3D PCI_HOST_BRIDGE_CLASS(class); =20 dc->fw_name =3D "pci"; + dc->props =3D pxb_host_props; /* Reason: Internal part of the pxb/pxb-pcie device, not usable by its= elf */ dc->user_creatable =3D false; sbc->explicit_ofw_unit_address =3D pxb_host_ofw_unit_address; @@ -157,7 +249,9 @@ static void pxb_host_class_init(ObjectClass *class, voi= d *data) =20 static const TypeInfo pxb_host_info =3D { .name =3D TYPE_PXB_HOST, - .parent =3D TYPE_PCI_HOST_BRIDGE, + .parent =3D TYPE_PCIE_HOST_BRIDGE, + .instance_size =3D sizeof(PXBPCIHost), + .instance_init =3D pxb_host_initfn, .class_init =3D pxb_host_class_init, }; =20 diff --git a/include/hw/pci-bridge/pci_expander_bridge.h b/include/hw/pci-b= ridge/pci_expander_bridge.h new file mode 100644 index 0000000..d48ddb1 --- /dev/null +++ b/include/hw/pci-bridge/pci_expander_bridge.h @@ -0,0 +1,7 @@ +#ifndef HW_PCI_EXPANDER_H +#define HW_PCI_EXPANDER_H + +/* return the number of pxb hosts that resides in the main memory above 4G= */ +int pxb_get_expander_hosts(void); + +#endif --=20 2.7.4 From nobody Sun Apr 28 21:14:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526801513292727.1223266594974; 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Sun, 20 May 2018 00:29:22 -0700 (PDT) From: Zihan Yang To: qemu-devel@nongnu.org Date: Sun, 20 May 2018 15:28:52 +0800 Message-Id: <1526801333-30613-3-git-send-email-whois.zihan.yang@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1526801333-30613-1-git-send-email-whois.zihan.yang@gmail.com> References: <1526801333-30613-1-git-send-email-whois.zihan.yang@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::242 Subject: [Qemu-devel] [RFC 2/3] pci: Link pci_host_bridges with QTAILQ X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Zihan Yang , "Michael S. Tsirkin" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" QLIST will place the original q35 host bridge at the end of list because it= is added first. Replace it with QTAILQ to make q35 at the first of queue, which makes it convinient and compatible when there are pxb hosts other than q35 = hosts Signed-off-by: Zihan Yang --- hw/pci/pci.c | 9 +++++---- include/hw/pci/pci_host.h | 2 +- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 80bc459..ddc27ba 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -196,7 +196,8 @@ static void pci_del_option_rom(PCIDevice *pdev); static uint16_t pci_default_sub_vendor_id =3D PCI_SUBVENDOR_ID_REDHAT_QUMR= ANET; static uint16_t pci_default_sub_device_id =3D PCI_SUBDEVICE_ID_QEMU; =20 -static QLIST_HEAD(, PCIHostState) pci_host_bridges; +static QTAILQ_HEAD(, PCIHostState) pci_host_bridges =3D + QTAILQ_HEAD_INITIALIZER(pci_host_bridges); =20 int pci_bar(PCIDevice *d, int reg) { @@ -330,7 +331,7 @@ static void pci_host_bus_register(DeviceState *host) { PCIHostState *host_bridge =3D PCI_HOST_BRIDGE(host); =20 - QLIST_INSERT_HEAD(&pci_host_bridges, host_bridge, next); + QTAILQ_INSERT_TAIL(&pci_host_bridges, host_bridge, next); } =20 PCIBus *pci_device_root_bus(const PCIDevice *d) @@ -1798,7 +1799,7 @@ PciInfoList *qmp_query_pci(Error **errp) PciInfoList *info, *head =3D NULL, *cur_item =3D NULL; PCIHostState *host_bridge; =20 - QLIST_FOREACH(host_bridge, &pci_host_bridges, next) { + QTAILQ_FOREACH(host_bridge, &pci_host_bridges, next) { info =3D g_malloc0(sizeof(*info)); info->value =3D qmp_query_pci_bus(host_bridge->bus, pci_bus_num(host_bridge->bus)); @@ -2493,7 +2494,7 @@ int pci_qdev_find_device(const char *id, PCIDevice **= pdev) PCIHostState *host_bridge; int rc =3D -ENODEV; =20 - QLIST_FOREACH(host_bridge, &pci_host_bridges, next) { + QTAILQ_FOREACH(host_bridge, &pci_host_bridges, next) { int tmp =3D pci_qdev_find_recursive(host_bridge->bus, id, pdev); if (!tmp) { rc =3D 0; diff --git a/include/hw/pci/pci_host.h b/include/hw/pci/pci_host.h index ba31595..a5617cf 100644 --- a/include/hw/pci/pci_host.h +++ b/include/hw/pci/pci_host.h @@ -47,7 +47,7 @@ struct PCIHostState { uint32_t config_reg; PCIBus *bus; =20 - QLIST_ENTRY(PCIHostState) next; + QTAILQ_ENTRY(PCIHostState) next; }; =20 typedef struct PCIHostBridgeClass { --=20 2.7.4 From nobody Sun Apr 28 21:14:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1526801626066492.8141094172438; Sun, 20 May 2018 00:33:46 -0700 (PDT) Received: from localhost ([::1]:45543 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fKIqf-0004Wh-8b for importer@patchew.org; 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Sun, 20 May 2018 00:29:28 -0700 (PDT) From: Zihan Yang To: qemu-devel@nongnu.org Date: Sun, 20 May 2018 15:28:53 +0800 Message-Id: <1526801333-30613-4-git-send-email-whois.zihan.yang@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1526801333-30613-1-git-send-email-whois.zihan.yang@gmail.com> References: <1526801333-30613-1-git-send-email-whois.zihan.yang@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::244 Subject: [Qemu-devel] [RFC 3/3] acpi-build: allocate mcfg for multiple host bridges X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , Zihan Yang , "Michael S. Tsirkin" , Paolo Bonzini , Igor Mammedov , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Currently only q35 host bridge us allocated space in MCFG table. To put pxb= host into sepratate pci domain, each of them should have its own configuration s= pace int MCFG table Signed-off-by: Zihan Yang --- hw/i386/acpi-build.c | 83 +++++++++++++++++++++++++++++++++++++++---------= ---- 1 file changed, 62 insertions(+), 21 deletions(-) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 9bc6d97..808d815 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -89,6 +89,7 @@ typedef struct AcpiMcfgInfo { uint64_t mcfg_base; uint32_t mcfg_size; + struct AcpiMcfgInfo *next; } AcpiMcfgInfo; =20 typedef struct AcpiPmInfo { @@ -2427,14 +2428,15 @@ build_mcfg_q35(GArray *table_data, BIOSLinker *link= er, AcpiMcfgInfo *info) { AcpiTableMcfg *mcfg; const char *sig; - int len =3D sizeof(*mcfg) + 1 * sizeof(mcfg->allocation[0]); + int len, count =3D 0; + AcpiMcfgInfo *cfg =3D info; =20 + while (cfg) { + ++count; + cfg =3D cfg->next; + } + len =3D sizeof(*mcfg) + count * sizeof(mcfg->allocation[0]); mcfg =3D acpi_data_push(table_data, len); - mcfg->allocation[0].address =3D cpu_to_le64(info->mcfg_base); - /* Only a single allocation so no need to play with segments */ - mcfg->allocation[0].pci_segment =3D cpu_to_le16(0); - mcfg->allocation[0].start_bus_number =3D 0; - mcfg->allocation[0].end_bus_number =3D PCIE_MMCFG_BUS(info->mcfg_size = - 1); =20 /* MCFG is used for ECAM which can be enabled or disabled by guest. * To avoid table size changes (which create migration issues), @@ -2448,6 +2450,17 @@ build_mcfg_q35(GArray *table_data, BIOSLinker *linke= r, AcpiMcfgInfo *info) } else { sig =3D "MCFG"; } + + count =3D 0; + while (info) { + mcfg[count].allocation[0].address =3D cpu_to_le64(info->mcfg_base); + /* Only a single allocation so no need to play with segments */ + mcfg[count].allocation[0].pci_segment =3D cpu_to_le16(count); + mcfg[count].allocation[0].start_bus_number =3D 0; + mcfg[count++].allocation[0].end_bus_number =3D PCIE_MMCFG_BUS(info= ->mcfg_size - 1); + info =3D info->next; + } + build_header(linker, table_data, (void *)mcfg, sig, len, 1, NULL, NULL= ); } =20 @@ -2602,26 +2615,52 @@ struct AcpiBuildState { MemoryRegion *linker_mr; } AcpiBuildState; =20 -static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg) +static inline void cleanup_mcfg(AcpiMcfgInfo *mcfg) +{ + AcpiMcfgInfo *tmp; + while (mcfg) { + tmp =3D mcfg->next; + g_free(mcfg); + mcfg =3D tmp; + } +} + +static AcpiMcfgInfo *acpi_get_mcfg(void) { Object *pci_host; QObject *o; + AcpiMcfgInfo *head =3D NULL, *tail, *mcfg; =20 pci_host =3D acpi_get_i386_pci_host(); g_assert(pci_host); =20 - o =3D object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL); - if (!o) { - return false; + while (pci_host) { + mcfg =3D g_new0(AcpiMcfgInfo, 1); + mcfg->next =3D NULL; + if (!head) { + tail =3D head =3D mcfg; + } else { + tail->next =3D mcfg; + tail =3D mcfg; + } + + o =3D object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, N= ULL); + if (!o) { + cleanup_mcfg(head); + g_free(mcfg); + return NULL; + } + mcfg->mcfg_base =3D qnum_get_uint(qobject_to(QNum, o)); + qobject_unref(o); + + o =3D object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, N= ULL); + assert(o); + mcfg->mcfg_size =3D qnum_get_uint(qobject_to(QNum, o)); + qobject_unref(o); + + pci_host =3D OBJECT(QTAILQ_NEXT(PCI_HOST_BRIDGE(pci_host), next)); } - mcfg->mcfg_base =3D qnum_get_uint(qobject_to(QNum, o)); - qobject_unref(o); - - o =3D object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL); - assert(o); - mcfg->mcfg_size =3D qnum_get_uint(qobject_to(QNum, o)); - qobject_unref(o); - return true; + return head; } =20 static @@ -2633,7 +2672,7 @@ void acpi_build(AcpiBuildTables *tables, MachineState= *machine) unsigned facs, dsdt, rsdt, fadt; AcpiPmInfo pm; AcpiMiscInfo misc; - AcpiMcfgInfo mcfg; + AcpiMcfgInfo *mcfg; Range pci_hole, pci_hole64; uint8_t *u; size_t aml_len =3D 0; @@ -2714,10 +2753,12 @@ void acpi_build(AcpiBuildTables *tables, MachineSta= te *machine) build_slit(tables_blob, tables->linker); } } - if (acpi_get_mcfg(&mcfg)) { + if ((mcfg =3D acpi_get_mcfg()) !=3D NULL) { acpi_add_table(table_offsets, tables_blob); - build_mcfg_q35(tables_blob, tables->linker, &mcfg); + build_mcfg_q35(tables_blob, tables->linker, mcfg); } + cleanup_mcfg(mcfg); + if (x86_iommu_get_default()) { IommuType IOMMUType =3D x86_iommu_get_type(); if (IOMMUType =3D=3D TYPE_AMD) { --=20 2.7.4