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X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PATCH v1 5/6] target/riscv: convert to TranslatorOps X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Bastian Koppelmann , Palmer Dabbelt , "Emilio G. Cota" , patches@groups.riscv.org, Michael Clark Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Emilio G. Cota" Reviewed-by: Richard Henderson Cc: Michael Clark Cc: Palmer Dabbelt Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Emilio G. Cota --- target/riscv/translate.c | 158 ++++++++++++++++++++++++-------------------= ---- 1 file changed, 80 insertions(+), 78 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 68979abfd7ed..1788668c6f28 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1837,78 +1837,71 @@ static void decode_opc(CPURISCVState *env, DisasCon= text *ctx) } } =20 -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) +static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState= *cs) { - CPURISCVState *env =3D cs->env_ptr; - DisasContext ctx; - target_ulong page_start; - int num_insns; - int max_insns; - - ctx.base.pc_first =3D tb->pc; - ctx.base.pc_next =3D ctx.base.pc_first; - /* once we have GDB, the rest of the translate.c implementation should= be - ready for singlestep */ - ctx.base.singlestep_enabled =3D cs->singlestep_enabled; - ctx.base.tb =3D tb; - ctx.base.is_jmp =3D DISAS_NEXT; - - page_start =3D ctx.base.pc_first & TARGET_PAGE_MASK; - ctx.pc_succ_insn =3D ctx.base.pc_first; - ctx.flags =3D tb->flags; - ctx.mem_idx =3D tb->flags & TB_FLAGS_MMU_MASK; - ctx.frm =3D -1; /* unknown rounding mode */ - - num_insns =3D 0; - max_insns =3D tb_cflags(ctx.base.tb) & CF_COUNT_MASK; - if (max_insns =3D=3D 0) { - max_insns =3D CF_COUNT_MASK; - } - if (max_insns > TCG_MAX_INSNS) { - max_insns =3D TCG_MAX_INSNS; - } - gen_tb_start(tb); + DisasContext *ctx =3D container_of(dcbase, DisasContext, base); =20 - while (ctx.base.is_jmp =3D=3D DISAS_NEXT) { - tcg_gen_insn_start(ctx.base.pc_next); - num_insns++; + ctx->pc_succ_insn =3D ctx->base.pc_first; + ctx->flags =3D ctx->base.tb->flags; + ctx->mem_idx =3D ctx->base.tb->flags & TB_FLAGS_MMU_MASK; + ctx->frm =3D -1; /* unknown rounding mode */ +} =20 - if (unlikely(cpu_breakpoint_test(cs, ctx.base.pc_next, BP_ANY))) { - tcg_gen_movi_tl(cpu_pc, ctx.base.pc_next); - ctx.base.is_jmp =3D DISAS_NORETURN; - gen_exception_debug(); - /* The address covered by the breakpoint must be included in - [tb->pc, tb->pc + tb->size) in order to for it to be - properly cleared -- thus we increment the PC here so that - the logic setting tb->size below does the right thing. */ - ctx.base.pc_next +=3D 4; - goto done_generating; - } +static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) +{ +} =20 - if (num_insns =3D=3D max_insns && (tb_cflags(ctx.base.tb) & CF_LAS= T_IO)) { - gen_io_start(); - } +static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *ctx =3D container_of(dcbase, DisasContext, base); + + tcg_gen_insn_start(ctx->base.pc_next); +} + +static bool riscv_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *= cpu, + const CPUBreakpoint *bp) +{ + DisasContext *ctx =3D container_of(dcbase, DisasContext, base); + + tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); + ctx->base.is_jmp =3D DISAS_NORETURN; + gen_exception_debug(); + /* The address covered by the breakpoint must be included in + [tb->pc, tb->pc + tb->size) in order to for it to be + properly cleared -- thus we increment the PC here so that + the logic setting tb->size below does the right thing. */ + ctx->base.pc_next +=3D 4; + return true; +} + + +static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cp= u) +{ + DisasContext *ctx =3D container_of(dcbase, DisasContext, base); + CPURISCVState *env =3D cpu->env_ptr; =20 - ctx.opcode =3D cpu_ldl_code(env, ctx.base.pc_next); - decode_opc(env, &ctx); - ctx.base.pc_next =3D ctx.pc_succ_insn; - - if (ctx.base.is_jmp =3D=3D DISAS_NEXT && - (cs->singlestep_enabled || - ctx.base.pc_next - page_start >=3D TARGET_PAGE_SIZE || - tcg_op_buf_full() || - num_insns >=3D max_insns || - singlestep)) { - ctx.base.is_jmp =3D DISAS_TOO_MANY; + ctx->opcode =3D cpu_ldl_code(env, ctx->base.pc_next); + decode_opc(env, ctx); + ctx->base.pc_next =3D ctx->pc_succ_insn; + + if (ctx->base.is_jmp =3D=3D DISAS_NEXT) { + target_ulong page_start; + + page_start =3D ctx->base.pc_first & TARGET_PAGE_MASK; + if (ctx->base.pc_next - page_start >=3D TARGET_PAGE_SIZE) { + ctx->base.is_jmp =3D DISAS_TOO_MANY; } } - if (tb_cflags(ctx.base.tb) & CF_LAST_IO) { - gen_io_end(); - } - switch (ctx.base.is_jmp) { +} + +static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *ctx =3D container_of(dcbase, DisasContext, base); + + switch (ctx->base.is_jmp) { case DISAS_TOO_MANY: - tcg_gen_movi_tl(cpu_pc, ctx.base.pc_next); - if (cs->singlestep_enabled) { + tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); + if (ctx->base.singlestep_enabled) { gen_exception_debug(); } else { tcg_gen_exit_tb(0); @@ -1919,20 +1912,29 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) default: g_assert_not_reached(); } -done_generating: - gen_tb_end(tb, num_insns); - tb->size =3D ctx.base.pc_next - ctx.base.pc_first; - tb->icount =3D num_insns; - -#ifdef DEBUG_DISAS - if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) - && qemu_log_in_addr_range(ctx.base.pc_first)) { - qemu_log("IN: %s\n", lookup_symbol(ctx.base.pc_first)); - log_target_disas(cs, ctx.base.pc_first, - ctx.base.pc_next - ctx.base.pc_first); - qemu_log("\n"); - } -#endif +} + +static void riscv_tr_disas_log(const DisasContextBase *dcbase, CPUState *c= pu) +{ + qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); + log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size); +} + +static const TranslatorOps riscv_tr_ops =3D { + .init_disas_context =3D riscv_tr_init_disas_context, + .tb_start =3D riscv_tr_tb_start, + .insn_start =3D riscv_tr_insn_start, + .breakpoint_check =3D riscv_tr_breakpoint_check, + .translate_insn =3D riscv_tr_translate_insn, + .tb_stop =3D riscv_tr_tb_stop, + .disas_log =3D riscv_tr_disas_log, +}; + +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) +{ + DisasContext ctx; + + translator_loop(&riscv_tr_ops, &ctx.base, cs, tb); } =20 void riscv_translate_init(void) --=20 2.7.0