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[122.58.167.38]) by smtp.gmail.com with ESMTPSA id q22sm20610396pfk.4.2018.05.09.03.13.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 09 May 2018 03:13:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Ffc6sMIUHzulrCCnCg1SEbhj+qKmFDivw3uGFoH8RVQ=; b=GqYku2U3K+QFoPq126G2AZNFmYdfbT8EPkpBGmOPUxCN4uNDdjxR14jaj4yeFPUpHt Zv9pCD2D9+iUob6DVY0VjwoMZ1TzjMwdWGWFpBUFSvcfo8pbV5berznoo/uTRK0IU9Fq vbxEH1nOZwbFa3TC2d+GOdGRUgVMumoVo+ghezUZZMDxHgfVnby52muk3ahb/bmYWhMm GT5zkfPI1RkJaUXr0OmUzo2Xkn3UhLOM7jdDN/HOwW6DE25Fxu8aoSU1IziK/WM2Wz7k K8golsJcZteIhrsHW/ED7ja6GlJ9wZ5JCPa19kMmFjtUU8CwX92OCNATeNj3908RvPZh omIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Ffc6sMIUHzulrCCnCg1SEbhj+qKmFDivw3uGFoH8RVQ=; b=X9zM0L+k9U49KyRSH3OgtKgreCmnye2gLwSbwWV61CPmMQ++hGtHBFUIuGoLg6wApg IkrgbaNiUq6Rt5SV6OJEDoqDITEKHL+91xURMf3HdFjeuYqvpa/Gtym0MqRqjgnltvzz mFqmK3YPi+NsWv2rVuA8mNCOULzEqEwOeK81uMkDRoRgsycAc+A5hsu4wrmonYGTn6Sq wu7cJHovp8iTZzvSOiJ9I8t88hkhBzqA0G5xQrG5jVZpA8p2DDtiES9KMyLoNIGtz5xj TR6QqLkktPa0p516RbpNLzWE3PCOfefxl6NTXpk4KyvHvXFeFj4ZzNn4kJsZ9CujiaUh NCxQ== X-Gm-Message-State: ALQs6tA0Sd6ZYimX5NuhyWwKcxOWWgKDfBIQyV/JzV3AJwVAEuQFpP0S L4/Ot4y0oV9jVadOcmKfoLCRl5QuhoY= X-Google-Smtp-Source: AB8JxZoGvlu8e7boP5fn7NM87Qp+FAxBvUeedLwp3fgDGEkT/wx0I5prSufkv+vObXRQP9TRSlUU/w== X-Received: by 2002:a65:5843:: with SMTP id s3-v6mr5072499pgr.323.1525860802649; Wed, 09 May 2018 03:13:22 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Wed, 9 May 2018 22:11:48 +1200 Message-Id: <1525860713-3476-2-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1525860713-3476-1-git-send-email-mjc@sifive.com> References: <1525860713-3476-1-git-send-email-mjc@sifive.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [PATCH v1 1/6] target/riscv: avoid integer overflow in next_page PC check X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Bastian Koppelmann , Palmer Dabbelt , "Emilio G. Cota" , patches@groups.riscv.org, Michael Clark Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Emilio G. Cota" If the PC is in the last page of the address space, next_page_start overflows to 0. Fix it. Reported-by: Richard Henderson Suggested-by: Richard Henderson Reviewed-by: Richard Henderson Reviewed-by: Michael Clark Acked-by: Bastian Koppelmann Cc: Michael Clark Cc: Palmer Dabbelt Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Emilio G. Cota --- target/riscv/translate.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index c0e6a044d383..a98033ca77ca 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1850,11 +1850,11 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) CPURISCVState *env =3D cs->env_ptr; DisasContext ctx; target_ulong pc_start; - target_ulong next_page_start; + target_ulong page_start; int num_insns; int max_insns; pc_start =3D tb->pc; - next_page_start =3D (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; + page_start =3D pc_start & TARGET_PAGE_MASK; ctx.pc =3D pc_start; =20 /* once we have GDB, the rest of the translate.c implementation should= be @@ -1904,7 +1904,7 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb) if (cs->singlestep_enabled) { break; } - if (ctx.pc >=3D next_page_start) { + if (ctx.pc - page_start >=3D TARGET_PAGE_SIZE) { break; } if (tcg_op_buf_full()) { --=20 2.7.0 From nobody Wed Oct 29 11:33:39 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1525861103276681.1395758695098; Wed, 9 May 2018 03:18:23 -0700 (PDT) Received: from localhost ([::1]:55513 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fGMAs-0007hU-PR for importer@patchew.org; Wed, 09 May 2018 06:18:18 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43315) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fGM6C-0003aM-9u for qemu-devel@nongnu.org; Wed, 09 May 2018 06:13:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fGM6A-0006yP-MC for qemu-devel@nongnu.org; Wed, 09 May 2018 06:13:28 -0400 Received: from mail-pf0-x244.google.com ([2607:f8b0:400e:c00::244]:36165) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fGM6A-0006x7-CA for qemu-devel@nongnu.org; Wed, 09 May 2018 06:13:26 -0400 Received: by mail-pf0-x244.google.com with SMTP id w129so19972021pfd.3 for ; Wed, 09 May 2018 03:13:26 -0700 (PDT) Received: from localhost.localdomain (122-58-167-38-fibre.bb.spark.co.nz. [122.58.167.38]) by smtp.gmail.com with ESMTPSA id q22sm20610396pfk.4.2018.05.09.03.13.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 09 May 2018 03:13:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=8TlNUxN6zyVojq+fHaouyr6s0GzzjunLDEj2jYU531o=; b=VCf19SviktQYahFcJBxvfK6mGBbPdr7wOPuuROAw8d2Wup2gSnmEKJpyzSqk0nKDvj zTvfBUZcRgkQDVDsd5YrkSZqjd8/zGHzza2C95CjsW5PJ6v1OjsKLCXKMJMIdYgL3dbi E5y94dcysRJ3w3Dl8LKuQ67ioxwKUaN7i33ftnahBmcKJrwGK+TbW1EaphLJf4Et6k03 Tne+P02coJmZl5nUh4zJgN2w4jPhCoNStcFJCNinHrIuB/BbWfESIq9/qw4Q8xG554JN QvE0g0UcnnCGPp6g1IZ8JsZgOBrHR9j9I+wBTCdu3hfKoh6xhn2vwPt2lFEo8qA8vK6U KpZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=8TlNUxN6zyVojq+fHaouyr6s0GzzjunLDEj2jYU531o=; b=XnOw66rGXUFLJvgrdOc7ANgMPXElW+Yn3xGpl4f2x5xCJ6Pjb+X72MTS9k5e6o5fPg PI/ZYe+IqhnHaJyNw82TvxMM5zfvUBaYAbzz6c0Zc6JROpZ6JchOaKWCWOkz88kgRvZL hKydZlqpVtFujUxr7uV+tMN451QvbCJXMj9Wu3jaQOFaMfjj69vhO3SBlVvqNbEUKw91 AvXPU2RndUkCU8iaJ8vtkEj8L8Rzqj/EuyN3RqZaOS+7Hszv1jKHM5UpGmq0VfwOaGlV R6PxeFwaeiDmMcxyiEWZ41b6FiTtZTvWKXw9wshXQHBVhhJsODkJ8qawQQZp8e1YY/vU OeoA== X-Gm-Message-State: ALQs6tDZdh+7MjcM7+2uMGGL4CvVjT5JH/p4eCzrKzS4kahd2/Y9xXSD 8cqWaBezWxBKuR/uxb2vsgcWaSvI42A= X-Google-Smtp-Source: AB8JxZqIj6xc1ig8+AHQbN1vYcSmW+MDvwCblvxS0qK+oNlOv1xs5rwHGpIZIfaz5V5f4HtS54/DcA== X-Received: by 2002:a63:a503:: with SMTP id n3-v6mr35011611pgf.19.1525860805249; Wed, 09 May 2018 03:13:25 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Wed, 9 May 2018 22:11:49 +1200 Message-Id: <1525860713-3476-3-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1525860713-3476-1-git-send-email-mjc@sifive.com> References: <1525860713-3476-1-git-send-email-mjc@sifive.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PATCH v1 2/6] translator: merge max_insns into DisasContextBase X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@groups.riscv.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Emilio G. Cota" While at it, use int for both num_insns and max_insns to make sure we have same-type comparisons. Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota --- accel/tcg/translator.c | 21 ++++++++++----------- include/exec/translator.h | 8 ++++---- target/alpha/translate.c | 6 ++---- target/arm/translate-a64.c | 8 +++----- target/arm/translate.c | 11 ++++------- target/hppa/translate.c | 7 ++----- target/i386/translate.c | 5 +---- target/ppc/translate.c | 5 ++--- 8 files changed, 28 insertions(+), 43 deletions(-) diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index 23c6602cd921..0f9dca911399 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -34,8 +34,6 @@ void translator_loop_temp_check(DisasContextBase *db) void translator_loop(const TranslatorOps *ops, DisasContextBase *db, CPUState *cpu, TranslationBlock *tb) { - int max_insns; - /* Initialize DisasContext */ db->tb =3D tb; db->pc_first =3D tb->pc; @@ -45,18 +43,18 @@ void translator_loop(const TranslatorOps *ops, DisasCon= textBase *db, db->singlestep_enabled =3D cpu->singlestep_enabled; =20 /* Instruction counting */ - max_insns =3D tb_cflags(db->tb) & CF_COUNT_MASK; - if (max_insns =3D=3D 0) { - max_insns =3D CF_COUNT_MASK; + db->max_insns =3D tb_cflags(db->tb) & CF_COUNT_MASK; + if (db->max_insns =3D=3D 0) { + db->max_insns =3D CF_COUNT_MASK; } - if (max_insns > TCG_MAX_INSNS) { - max_insns =3D TCG_MAX_INSNS; + if (db->max_insns > TCG_MAX_INSNS) { + db->max_insns =3D TCG_MAX_INSNS; } if (db->singlestep_enabled || singlestep) { - max_insns =3D 1; + db->max_insns =3D 1; } =20 - max_insns =3D ops->init_disas_context(db, cpu, max_insns); + ops->init_disas_context(db, cpu); tcg_debug_assert(db->is_jmp =3D=3D DISAS_NEXT); /* no early exit */ =20 /* Reset the temp count so that we can identify leaks */ @@ -95,7 +93,8 @@ void translator_loop(const TranslatorOps *ops, DisasConte= xtBase *db, update db->pc_next and db->is_jmp to indicate what should be done next -- either exiting this loop or locate the start of the next instruction. */ - if (db->num_insns =3D=3D max_insns && (tb_cflags(db->tb) & CF_LAST= _IO)) { + if (db->num_insns =3D=3D db->max_insns + && (tb_cflags(db->tb) & CF_LAST_IO)) { /* Accept I/O on the last instruction. */ gen_io_start(); ops->translate_insn(db, cpu); @@ -111,7 +110,7 @@ void translator_loop(const TranslatorOps *ops, DisasCon= textBase *db, =20 /* Stop translation if the output buffer is full, or we have executed all of the allowed instructions. */ - if (tcg_op_buf_full() || db->num_insns >=3D max_insns) { + if (tcg_op_buf_full() || db->num_insns >=3D db->max_insns) { db->is_jmp =3D DISAS_TOO_MANY; break; } diff --git a/include/exec/translator.h b/include/exec/translator.h index e2dc2a04ae37..71e7b2c34714 100644 --- a/include/exec/translator.h +++ b/include/exec/translator.h @@ -58,6 +58,7 @@ typedef enum DisasJumpType { * disassembly). * @is_jmp: What instruction to disassemble next. * @num_insns: Number of translated instructions (including current). + * @max_insns: Maximum number of instructions to be translated in this TB. * @singlestep_enabled: "Hardware" single stepping enabled. * * Architecture-agnostic disassembly context. @@ -67,7 +68,8 @@ typedef struct DisasContextBase { target_ulong pc_first; target_ulong pc_next; DisasJumpType is_jmp; - unsigned int num_insns; + int num_insns; + int max_insns; bool singlestep_enabled; } DisasContextBase; =20 @@ -76,7 +78,6 @@ typedef struct DisasContextBase { * @init_disas_context: * Initialize the target-specific portions of DisasContext struct. * The generic DisasContextBase has already been initialized. - * Return max_insns, modified as necessary by db->tb->flags. * * @tb_start: * Emit any code required before the start of the main loop, @@ -106,8 +107,7 @@ typedef struct DisasContextBase { * Print instruction disassembly to log. */ typedef struct TranslatorOps { - int (*init_disas_context)(DisasContextBase *db, CPUState *cpu, - int max_insns); + void (*init_disas_context)(DisasContextBase *db, CPUState *cpu); void (*tb_start)(DisasContextBase *db, CPUState *cpu); void (*insn_start)(DisasContextBase *db, CPUState *cpu); bool (*breakpoint_check)(DisasContextBase *db, CPUState *cpu, diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 73a1b5e63ed1..15eca71d49f7 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -2919,8 +2919,7 @@ static DisasJumpType translate_one(DisasContext *ctx,= uint32_t insn) return ret; } =20 -static int alpha_tr_init_disas_context(DisasContextBase *dcbase, - CPUState *cpu, int max_insns) +static void alpha_tr_init_disas_context(DisasContextBase *dcbase, CPUState= *cpu) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); CPUAlphaState *env =3D cpu->env_ptr; @@ -2959,8 +2958,7 @@ static int alpha_tr_init_disas_context(DisasContextBa= se *dcbase, mask =3D TARGET_PAGE_MASK; } bound =3D -(ctx->base.pc_first | mask) / 4; - - return MIN(max_insns, bound); + ctx->base.max_insns =3D MIN(ctx->base.max_insns, bound); } =20 static void alpha_tr_tb_start(DisasContextBase *db, CPUState *cpu) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 6d49f30b4a4e..1e7c150514ca 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -13224,8 +13224,8 @@ static void disas_a64_insn(CPUARMState *env, DisasC= ontext *s) free_tmp_a64(s); } =20 -static int aarch64_tr_init_disas_context(DisasContextBase *dcbase, - CPUState *cpu, int max_insns) +static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, + CPUState *cpu) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); CPUARMState *env =3D cpu->env_ptr; @@ -13288,11 +13288,9 @@ static int aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, if (dc->ss_active) { bound =3D 1; } - max_insns =3D MIN(max_insns, bound); + dc->base.max_insns =3D MIN(dc->base.max_insns, bound); =20 init_tmp_a64_array(dc); - - return max_insns; } =20 static void aarch64_tr_tb_start(DisasContextBase *db, CPUState *cpu) diff --git a/target/arm/translate.c b/target/arm/translate.c index ad208867a79f..47f990cc0d01 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -12243,8 +12243,7 @@ static bool insn_crosses_page(CPUARMState *env, Dis= asContext *s) return !thumb_insn_is_16bit(s, insn); } =20 -static int arm_tr_init_disas_context(DisasContextBase *dcbase, - CPUState *cs, int max_insns) +static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *= cs) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); CPUARMState *env =3D cs->env_ptr; @@ -12306,14 +12305,14 @@ static int arm_tr_init_disas_context(DisasContext= Base *dcbase, =20 /* If architectural single step active, limit to 1. */ if (is_singlestepping(dc)) { - max_insns =3D 1; + dc->base.max_insns =3D 1; } =20 /* ARM is a fixed-length ISA. Bound the number of insns to execute to those left on the page. */ if (!dc->thumb) { - int bound =3D (dc->next_page_start - dc->base.pc_first) / 4; - max_insns =3D MIN(max_insns, bound); + int bound =3D -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; + dc->base.max_insns =3D MIN(dc->base.max_insns, bound); } =20 cpu_F0s =3D tcg_temp_new_i32(); @@ -12324,8 +12323,6 @@ static int arm_tr_init_disas_context(DisasContextBa= se *dcbase, cpu_V1 =3D cpu_F1d; /* FIXME: cpu_M0 can probably be the same as cpu_V0. */ cpu_M0 =3D tcg_temp_new_i64(); - - return max_insns; } =20 static void arm_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index cdc397308b9f..5320b217deb0 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -4669,8 +4669,7 @@ static DisasJumpType translate_one(DisasContext *ctx,= uint32_t insn) return gen_illegal(ctx); } =20 -static int hppa_tr_init_disas_context(DisasContextBase *dcbase, - CPUState *cs, int max_insns) +static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState = *cs) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); int bound; @@ -4700,14 +4699,12 @@ static int hppa_tr_init_disas_context(DisasContextB= ase *dcbase, =20 /* Bound the number of instructions by those left on the page. */ bound =3D -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4; - bound =3D MIN(max_insns, bound); + ctx->base.max_insns =3D MIN(ctx->base.max_insns, bound); =20 ctx->ntempr =3D 0; ctx->ntempl =3D 0; memset(ctx->tempr, 0, sizeof(ctx->tempr)); memset(ctx->templ, 0, sizeof(ctx->templ)); - - return bound; } =20 static void hppa_tr_tb_start(DisasContextBase *dcbase, CPUState *cs) diff --git a/target/i386/translate.c b/target/i386/translate.c index c9ed8dc70978..b0f69838f24b 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -8402,8 +8402,7 @@ void tcg_x86_init(void) } } =20 -static int i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *= cpu, - int max_insns) +static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState = *cpu) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); CPUX86State *env =3D cpu->env_ptr; @@ -8470,8 +8469,6 @@ static int i386_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cpu, cpu_ptr0 =3D tcg_temp_new_ptr(); cpu_ptr1 =3D tcg_temp_new_ptr(); cpu_cc_srcT =3D tcg_temp_local_new(); - - return max_insns; } =20 static void i386_tr_tb_start(DisasContextBase *db, CPUState *cpu) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 2a4140f42062..7972e6b4101e 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7215,8 +7215,7 @@ void ppc_cpu_dump_statistics(CPUState *cs, FILE*f, #endif } =20 -static int ppc_tr_init_disas_context(DisasContextBase *dcbase, - CPUState *cs, int max_insns) +static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *= cs) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); CPUPPCState *env =3D cs->env_ptr; @@ -7281,7 +7280,7 @@ static int ppc_tr_init_disas_context(DisasContextBase= *dcbase, #endif =20 bound =3D -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4; - return MIN(max_insns, bound); + ctx->base.max_insns =3D MIN(ctx->base.max_insns, bound); } =20 static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs) --=20 2.7.0 From nobody Wed Oct 29 11:33:39 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1525860928429927.3971590484634; Wed, 9 May 2018 03:15:28 -0700 (PDT) Received: from localhost ([::1]:55498 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fGM87-0005FG-Dp for importer@patchew.org; Wed, 09 May 2018 06:15:27 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43348) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fGM6F-0003dB-Oc for qemu-devel@nongnu.org; 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X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PATCH v1 3/6] target/riscv: convert to DisasJumpType X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Bastian Koppelmann , Palmer Dabbelt , "Emilio G. Cota" , patches@groups.riscv.org, Michael Clark Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Emilio G. Cota" Reviewed-by: Bastian Koppelmann Reviewed-by: Richard Henderson Cc: Michael Clark Cc: Palmer Dabbelt Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Emilio G. Cota --- target/riscv/translate.c | 72 +++++++++++++++++++-------------------------= ---- 1 file changed, 28 insertions(+), 44 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index a98033ca77ca..1fee5b51dc20 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -26,6 +26,7 @@ #include "exec/helper-proto.h" #include "exec/helper-gen.h" =20 +#include "exec/translator.h" #include "exec/log.h" =20 #include "instmap.h" @@ -46,7 +47,7 @@ typedef struct DisasContext { uint32_t flags; uint32_t mem_idx; int singlestep_enabled; - int bstate; + DisasJumpType is_jmp; /* Remember the rounding mode encoded in the previous fp instruction, which we have already installed into env->fp_status. Or -1 for no previous fp instruction. Note that we exit the TB when writing @@ -55,13 +56,6 @@ typedef struct DisasContext { int frm; } DisasContext; =20 -enum { - BS_NONE =3D 0, /* When seen outside of translation while loop, ind= icates - need to exit tb due to end of page. */ - BS_STOP =3D 1, /* Need to exit tb for syscall, sret, etc. */ - BS_BRANCH =3D 2, /* Need to exit tb for branch, jal, etc. */ -}; - /* convert riscv funct3 to qemu memop for load/store */ static const int tcg_memop_lookup[8] =3D { [0 ... 7] =3D -1, @@ -88,7 +82,7 @@ static void generate_exception(DisasContext *ctx, int exc= p) TCGv_i32 helper_tmp =3D tcg_const_i32(excp); gen_helper_raise_exception(cpu_env, helper_tmp); tcg_temp_free_i32(helper_tmp); - ctx->bstate =3D BS_BRANCH; + ctx->is_jmp =3D DISAS_NORETURN; } =20 static void generate_exception_mbadaddr(DisasContext *ctx, int excp) @@ -98,7 +92,7 @@ static void generate_exception_mbadaddr(DisasContext *ctx= , int excp) TCGv_i32 helper_tmp =3D tcg_const_i32(excp); gen_helper_raise_exception(cpu_env, helper_tmp); tcg_temp_free_i32(helper_tmp); - ctx->bstate =3D BS_BRANCH; + ctx->is_jmp =3D DISAS_NORETURN; } =20 static void gen_exception_debug(void) @@ -531,7 +525,7 @@ static void gen_jal(CPURISCVState *env, DisasContext *c= tx, int rd, } =20 gen_goto_tb(ctx, 0, ctx->pc + imm); /* must use this for safety */ - ctx->bstate =3D BS_BRANCH; + ctx->is_jmp =3D DISAS_NORETURN; } =20 static void gen_jalr(CPURISCVState *env, DisasContext *ctx, uint32_t opc, @@ -562,7 +556,7 @@ static void gen_jalr(CPURISCVState *env, DisasContext *= ctx, uint32_t opc, gen_set_label(misaligned); gen_exception_inst_addr_mis(ctx); } - ctx->bstate =3D BS_BRANCH; + ctx->is_jmp =3D DISAS_NORETURN; break; =20 default: @@ -616,7 +610,7 @@ static void gen_branch(CPURISCVState *env, DisasContext= *ctx, uint32_t opc, } else { gen_goto_tb(ctx, 0, ctx->pc + bimm); } - ctx->bstate =3D BS_BRANCH; + ctx->is_jmp =3D DISAS_NORETURN; } =20 static void gen_load(DisasContext *ctx, uint32_t opc, int rd, int rs1, @@ -1344,12 +1338,12 @@ static void gen_system(CPURISCVState *env, DisasCon= text *ctx, uint32_t opc, /* always generates U-level ECALL, fixed in do_interrupt handl= er */ generate_exception(ctx, RISCV_EXCP_U_ECALL); tcg_gen_exit_tb(0); /* no chaining */ - ctx->bstate =3D BS_BRANCH; + ctx->is_jmp =3D DISAS_NORETURN; break; case 0x1: /* EBREAK */ generate_exception(ctx, RISCV_EXCP_BREAKPOINT); tcg_gen_exit_tb(0); /* no chaining */ - ctx->bstate =3D BS_BRANCH; + ctx->is_jmp =3D DISAS_NORETURN; break; #ifndef CONFIG_USER_ONLY case 0x002: /* URET */ @@ -1359,7 +1353,7 @@ static void gen_system(CPURISCVState *env, DisasConte= xt *ctx, uint32_t opc, if (riscv_has_ext(env, RVS)) { gen_helper_sret(cpu_pc, cpu_env, cpu_pc); tcg_gen_exit_tb(0); /* no chaining */ - ctx->bstate =3D BS_BRANCH; + ctx->is_jmp =3D DISAS_NORETURN; } else { gen_exception_illegal(ctx); } @@ -1370,7 +1364,7 @@ static void gen_system(CPURISCVState *env, DisasConte= xt *ctx, uint32_t opc, case 0x302: /* MRET */ gen_helper_mret(cpu_pc, cpu_env, cpu_pc); tcg_gen_exit_tb(0); /* no chaining */ - ctx->bstate =3D BS_BRANCH; + ctx->is_jmp =3D DISAS_NORETURN; break; case 0x7b2: /* DRET */ gen_exception_illegal(ctx); @@ -1419,7 +1413,7 @@ static void gen_system(CPURISCVState *env, DisasConte= xt *ctx, uint32_t opc, /* end tb since we may be changing priv modes, to get mmu_index ri= ght */ tcg_gen_movi_tl(cpu_pc, ctx->next_pc); tcg_gen_exit_tb(0); /* no chaining */ - ctx->bstate =3D BS_BRANCH; + ctx->is_jmp =3D DISAS_NORETURN; break; } tcg_temp_free(source1); @@ -1812,7 +1806,7 @@ static void decode_RV32_64G(CPURISCVState *env, Disas= Context *ctx) * however we need to end the translation block */ tcg_gen_movi_tl(cpu_pc, ctx->next_pc); tcg_gen_exit_tb(0); - ctx->bstate =3D BS_BRANCH; + ctx->is_jmp =3D DISAS_NORETURN; } else { /* FENCE is a full memory barrier. */ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); @@ -1862,7 +1856,7 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb) ctx.singlestep_enabled =3D cs->singlestep_enabled; =20 ctx.tb =3D tb; - ctx.bstate =3D BS_NONE; + ctx.is_jmp =3D DISAS_NEXT; ctx.flags =3D tb->flags; ctx.mem_idx =3D tb->flags & TB_FLAGS_MMU_MASK; ctx.frm =3D -1; /* unknown rounding mode */ @@ -1877,13 +1871,13 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) } gen_tb_start(tb); =20 - while (ctx.bstate =3D=3D BS_NONE) { + while (ctx.is_jmp =3D=3D DISAS_NEXT) { tcg_gen_insn_start(ctx.pc); num_insns++; =20 if (unlikely(cpu_breakpoint_test(cs, ctx.pc, BP_ANY))) { tcg_gen_movi_tl(cpu_pc, ctx.pc); - ctx.bstate =3D BS_BRANCH; + ctx.is_jmp =3D DISAS_NORETURN; gen_exception_debug(); /* The address covered by the breakpoint must be included in [tb->pc, tb->pc + tb->size) in order to for it to be @@ -1901,31 +1895,20 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) decode_opc(env, &ctx); ctx.pc =3D ctx.next_pc; =20 - if (cs->singlestep_enabled) { - break; - } - if (ctx.pc - page_start >=3D TARGET_PAGE_SIZE) { - break; - } - if (tcg_op_buf_full()) { - break; + if (ctx.is_jmp =3D=3D DISAS_NEXT && + (cs->singlestep_enabled || + ctx.pc - page_start >=3D TARGET_PAGE_SIZE || + tcg_op_buf_full() || + num_insns >=3D max_insns || + singlestep)) { + ctx.is_jmp =3D DISAS_TOO_MANY; } - if (num_insns >=3D max_insns) { - break; - } - if (singlestep) { - break; - } - } if (tb->cflags & CF_LAST_IO) { gen_io_end(); } - switch (ctx.bstate) { - case BS_STOP: - gen_goto_tb(&ctx, 0, ctx.pc); - break; - case BS_NONE: /* handle end of page - DO NOT CHAIN. See gen_goto_tb. */ + switch (ctx.is_jmp) { + case DISAS_TOO_MANY: tcg_gen_movi_tl(cpu_pc, ctx.pc); if (cs->singlestep_enabled) { gen_exception_debug(); @@ -1933,9 +1916,10 @@ void gen_intermediate_code(CPUState *cs, Translation= Block *tb) tcg_gen_exit_tb(0); } break; - case BS_BRANCH: /* ops using BS_BRANCH generate own exit seq */ - default: + case DISAS_NORETURN: break; + default: + g_assert_not_reached(); } done_generating: gen_tb_end(tb, num_insns); --=20 2.7.0 From nobody Wed Oct 29 11:33:39 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1525860934054469.9053712852135; Wed, 9 May 2018 03:15:34 -0700 (PDT) Received: from localhost ([::1]:55499 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fGM8D-0005Py-44 for importer@patchew.org; Wed, 09 May 2018 06:15:33 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43380) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fGM6K-0003h8-UH for qemu-devel@nongnu.org; Wed, 09 May 2018 06:13:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fGM6I-00079Y-6O for qemu-devel@nongnu.org; Wed, 09 May 2018 06:13:36 -0400 Received: from mail-pl0-x241.google.com ([2607:f8b0:400e:c01::241]:38109) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fGM6H-00078r-SH for qemu-devel@nongnu.org; Wed, 09 May 2018 06:13:34 -0400 Received: by mail-pl0-x241.google.com with SMTP id c11-v6so4015774plr.5 for ; Wed, 09 May 2018 03:13:33 -0700 (PDT) Received: from localhost.localdomain (122-58-167-38-fibre.bb.spark.co.nz. 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X-Received-From: 2607:f8b0:400e:c01::241 Subject: [Qemu-devel] [PATCH v1 4/6] target/riscv: convert to DisasContextBase X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Bastian Koppelmann , Palmer Dabbelt , "Emilio G. Cota" , patches@groups.riscv.org, Michael Clark Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Emilio G. Cota" Notes: - Did not convert {num,max}_insns, since the corresponding code will go away in the next patch. - ctx->pc becomes ctx->base.pc_next, and ctx->next_pc becomes ctx->pc_succ_insn. While at it, convert the remaining tb->cflags readers to tb_cflags(). Reviewed-by: Richard Henderson Cc: Michael Clark Cc: Palmer Dabbelt Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Emilio G. Cota --- target/riscv/translate.c | 129 +++++++++++++++++++++++--------------------= ---- 1 file changed, 64 insertions(+), 65 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 1fee5b51dc20..68979abfd7ed 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -40,14 +40,12 @@ static TCGv load_val; #include "exec/gen-icount.h" =20 typedef struct DisasContext { - struct TranslationBlock *tb; - target_ulong pc; - target_ulong next_pc; + DisasContextBase base; + /* pc_succ_insn points to the instruction following base.pc_next */ + target_ulong pc_succ_insn; uint32_t opcode; uint32_t flags; uint32_t mem_idx; - int singlestep_enabled; - DisasJumpType is_jmp; /* Remember the rounding mode encoded in the previous fp instruction, which we have already installed into env->fp_status. Or -1 for no previous fp instruction. Note that we exit the TB when writing @@ -78,21 +76,21 @@ static const int tcg_memop_lookup[8] =3D { =20 static void generate_exception(DisasContext *ctx, int excp) { - tcg_gen_movi_tl(cpu_pc, ctx->pc); + tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); TCGv_i32 helper_tmp =3D tcg_const_i32(excp); gen_helper_raise_exception(cpu_env, helper_tmp); tcg_temp_free_i32(helper_tmp); - ctx->is_jmp =3D DISAS_NORETURN; + ctx->base.is_jmp =3D DISAS_NORETURN; } =20 static void generate_exception_mbadaddr(DisasContext *ctx, int excp) { - tcg_gen_movi_tl(cpu_pc, ctx->pc); + tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr)); TCGv_i32 helper_tmp =3D tcg_const_i32(excp); gen_helper_raise_exception(cpu_env, helper_tmp); tcg_temp_free_i32(helper_tmp); - ctx->is_jmp =3D DISAS_NORETURN; + ctx->base.is_jmp =3D DISAS_NORETURN; } =20 static void gen_exception_debug(void) @@ -114,12 +112,12 @@ static void gen_exception_inst_addr_mis(DisasContext = *ctx) =20 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) { - if (unlikely(ctx->singlestep_enabled)) { + if (unlikely(ctx->base.singlestep_enabled)) { return false; } =20 #ifndef CONFIG_USER_ONLY - return (ctx->tb->pc & TARGET_PAGE_MASK) =3D=3D (dest & TARGET_PAGE_MAS= K); + return (ctx->base.tb->pc & TARGET_PAGE_MASK) =3D=3D (dest & TARGET_PAG= E_MASK); #else return true; #endif @@ -131,10 +129,10 @@ static void gen_goto_tb(DisasContext *ctx, int n, tar= get_ulong dest) /* chaining is only allowed when the jump is to the same page */ tcg_gen_goto_tb(n); tcg_gen_movi_tl(cpu_pc, dest); - tcg_gen_exit_tb((uintptr_t)ctx->tb + n); + tcg_gen_exit_tb((uintptr_t)ctx->base.tb + n); } else { tcg_gen_movi_tl(cpu_pc, dest); - if (ctx->singlestep_enabled) { + if (ctx->base.singlestep_enabled) { gen_exception_debug(); } else { tcg_gen_exit_tb(0); @@ -513,7 +511,7 @@ static void gen_jal(CPURISCVState *env, DisasContext *c= tx, int rd, target_ulong next_pc; =20 /* check misaligned: */ - next_pc =3D ctx->pc + imm; + next_pc =3D ctx->base.pc_next + imm; if (!riscv_has_ext(env, RVC)) { if ((next_pc & 0x3) !=3D 0) { gen_exception_inst_addr_mis(ctx); @@ -521,11 +519,11 @@ static void gen_jal(CPURISCVState *env, DisasContext = *ctx, int rd, } } if (rd !=3D 0) { - tcg_gen_movi_tl(cpu_gpr[rd], ctx->next_pc); + tcg_gen_movi_tl(cpu_gpr[rd], ctx->pc_succ_insn); } =20 - gen_goto_tb(ctx, 0, ctx->pc + imm); /* must use this for safety */ - ctx->is_jmp =3D DISAS_NORETURN; + gen_goto_tb(ctx, 0, ctx->base.pc_next + imm); /* must use this for saf= ety */ + ctx->base.is_jmp =3D DISAS_NORETURN; } =20 static void gen_jalr(CPURISCVState *env, DisasContext *ctx, uint32_t opc, @@ -548,7 +546,7 @@ static void gen_jalr(CPURISCVState *env, DisasContext *= ctx, uint32_t opc, } =20 if (rd !=3D 0) { - tcg_gen_movi_tl(cpu_gpr[rd], ctx->next_pc); + tcg_gen_movi_tl(cpu_gpr[rd], ctx->pc_succ_insn); } tcg_gen_exit_tb(0); =20 @@ -556,7 +554,7 @@ static void gen_jalr(CPURISCVState *env, DisasContext *= ctx, uint32_t opc, gen_set_label(misaligned); gen_exception_inst_addr_mis(ctx); } - ctx->is_jmp =3D DISAS_NORETURN; + ctx->base.is_jmp =3D DISAS_NORETURN; break; =20 default: @@ -602,15 +600,15 @@ static void gen_branch(CPURISCVState *env, DisasConte= xt *ctx, uint32_t opc, tcg_temp_free(source1); tcg_temp_free(source2); =20 - gen_goto_tb(ctx, 1, ctx->next_pc); + gen_goto_tb(ctx, 1, ctx->pc_succ_insn); gen_set_label(l); /* branch taken */ - if (!riscv_has_ext(env, RVC) && ((ctx->pc + bimm) & 0x3)) { + if (!riscv_has_ext(env, RVC) && ((ctx->base.pc_next + bimm) & 0x3)) { /* misaligned */ gen_exception_inst_addr_mis(ctx); } else { - gen_goto_tb(ctx, 0, ctx->pc + bimm); + gen_goto_tb(ctx, 0, ctx->base.pc_next + bimm); } - ctx->is_jmp =3D DISAS_NORETURN; + ctx->base.is_jmp =3D DISAS_NORETURN; } =20 static void gen_load(DisasContext *ctx, uint32_t opc, int rd, int rs1, @@ -836,7 +834,7 @@ static void gen_atomic(DisasContext *ctx, uint32_t opc, if (rl) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); } - if (tb_cflags(ctx->tb) & CF_PARALLEL) { + if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { l1 =3D gen_new_label(); gen_set_label(l1); } else { @@ -853,7 +851,7 @@ static void gen_atomic(DisasContext *ctx, uint32_t opc, tcg_gen_qemu_ld_tl(dat, src1, ctx->mem_idx, mop); tcg_gen_movcond_tl(cond, src2, dat, src2, dat, src2); =20 - if (tb_cflags(ctx->tb) & CF_PARALLEL) { + if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { /* Parallel context. Make this operation atomic by verifying that the memory didn't change while we computed the result.= */ tcg_gen_atomic_cmpxchg_tl(src2, src1, dat, src2, ctx->mem_idx,= mop); @@ -1317,7 +1315,7 @@ static void gen_system(CPURISCVState *env, DisasConte= xt *ctx, uint32_t opc, rs1_pass =3D tcg_temp_new(); imm_rs1 =3D tcg_temp_new(); gen_get_gpr(source1, rs1); - tcg_gen_movi_tl(cpu_pc, ctx->pc); + tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); tcg_gen_movi_tl(rs1_pass, rs1); tcg_gen_movi_tl(csr_store, csr); /* copy into temp reg to feed to help= er */ =20 @@ -1338,12 +1336,12 @@ static void gen_system(CPURISCVState *env, DisasCon= text *ctx, uint32_t opc, /* always generates U-level ECALL, fixed in do_interrupt handl= er */ generate_exception(ctx, RISCV_EXCP_U_ECALL); tcg_gen_exit_tb(0); /* no chaining */ - ctx->is_jmp =3D DISAS_NORETURN; + ctx->base.is_jmp =3D DISAS_NORETURN; break; case 0x1: /* EBREAK */ generate_exception(ctx, RISCV_EXCP_BREAKPOINT); tcg_gen_exit_tb(0); /* no chaining */ - ctx->is_jmp =3D DISAS_NORETURN; + ctx->base.is_jmp =3D DISAS_NORETURN; break; #ifndef CONFIG_USER_ONLY case 0x002: /* URET */ @@ -1353,7 +1351,7 @@ static void gen_system(CPURISCVState *env, DisasConte= xt *ctx, uint32_t opc, if (riscv_has_ext(env, RVS)) { gen_helper_sret(cpu_pc, cpu_env, cpu_pc); tcg_gen_exit_tb(0); /* no chaining */ - ctx->is_jmp =3D DISAS_NORETURN; + ctx->base.is_jmp =3D DISAS_NORETURN; } else { gen_exception_illegal(ctx); } @@ -1364,13 +1362,13 @@ static void gen_system(CPURISCVState *env, DisasCon= text *ctx, uint32_t opc, case 0x302: /* MRET */ gen_helper_mret(cpu_pc, cpu_env, cpu_pc); tcg_gen_exit_tb(0); /* no chaining */ - ctx->is_jmp =3D DISAS_NORETURN; + ctx->base.is_jmp =3D DISAS_NORETURN; break; case 0x7b2: /* DRET */ gen_exception_illegal(ctx); break; case 0x105: /* WFI */ - tcg_gen_movi_tl(cpu_pc, ctx->next_pc); + tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn); gen_helper_wfi(cpu_env); break; case 0x104: /* SFENCE.VM */ @@ -1411,9 +1409,9 @@ static void gen_system(CPURISCVState *env, DisasConte= xt *ctx, uint32_t opc, gen_io_end(); gen_set_gpr(rd, dest); /* end tb since we may be changing priv modes, to get mmu_index ri= ght */ - tcg_gen_movi_tl(cpu_pc, ctx->next_pc); + tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn); tcg_gen_exit_tb(0); /* no chaining */ - ctx->is_jmp =3D DISAS_NORETURN; + ctx->base.is_jmp =3D DISAS_NORETURN; break; } tcg_temp_free(source1); @@ -1731,7 +1729,7 @@ static void decode_RV32_64G(CPURISCVState *env, Disas= Context *ctx) break; /* NOP */ } tcg_gen_movi_tl(cpu_gpr[rd], (sextract64(ctx->opcode, 12, 20) << 1= 2) + - ctx->pc); + ctx->base.pc_next); break; case OPC_RISC_JAL: imm =3D GET_JAL_IMM(ctx->opcode); @@ -1804,9 +1802,9 @@ static void decode_RV32_64G(CPURISCVState *env, Disas= Context *ctx) if (ctx->opcode & 0x1000) { /* FENCE_I is a no-op in QEMU, * however we need to end the translation block */ - tcg_gen_movi_tl(cpu_pc, ctx->next_pc); + tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn); tcg_gen_exit_tb(0); - ctx->is_jmp =3D DISAS_NORETURN; + ctx->base.is_jmp =3D DISAS_NORETURN; } else { /* FENCE is a full memory barrier. */ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); @@ -1830,11 +1828,11 @@ static void decode_opc(CPURISCVState *env, DisasCon= text *ctx) if (!riscv_has_ext(env, RVC)) { gen_exception_illegal(ctx); } else { - ctx->next_pc =3D ctx->pc + 2; + ctx->pc_succ_insn =3D ctx->base.pc_next + 2; decode_RV32_64C(env, ctx); } } else { - ctx->next_pc =3D ctx->pc + 4; + ctx->pc_succ_insn =3D ctx->base.pc_next + 4; decode_RV32_64G(env, ctx); } } @@ -1843,26 +1841,26 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) { CPURISCVState *env =3D cs->env_ptr; DisasContext ctx; - target_ulong pc_start; target_ulong page_start; int num_insns; int max_insns; - pc_start =3D tb->pc; - page_start =3D pc_start & TARGET_PAGE_MASK; - ctx.pc =3D pc_start; =20 + ctx.base.pc_first =3D tb->pc; + ctx.base.pc_next =3D ctx.base.pc_first; /* once we have GDB, the rest of the translate.c implementation should= be ready for singlestep */ - ctx.singlestep_enabled =3D cs->singlestep_enabled; + ctx.base.singlestep_enabled =3D cs->singlestep_enabled; + ctx.base.tb =3D tb; + ctx.base.is_jmp =3D DISAS_NEXT; =20 - ctx.tb =3D tb; - ctx.is_jmp =3D DISAS_NEXT; + page_start =3D ctx.base.pc_first & TARGET_PAGE_MASK; + ctx.pc_succ_insn =3D ctx.base.pc_first; ctx.flags =3D tb->flags; ctx.mem_idx =3D tb->flags & TB_FLAGS_MMU_MASK; ctx.frm =3D -1; /* unknown rounding mode */ =20 num_insns =3D 0; - max_insns =3D tb->cflags & CF_COUNT_MASK; + max_insns =3D tb_cflags(ctx.base.tb) & CF_COUNT_MASK; if (max_insns =3D=3D 0) { max_insns =3D CF_COUNT_MASK; } @@ -1871,45 +1869,45 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) } gen_tb_start(tb); =20 - while (ctx.is_jmp =3D=3D DISAS_NEXT) { - tcg_gen_insn_start(ctx.pc); + while (ctx.base.is_jmp =3D=3D DISAS_NEXT) { + tcg_gen_insn_start(ctx.base.pc_next); num_insns++; =20 - if (unlikely(cpu_breakpoint_test(cs, ctx.pc, BP_ANY))) { - tcg_gen_movi_tl(cpu_pc, ctx.pc); - ctx.is_jmp =3D DISAS_NORETURN; + if (unlikely(cpu_breakpoint_test(cs, ctx.base.pc_next, BP_ANY))) { + tcg_gen_movi_tl(cpu_pc, ctx.base.pc_next); + ctx.base.is_jmp =3D DISAS_NORETURN; gen_exception_debug(); /* The address covered by the breakpoint must be included in [tb->pc, tb->pc + tb->size) in order to for it to be properly cleared -- thus we increment the PC here so that the logic setting tb->size below does the right thing. */ - ctx.pc +=3D 4; + ctx.base.pc_next +=3D 4; goto done_generating; } =20 - if (num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_IO)) { + if (num_insns =3D=3D max_insns && (tb_cflags(ctx.base.tb) & CF_LAS= T_IO)) { gen_io_start(); } =20 - ctx.opcode =3D cpu_ldl_code(env, ctx.pc); + ctx.opcode =3D cpu_ldl_code(env, ctx.base.pc_next); decode_opc(env, &ctx); - ctx.pc =3D ctx.next_pc; + ctx.base.pc_next =3D ctx.pc_succ_insn; =20 - if (ctx.is_jmp =3D=3D DISAS_NEXT && + if (ctx.base.is_jmp =3D=3D DISAS_NEXT && (cs->singlestep_enabled || - ctx.pc - page_start >=3D TARGET_PAGE_SIZE || + ctx.base.pc_next - page_start >=3D TARGET_PAGE_SIZE || tcg_op_buf_full() || num_insns >=3D max_insns || singlestep)) { - ctx.is_jmp =3D DISAS_TOO_MANY; + ctx.base.is_jmp =3D DISAS_TOO_MANY; } } - if (tb->cflags & CF_LAST_IO) { + if (tb_cflags(ctx.base.tb) & CF_LAST_IO) { gen_io_end(); } - switch (ctx.is_jmp) { + switch (ctx.base.is_jmp) { case DISAS_TOO_MANY: - tcg_gen_movi_tl(cpu_pc, ctx.pc); + tcg_gen_movi_tl(cpu_pc, ctx.base.pc_next); if (cs->singlestep_enabled) { gen_exception_debug(); } else { @@ -1923,14 +1921,15 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) } done_generating: gen_tb_end(tb, num_insns); - tb->size =3D ctx.pc - pc_start; + tb->size =3D ctx.base.pc_next - ctx.base.pc_first; tb->icount =3D num_insns; =20 #ifdef DEBUG_DISAS if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) - && qemu_log_in_addr_range(pc_start)) { - qemu_log("IN: %s\n", lookup_symbol(pc_start)); - log_target_disas(cs, pc_start, ctx.pc - pc_start); + && qemu_log_in_addr_range(ctx.base.pc_first)) { + qemu_log("IN: %s\n", lookup_symbol(ctx.base.pc_first)); + log_target_disas(cs, ctx.base.pc_first, + ctx.base.pc_next - ctx.base.pc_first); qemu_log("\n"); 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X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PATCH v1 5/6] target/riscv: convert to TranslatorOps X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Bastian Koppelmann , Palmer Dabbelt , "Emilio G. Cota" , patches@groups.riscv.org, Michael Clark Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Emilio G. Cota" Reviewed-by: Richard Henderson Cc: Michael Clark Cc: Palmer Dabbelt Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Emilio G. Cota --- target/riscv/translate.c | 158 ++++++++++++++++++++++++-------------------= ---- 1 file changed, 80 insertions(+), 78 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 68979abfd7ed..1788668c6f28 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1837,78 +1837,71 @@ static void decode_opc(CPURISCVState *env, DisasCon= text *ctx) } } =20 -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) +static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState= *cs) { - CPURISCVState *env =3D cs->env_ptr; - DisasContext ctx; - target_ulong page_start; - int num_insns; - int max_insns; - - ctx.base.pc_first =3D tb->pc; - ctx.base.pc_next =3D ctx.base.pc_first; - /* once we have GDB, the rest of the translate.c implementation should= be - ready for singlestep */ - ctx.base.singlestep_enabled =3D cs->singlestep_enabled; - ctx.base.tb =3D tb; - ctx.base.is_jmp =3D DISAS_NEXT; - - page_start =3D ctx.base.pc_first & TARGET_PAGE_MASK; - ctx.pc_succ_insn =3D ctx.base.pc_first; - ctx.flags =3D tb->flags; - ctx.mem_idx =3D tb->flags & TB_FLAGS_MMU_MASK; - ctx.frm =3D -1; /* unknown rounding mode */ - - num_insns =3D 0; - max_insns =3D tb_cflags(ctx.base.tb) & CF_COUNT_MASK; - if (max_insns =3D=3D 0) { - max_insns =3D CF_COUNT_MASK; - } - if (max_insns > TCG_MAX_INSNS) { - max_insns =3D TCG_MAX_INSNS; - } - gen_tb_start(tb); + DisasContext *ctx =3D container_of(dcbase, DisasContext, base); =20 - while (ctx.base.is_jmp =3D=3D DISAS_NEXT) { - tcg_gen_insn_start(ctx.base.pc_next); - num_insns++; + ctx->pc_succ_insn =3D ctx->base.pc_first; + ctx->flags =3D ctx->base.tb->flags; + ctx->mem_idx =3D ctx->base.tb->flags & TB_FLAGS_MMU_MASK; + ctx->frm =3D -1; /* unknown rounding mode */ +} =20 - if (unlikely(cpu_breakpoint_test(cs, ctx.base.pc_next, BP_ANY))) { - tcg_gen_movi_tl(cpu_pc, ctx.base.pc_next); - ctx.base.is_jmp =3D DISAS_NORETURN; - gen_exception_debug(); - /* The address covered by the breakpoint must be included in - [tb->pc, tb->pc + tb->size) in order to for it to be - properly cleared -- thus we increment the PC here so that - the logic setting tb->size below does the right thing. */ - ctx.base.pc_next +=3D 4; - goto done_generating; - } +static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) +{ +} =20 - if (num_insns =3D=3D max_insns && (tb_cflags(ctx.base.tb) & CF_LAS= T_IO)) { - gen_io_start(); - } +static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *ctx =3D container_of(dcbase, DisasContext, base); + + tcg_gen_insn_start(ctx->base.pc_next); +} + +static bool riscv_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *= cpu, + const CPUBreakpoint *bp) +{ + DisasContext *ctx =3D container_of(dcbase, DisasContext, base); + + tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); + ctx->base.is_jmp =3D DISAS_NORETURN; + gen_exception_debug(); + /* The address covered by the breakpoint must be included in + [tb->pc, tb->pc + tb->size) in order to for it to be + properly cleared -- thus we increment the PC here so that + the logic setting tb->size below does the right thing. */ + ctx->base.pc_next +=3D 4; + return true; +} + + +static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cp= u) +{ + DisasContext *ctx =3D container_of(dcbase, DisasContext, base); + CPURISCVState *env =3D cpu->env_ptr; =20 - ctx.opcode =3D cpu_ldl_code(env, ctx.base.pc_next); - decode_opc(env, &ctx); - ctx.base.pc_next =3D ctx.pc_succ_insn; - - if (ctx.base.is_jmp =3D=3D DISAS_NEXT && - (cs->singlestep_enabled || - ctx.base.pc_next - page_start >=3D TARGET_PAGE_SIZE || - tcg_op_buf_full() || - num_insns >=3D max_insns || - singlestep)) { - ctx.base.is_jmp =3D DISAS_TOO_MANY; + ctx->opcode =3D cpu_ldl_code(env, ctx->base.pc_next); + decode_opc(env, ctx); + ctx->base.pc_next =3D ctx->pc_succ_insn; + + if (ctx->base.is_jmp =3D=3D DISAS_NEXT) { + target_ulong page_start; + + page_start =3D ctx->base.pc_first & TARGET_PAGE_MASK; + if (ctx->base.pc_next - page_start >=3D TARGET_PAGE_SIZE) { + ctx->base.is_jmp =3D DISAS_TOO_MANY; } } - if (tb_cflags(ctx.base.tb) & CF_LAST_IO) { - gen_io_end(); - } - switch (ctx.base.is_jmp) { +} + +static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *ctx =3D container_of(dcbase, DisasContext, base); + + switch (ctx->base.is_jmp) { case DISAS_TOO_MANY: - tcg_gen_movi_tl(cpu_pc, ctx.base.pc_next); - if (cs->singlestep_enabled) { + tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); + if (ctx->base.singlestep_enabled) { gen_exception_debug(); } else { tcg_gen_exit_tb(0); @@ -1919,20 +1912,29 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) default: g_assert_not_reached(); } -done_generating: - gen_tb_end(tb, num_insns); - tb->size =3D ctx.base.pc_next - ctx.base.pc_first; - tb->icount =3D num_insns; - -#ifdef DEBUG_DISAS - if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) - && qemu_log_in_addr_range(ctx.base.pc_first)) { - qemu_log("IN: %s\n", lookup_symbol(ctx.base.pc_first)); - log_target_disas(cs, ctx.base.pc_first, - ctx.base.pc_next - ctx.base.pc_first); - qemu_log("\n"); - } -#endif +} + +static void riscv_tr_disas_log(const DisasContextBase *dcbase, CPUState *c= pu) +{ + qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); + log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size); +} + +static const TranslatorOps riscv_tr_ops =3D { + .init_disas_context =3D riscv_tr_init_disas_context, + .tb_start =3D riscv_tr_tb_start, + .insn_start =3D riscv_tr_insn_start, + .breakpoint_check =3D riscv_tr_breakpoint_check, + .translate_insn =3D riscv_tr_translate_insn, + .tb_stop =3D riscv_tr_tb_stop, + .disas_log =3D riscv_tr_disas_log, +}; + +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) +{ + DisasContext ctx; + + translator_loop(&riscv_tr_ops, &ctx.base, cs, tb); } =20 void riscv_translate_init(void) --=20 2.7.0 From nobody Wed Oct 29 11:33:39 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 152586113282383.96362786045745; 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[122.58.167.38]) by smtp.gmail.com with ESMTPSA id q22sm20610396pfk.4.2018.05.09.03.13.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 09 May 2018 03:13:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=+Yes4DuxDio15BIf9eL0ZcLbV5hSOX5POEvomD8c8Xk=; b=hdHun7Tobr2bYhxPP4VT+IqQ0kr32/BTvxFhaWSdggWmcAI3r5B+NhcyD7qhedsnQj hlcKIsM9LSKUtc9Xhrvr1LLV2KZ8Mau4n/WwYLBSSjfAu0Wm4+hjoy/eO0D+Bnq7nLYE LuLVXXVLrJ5l4L/brqz/cGBI8nQx+7d9QFQfg3X8Phz3mostlL9jLCJyEt7bwkJKCuYe bv6G05M5nSTSUfbNz1iH/rkZnZlDaHotYt6c2sCsliIVf/wNf5P6OiRt8yjoyG8zyNyX sWPIoL+QVci/wkFtFw+cziJ2l5OjhA9AuOv8+kKaln++VU3HN+65thwNC06pP+Eh6fSy cY2Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=+Yes4DuxDio15BIf9eL0ZcLbV5hSOX5POEvomD8c8Xk=; b=E9G+EMZDoHGAX7h2tvWCLWtIEWKIHyU1Yds1flcuUw4duCIUaZjJwyG9f1yucxx3pB oldssC7UxJCt17bjQ0Ac1mZVKy/wutGRrsOFbRJeWkR5vrCXjzgFzWKY9AeOiX7Qag+j ufbgGAk3CVTCcxt2rg9psbDU+DJjdqUrsHiFrli4ym7xhtDw+BaWBH2yx5bMWsOuT7Wl qUmaeQ1sYLimAGfv9U3S0iHWOQJmILGQ24l6aW/jkFSoAUPqOhSzQO2XXkWKGrn9SJY0 Z8BtKUxqgWQ6Xm0ZlbSEc98OnmeGsDbiE3YIFhGEjo0v4no8xUUs6240Vy+MscBwwh0c PHxA== X-Gm-Message-State: ALQs6tBPJGGyALntv0fux6+XABt7DVEf2gYXk7fxIFlG/vf8UNSMPGhR CAVPbnNvIgKF3fUFp3fJMZR0ip/IhZM= X-Google-Smtp-Source: AB8JxZrbLRELOsq/BZENwVaTvQyp+JOp+DElnVmmmYoodD8m5Yjejfqre1DsQo16MDxFHV6blsu9Og== X-Received: by 2002:a17:902:9a06:: with SMTP id v6-v6mr7891369plp.21.1525860820067; Wed, 09 May 2018 03:13:40 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Wed, 9 May 2018 22:11:53 +1200 Message-Id: <1525860713-3476-7-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1525860713-3476-1-git-send-email-mjc@sifive.com> References: <1525860713-3476-1-git-send-email-mjc@sifive.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::242 Subject: [Qemu-devel] [PATCH v1 6/6] target/riscv: add misa to DisasContext X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Bastian Koppelmann , Palmer Dabbelt , "Emilio G . Cota" , Michael Clark , Alistair Francis , patches@groups.riscv.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" gen methods should access state from DisasContext. Add misa field to the DisasContext struct and remove CPURISCVState argument from all gen methods. [Rebased against github.com/cota/qemu/tree/trloop-conv-v3] Cc: Palmer Dabbelt Cc: Sagar Karandikar Cc: Bastian Koppelmann Cc: Alistair Francis Cc: Emilio G. Cota Signed-off-by: Michael Clark --- target/riscv/translate.c | 77 ++++++++++++++++++++++++++------------------= ---- 1 file changed, 42 insertions(+), 35 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 1788668c6f28..507d74186293 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -45,6 +45,7 @@ typedef struct DisasContext { target_ulong pc_succ_insn; uint32_t opcode; uint32_t flags; + uint32_t misa; uint32_t mem_idx; /* Remember the rounding mode encoded in the previous fp instruction, which we have already installed into env->fp_status. Or -1 for @@ -74,6 +75,11 @@ static const int tcg_memop_lookup[8] =3D { #define CASE_OP_32_64(X) case X #endif =20 +static inline bool has_ext(DisasContext *ctx, uint32_t ext) +{ + return ctx->misa & ext; +} + static void generate_exception(DisasContext *ctx, int excp) { tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); @@ -505,14 +511,13 @@ static void gen_arith_imm(DisasContext *ctx, uint32_t= opc, int rd, tcg_temp_free(source1); } =20 -static void gen_jal(CPURISCVState *env, DisasContext *ctx, int rd, - target_ulong imm) +static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) { target_ulong next_pc; =20 /* check misaligned: */ next_pc =3D ctx->base.pc_next + imm; - if (!riscv_has_ext(env, RVC)) { + if (!has_ext(ctx, RVC)) { if ((next_pc & 0x3) !=3D 0) { gen_exception_inst_addr_mis(ctx); return; @@ -526,8 +531,8 @@ static void gen_jal(CPURISCVState *env, DisasContext *c= tx, int rd, ctx->base.is_jmp =3D DISAS_NORETURN; } =20 -static void gen_jalr(CPURISCVState *env, DisasContext *ctx, uint32_t opc, - int rd, int rs1, target_long imm) +static void gen_jalr(DisasContext *ctx, uint32_t opc, int rd, int rs1, + target_long imm) { /* no chaining with JALR */ TCGLabel *misaligned =3D NULL; @@ -539,7 +544,7 @@ static void gen_jalr(CPURISCVState *env, DisasContext *= ctx, uint32_t opc, tcg_gen_addi_tl(cpu_pc, cpu_pc, imm); tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2); =20 - if (!riscv_has_ext(env, RVC)) { + if (!has_ext(ctx, RVC)) { misaligned =3D gen_new_label(); tcg_gen_andi_tl(t0, cpu_pc, 0x2); tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0x0, misaligned); @@ -564,8 +569,8 @@ static void gen_jalr(CPURISCVState *env, DisasContext *= ctx, uint32_t opc, tcg_temp_free(t0); } =20 -static void gen_branch(CPURISCVState *env, DisasContext *ctx, uint32_t opc, - int rs1, int rs2, target_long bimm) +static void gen_branch(DisasContext *ctx, uint32_t opc, int rs1, int rs2, + target_long bimm) { TCGLabel *l =3D gen_new_label(); TCGv source1, source2; @@ -602,7 +607,7 @@ static void gen_branch(CPURISCVState *env, DisasContext= *ctx, uint32_t opc, =20 gen_goto_tb(ctx, 1, ctx->pc_succ_insn); gen_set_label(l); /* branch taken */ - if (!riscv_has_ext(env, RVC) && ((ctx->base.pc_next + bimm) & 0x3)) { + if (!has_ext(ctx, RVC) && ((ctx->base.pc_next + bimm) & 0x3)) { /* misaligned */ gen_exception_inst_addr_mis(ctx); } else { @@ -1305,8 +1310,8 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t = opc, int rd, } } =20 -static void gen_system(CPURISCVState *env, DisasContext *ctx, uint32_t opc, - int rd, int rs1, int csr) +static void gen_system(DisasContext *ctx, uint32_t opc, int rd, int rs1, + int csr) { TCGv source1, csr_store, dest, rs1_pass, imm_rs1; source1 =3D tcg_temp_new(); @@ -1348,7 +1353,7 @@ static void gen_system(CPURISCVState *env, DisasConte= xt *ctx, uint32_t opc, gen_exception_illegal(ctx); break; case 0x102: /* SRET */ - if (riscv_has_ext(env, RVS)) { + if (has_ext(ctx, RVS)) { gen_helper_sret(cpu_pc, cpu_env, cpu_pc); tcg_gen_exit_tb(0); /* no chaining */ ctx->base.is_jmp =3D DISAS_NORETURN; @@ -1489,7 +1494,7 @@ static void decode_RV32_64C0(DisasContext *ctx) } } =20 -static void decode_RV32_64C1(CPURISCVState *env, DisasContext *ctx) +static void decode_RV32_64C1(DisasContext *ctx) { uint8_t funct3 =3D extract32(ctx->opcode, 13, 3); uint8_t rd_rs1 =3D GET_C_RS1(ctx->opcode); @@ -1509,7 +1514,7 @@ static void decode_RV32_64C1(CPURISCVState *env, Disa= sContext *ctx) GET_C_IMM(ctx->opcode)); #else /* C.JAL(RV32) -> jal x1, offset[11:1] */ - gen_jal(env, ctx, 1, GET_C_J_IMM(ctx->opcode)); + gen_jal(ctx, 1, GET_C_J_IMM(ctx->opcode)); #endif break; case 2: @@ -1588,22 +1593,22 @@ static void decode_RV32_64C1(CPURISCVState *env, Di= sasContext *ctx) break; case 5: /* C.J -> jal x0, offset[11:1]*/ - gen_jal(env, ctx, 0, GET_C_J_IMM(ctx->opcode)); + gen_jal(ctx, 0, GET_C_J_IMM(ctx->opcode)); break; case 6: /* C.BEQZ -> beq rs1', x0, offset[8:1]*/ rs1s =3D GET_C_RS1S(ctx->opcode); - gen_branch(env, ctx, OPC_RISC_BEQ, rs1s, 0, GET_C_B_IMM(ctx->opcod= e)); + gen_branch(ctx, OPC_RISC_BEQ, rs1s, 0, GET_C_B_IMM(ctx->opcode)); break; case 7: /* C.BNEZ -> bne rs1', x0, offset[8:1]*/ rs1s =3D GET_C_RS1S(ctx->opcode); - gen_branch(env, ctx, OPC_RISC_BNE, rs1s, 0, GET_C_B_IMM(ctx->opcod= e)); + gen_branch(ctx, OPC_RISC_BNE, rs1s, 0, GET_C_B_IMM(ctx->opcode)); break; } } =20 -static void decode_RV32_64C2(CPURISCVState *env, DisasContext *ctx) +static void decode_RV32_64C2(DisasContext *ctx) { uint8_t rd, rs2; uint8_t funct3 =3D extract32(ctx->opcode, 13, 3); @@ -1637,7 +1642,7 @@ static void decode_RV32_64C2(CPURISCVState *env, Disa= sContext *ctx) if (extract32(ctx->opcode, 12, 1) =3D=3D 0) { if (rs2 =3D=3D 0) { /* C.JR -> jalr x0, rs1, 0*/ - gen_jalr(env, ctx, OPC_RISC_JALR, 0, rd, 0); + gen_jalr(ctx, OPC_RISC_JALR, 0, rd, 0); } else { /* C.MV -> add rd, x0, rs2 */ gen_arith(ctx, OPC_RISC_ADD, rd, 0, rs2); @@ -1645,11 +1650,11 @@ static void decode_RV32_64C2(CPURISCVState *env, Di= sasContext *ctx) } else { if (rd =3D=3D 0) { /* C.EBREAK -> ebreak*/ - gen_system(env, ctx, OPC_RISC_ECALL, 0, 0, 0x1); + gen_system(ctx, OPC_RISC_ECALL, 0, 0, 0x1); } else { if (rs2 =3D=3D 0) { /* C.JALR -> jalr x1, rs1, 0*/ - gen_jalr(env, ctx, OPC_RISC_JALR, 1, rd, 0); + gen_jalr(ctx, OPC_RISC_JALR, 1, rd, 0); } else { /* C.ADD -> add rd, rd, rs2 */ gen_arith(ctx, OPC_RISC_ADD, rd, rd, rs2); @@ -1681,7 +1686,7 @@ static void decode_RV32_64C2(CPURISCVState *env, Disa= sContext *ctx) } } =20 -static void decode_RV32_64C(CPURISCVState *env, DisasContext *ctx) +static void decode_RV32_64C(DisasContext *ctx) { uint8_t op =3D extract32(ctx->opcode, 0, 2); =20 @@ -1690,15 +1695,15 @@ static void decode_RV32_64C(CPURISCVState *env, Dis= asContext *ctx) decode_RV32_64C0(ctx); break; case 1: - decode_RV32_64C1(env, ctx); + decode_RV32_64C1(ctx); break; case 2: - decode_RV32_64C2(env, ctx); + decode_RV32_64C2(ctx); break; } } =20 -static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx) +static void decode_RV32_64G(DisasContext *ctx) { int rs1; int rs2; @@ -1733,13 +1738,13 @@ static void decode_RV32_64G(CPURISCVState *env, Dis= asContext *ctx) break; case OPC_RISC_JAL: imm =3D GET_JAL_IMM(ctx->opcode); - gen_jal(env, ctx, rd, imm); + gen_jal(ctx, rd, imm); break; case OPC_RISC_JALR: - gen_jalr(env, ctx, MASK_OP_JALR(ctx->opcode), rd, rs1, imm); + gen_jalr(ctx, MASK_OP_JALR(ctx->opcode), rd, rs1, imm); break; case OPC_RISC_BRANCH: - gen_branch(env, ctx, MASK_OP_BRANCH(ctx->opcode), rs1, rs2, + gen_branch(ctx, MASK_OP_BRANCH(ctx->opcode), rs1, rs2, GET_B_IMM(ctx->opcode)); break; case OPC_RISC_LOAD: @@ -1812,7 +1817,7 @@ static void decode_RV32_64G(CPURISCVState *env, Disas= Context *ctx) #endif break; case OPC_RISC_SYSTEM: - gen_system(env, ctx, MASK_OP_SYSTEM(ctx->opcode), rd, rs1, + gen_system(ctx, MASK_OP_SYSTEM(ctx->opcode), rd, rs1, (ctx->opcode & 0xFFF00000) >> 20); break; default: @@ -1821,28 +1826,30 @@ static void decode_RV32_64G(CPURISCVState *env, Dis= asContext *ctx) } } =20 -static void decode_opc(CPURISCVState *env, DisasContext *ctx) +static void decode_opc(DisasContext *ctx) { /* check for compressed insn */ if (extract32(ctx->opcode, 0, 2) !=3D 3) { - if (!riscv_has_ext(env, RVC)) { + if (!has_ext(ctx, RVC)) { gen_exception_illegal(ctx); } else { ctx->pc_succ_insn =3D ctx->base.pc_next + 2; - decode_RV32_64C(env, ctx); + decode_RV32_64C(ctx); } } else { ctx->pc_succ_insn =3D ctx->base.pc_next + 4; - decode_RV32_64G(env, ctx); + decode_RV32_64G(ctx); } } =20 -static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState= *cs) +static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState= *cpu) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); + CPURISCVState *env =3D cpu->env_ptr; =20 ctx->pc_succ_insn =3D ctx->base.pc_first; ctx->flags =3D ctx->base.tb->flags; + ctx->misa =3D env->misa; ctx->mem_idx =3D ctx->base.tb->flags & TB_FLAGS_MMU_MASK; ctx->frm =3D -1; /* unknown rounding mode */ } @@ -1881,7 +1888,7 @@ static void riscv_tr_translate_insn(DisasContextBase = *dcbase, CPUState *cpu) CPURISCVState *env =3D cpu->env_ptr; =20 ctx->opcode =3D cpu_ldl_code(env, ctx->base.pc_next); - decode_opc(env, ctx); + decode_opc(ctx); ctx->base.pc_next =3D ctx->pc_succ_insn; =20 if (ctx->base.is_jmp =3D=3D DISAS_NEXT) { --=20 2.7.0