From nobody Wed Oct 29 11:56:38 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1525563737066676.7759451921298; Sat, 5 May 2018 16:42:17 -0700 (PDT) Received: from localhost ([::1]:40286 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fF6oi-0007iM-4n for importer@patchew.org; Sat, 05 May 2018 19:42:16 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54270) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fF6jm-0003uf-9H for qemu-devel@nongnu.org; Sat, 05 May 2018 19:37:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fF6jk-0003cc-QC for qemu-devel@nongnu.org; Sat, 05 May 2018 19:37:10 -0400 Received: from mail-pf0-x242.google.com ([2607:f8b0:400e:c00::242]:37612) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fF6jk-0003cG-I7 for qemu-devel@nongnu.org; Sat, 05 May 2018 19:37:08 -0400 Received: by mail-pf0-x242.google.com with SMTP id e9so16092818pfi.4 for ; Sat, 05 May 2018 16:37:08 -0700 (PDT) Received: from localhost.localdomain (122-58-167-38-fibre.bb.spark.co.nz. [122.58.167.38]) by smtp.gmail.com with ESMTPSA id x8sm47297094pfa.173.2018.05.05.16.37.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 05 May 2018 16:37:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WN37+KqseeIgXipiGu6LDKAfte7NHaQ3es3PGBSRuiY=; b=MRIIGL9OdwjiGNm50m8bXjpYhWwcuWFUjOQGTfjhhbJ2V5LihIBVSO1CzNILjAmzWy hslMEa5YOHTpsWJ4xCGv0DA/BL5SJ8MLxKCZIrkmPJTjnbJltcGlPrrD5vxxtv0tBUG6 WtXFX/3TCKsOrMwn60Zq/4h0DZl9aNxU1X++L8Ktz9u6+dGgriqbATiHcxPxRu/tLCRj VtVddiMeDrZbPLuYKu1a4ojncVAbvi3lLtim5a4IAuzGjgYhjpN5IupUlEEj681B0VKy iCe90A140jBfVST34MdwclFeDjbG26vQ4mVM4Sy1gsoS7BIBsmW+UD6KUzpilE6060cS Grlg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WN37+KqseeIgXipiGu6LDKAfte7NHaQ3es3PGBSRuiY=; b=kkl5+N/8Smvs3Yzw3/MxDyydfQl+fi1/x9/guHfxSQ8wH/XvPZtBEpZib56mVNbj/6 9SZy+hTb08YcewNub/sDOvXwAAWEtPQEpbPZd1tdSMNs93x1E0P8qnskvtiogi7K+v4M egMG+2Q0QWlTJNr+2NPzjWWdWD4XvSZlwMwtkS1iY4VUKp9h1AFCX68Kb8aw4Tz7JYgi pYsdUs5xspQfPDj13kz+gHp0rN73qBgMG59O6w3gH7uRPsWsQGTIyQTi5zEzPvz1hgj3 Nk+to5nQsNNH8pGQ4gB+R9pXbqQzOFYwihOG2qNR0n+4aQUMA4YnmJpQRfnnKL4UOLlS VNvw== X-Gm-Message-State: ALQs6tA0J/neE734YqeTBjwRn8n9a/9QkLk5piJp/VRHKma8V/6BpvH/ bAgPqZYHjq3adVPApVXqoh/p2MFB0Fk= X-Google-Smtp-Source: AB8JxZpsvBPz94zKtmdvrr9cHGDd5DCvZwpRAOfutNz/iLxUN5ATcN9ajJgy5qvZ2p7zhpRZMNDFhw== X-Received: by 2002:a63:3c47:: with SMTP id i7-v6mr26220836pgn.254.1525563427420; Sat, 05 May 2018 16:37:07 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Sun, 6 May 2018 11:35:10 +1200 Message-Id: <1525563325-62963-6-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1525563325-62963-1-git-send-email-mjc@sifive.com> References: <1525563325-62963-1-git-send-email-mjc@sifive.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [PULL 05/20] RISC-V: Remove unused class definitions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@groups.riscv.org, Michael Clark , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Removes a whole lot of unnecessary boilerplate code. Machines don't need to be objects. The expansion of the SOC object model for the RISC-V machines will happen in the future as SiFive plans to add their FE310 and FU540 SOCs to QEMU. However, it seems that this present boilerplate is complete unnecessary. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis --- hw/riscv/riscv_hart.c | 6 ------ hw/riscv/sifive_e.c | 25 ------------------------- hw/riscv/sifive_u.c | 25 ------------------------- hw/riscv/spike.c | 20 -------------------- hw/riscv/virt.c | 25 ------------------------- include/hw/riscv/sifive_e.h | 5 ----- include/hw/riscv/sifive_u.h | 5 ----- include/hw/riscv/spike.h | 7 ------- include/hw/riscv/virt.h | 5 ----- 9 files changed, 123 deletions(-) diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c index 14e3c186fea7..75ba7ed579bd 100644 --- a/hw/riscv/riscv_hart.c +++ b/hw/riscv/riscv_hart.c @@ -68,16 +68,10 @@ static void riscv_harts_class_init(ObjectClass *klass, = void *data) dc->realize =3D riscv_harts_realize; } =20 -static void riscv_harts_init(Object *obj) -{ - /* RISCVHartArrayState *s =3D SIFIVE_COREPLEX(obj); */ -} - static const TypeInfo riscv_harts_info =3D { .name =3D TYPE_RISCV_HART_ARRAY, .parent =3D TYPE_SYS_BUS_DEVICE, .instance_size =3D sizeof(RISCVHartArrayState), - .instance_init =3D riscv_harts_init, .class_init =3D riscv_harts_class_init, }; =20 diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 3e523a073469..22dc526713c2 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -194,24 +194,6 @@ static void riscv_sifive_e_init(MachineState *machine) } } =20 -static int riscv_sifive_e_sysbus_device_init(SysBusDevice *sysbusdev) -{ - return 0; -} - -static void riscv_sifive_e_class_init(ObjectClass *klass, void *data) -{ - SysBusDeviceClass *k =3D SYS_BUS_DEVICE_CLASS(klass); - k->init =3D riscv_sifive_e_sysbus_device_init; -} - -static const TypeInfo riscv_sifive_e_device =3D { - .name =3D TYPE_SIFIVE_E, - .parent =3D TYPE_SYS_BUS_DEVICE, - .instance_size =3D sizeof(SiFiveEState), - .class_init =3D riscv_sifive_e_class_init, -}; - static void riscv_sifive_e_machine_init(MachineClass *mc) { mc->desc =3D "RISC-V Board compatible with SiFive E SDK"; @@ -220,10 +202,3 @@ static void riscv_sifive_e_machine_init(MachineClass *= mc) } =20 DEFINE_MACHINE("sifive_e", riscv_sifive_e_machine_init) - -static void riscv_sifive_e_register_types(void) -{ - type_register_static(&riscv_sifive_e_device); -} - -type_init(riscv_sifive_e_register_types); diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index adc6c2266275..5bb495ab9a6c 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -301,31 +301,6 @@ static void riscv_sifive_u_init(MachineState *machine) SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE); } =20 -static int riscv_sifive_u_sysbus_device_init(SysBusDevice *sysbusdev) -{ - return 0; -} - -static void riscv_sifive_u_class_init(ObjectClass *klass, void *data) -{ - SysBusDeviceClass *k =3D SYS_BUS_DEVICE_CLASS(klass); - k->init =3D riscv_sifive_u_sysbus_device_init; -} - -static const TypeInfo riscv_sifive_u_device =3D { - .name =3D TYPE_SIFIVE_U, - .parent =3D TYPE_SYS_BUS_DEVICE, - .instance_size =3D sizeof(SiFiveUState), - .class_init =3D riscv_sifive_u_class_init, -}; - -static void riscv_sifive_u_register_types(void) -{ - type_register_static(&riscv_sifive_u_device); -} - -type_init(riscv_sifive_u_register_types); - static void riscv_sifive_u_machine_init(MachineClass *mc) { mc->desc =3D "RISC-V Board compatible with SiFive U SDK"; diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index cf7f9bcc3950..44eab94e17ef 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -334,18 +334,6 @@ static void spike_v1_09_1_board_init(MachineState *mac= hine) smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE); } =20 -static const TypeInfo spike_v_1_09_1_device =3D { - .name =3D TYPE_RISCV_SPIKE_V1_09_1_BOARD, - .parent =3D TYPE_SYS_BUS_DEVICE, - .instance_size =3D sizeof(SpikeState), -}; - -static const TypeInfo spike_v_1_10_0_device =3D { - .name =3D TYPE_RISCV_SPIKE_V1_10_0_BOARD, - .parent =3D TYPE_SYS_BUS_DEVICE, - .instance_size =3D sizeof(SpikeState), -}; - static void spike_v1_09_1_machine_init(MachineClass *mc) { mc->desc =3D "RISC-V Spike Board (Privileged ISA v1.9.1)"; @@ -363,11 +351,3 @@ static void spike_v1_10_0_machine_init(MachineClass *m= c) =20 DEFINE_MACHINE("spike_v1.9.1", spike_v1_09_1_machine_init) DEFINE_MACHINE("spike_v1.10", spike_v1_10_0_machine_init) - -static void riscv_spike_board_register_types(void) -{ - type_register_static(&spike_v_1_09_1_device); - type_register_static(&spike_v_1_10_0_device); -} - -type_init(riscv_spike_board_register_types); diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index c2aa795981d2..88b9ad509315 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -382,24 +382,6 @@ static void riscv_virt_board_init(MachineState *machin= e) serial_hd(0), DEVICE_LITTLE_ENDIAN); } =20 -static int riscv_virt_board_sysbus_device_init(SysBusDevice *sysbusdev) -{ - return 0; -} - -static void riscv_virt_board_class_init(ObjectClass *klass, void *data) -{ - SysBusDeviceClass *k =3D SYS_BUS_DEVICE_CLASS(klass); - k->init =3D riscv_virt_board_sysbus_device_init; -} - -static const TypeInfo riscv_virt_board_device =3D { - .name =3D TYPE_RISCV_VIRT_BOARD, - .parent =3D TYPE_SYS_BUS_DEVICE, - .instance_size =3D sizeof(RISCVVirtState), - .class_init =3D riscv_virt_board_class_init, -}; - static void riscv_virt_board_machine_init(MachineClass *mc) { mc->desc =3D "RISC-V VirtIO Board (Privileged ISA v1.10)"; @@ -408,10 +390,3 @@ static void riscv_virt_board_machine_init(MachineClass= *mc) } =20 DEFINE_MACHINE("virt", riscv_virt_board_machine_init) - -static void riscv_virt_board_register_types(void) -{ - type_register_static(&riscv_virt_board_device); -} - -type_init(riscv_virt_board_register_types); diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h index 0aebc576c1d5..12ad6d2ebb2b 100644 --- a/include/hw/riscv/sifive_e.h +++ b/include/hw/riscv/sifive_e.h @@ -19,11 +19,6 @@ #ifndef HW_SIFIVE_E_H #define HW_SIFIVE_E_H =20 -#define TYPE_SIFIVE_E "riscv.sifive_e" - -#define SIFIVE_E(obj) \ - OBJECT_CHECK(SiFiveEState, (obj), TYPE_SIFIVE_E) - typedef struct SiFiveEState { /*< private >*/ SysBusDevice parent_obj; diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index be38aa09da20..94a390566e59 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -19,11 +19,6 @@ #ifndef HW_SIFIVE_U_H #define HW_SIFIVE_U_H =20 -#define TYPE_SIFIVE_U "riscv.sifive_u" - -#define SIFIVE_U(obj) \ - OBJECT_CHECK(SiFiveUState, (obj), TYPE_SIFIVE_U) - typedef struct SiFiveUState { /*< private >*/ SysBusDevice parent_obj; diff --git a/include/hw/riscv/spike.h b/include/hw/riscv/spike.h index d85a64e33d86..8410430614b7 100644 --- a/include/hw/riscv/spike.h +++ b/include/hw/riscv/spike.h @@ -19,12 +19,6 @@ #ifndef HW_SPIKE_H #define HW_SPIKE_H =20 -#define TYPE_RISCV_SPIKE_V1_09_1_BOARD "riscv.spike_v1_9_1" -#define TYPE_RISCV_SPIKE_V1_10_0_BOARD "riscv.spike_v1_10" - -#define SPIKE(obj) \ - OBJECT_CHECK(SpikeState, (obj), TYPE_RISCV_SPIKE_BOARD) - typedef struct { /*< private >*/ SysBusDevice parent_obj; @@ -35,7 +29,6 @@ typedef struct { int fdt_size; } SpikeState; =20 - enum { SPIKE_MROM, SPIKE_CLINT, diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index 655e85ddbd3c..b91a4125dd61 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -19,10 +19,6 @@ #ifndef HW_VIRT_H #define HW_VIRT_H =20 -#define TYPE_RISCV_VIRT_BOARD "riscv.virt" -#define VIRT(obj) \ - OBJECT_CHECK(RISCVVirtState, (obj), TYPE_RISCV_VIRT_BOARD) - typedef struct { /*< private >*/ SysBusDevice parent_obj; @@ -45,7 +41,6 @@ enum { VIRT_DRAM }; =20 - enum { UART0_IRQ =3D 10, VIRTIO_IRQ =3D 1, /* 1 to 8 */ --=20 2.7.0