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X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [PATCH v8 33/35] RISC-V: Add public API for the CSR dispatch table X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Bastian Koppelmann , Palmer Dabbelt , Michael Clark , Alistair Francis , patches@groups.riscv.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This allows hardware and/or derived cpu instances to override or implement new CSR operations. Cc: Sagar Karandikar Cc: Bastian Koppelmann Cc: Palmer Dabbelt Cc: Alistair Francis Signed-off-by: Michael Clark --- target/riscv/cpu.h | 18 ++++++++++++++++++ target/riscv/csr.c | 35 ++++++++++++++++++----------------- 2 files changed, 36 insertions(+), 17 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 6fb0014..4030530 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -301,6 +301,24 @@ static inline target_ulong csr_read_helper(CPURISCVSta= te *env, int csrno) return val; } =20 +typedef int (*riscv_csr_predicate_fn)(CPURISCVState *env, int csrno); +typedef int (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, + target_ulong *ret_value); +typedef int (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, + target_ulong new_value); +typedef int (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, + target_ulong *ret_value, target_ulong new_value, target_ulong write_ma= sk); + +typedef struct { + riscv_csr_predicate_fn predicate; + riscv_csr_read_fn read; + riscv_csr_write_fn write; + riscv_csr_op_fn op; +} riscv_csr_operations; + +void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); +void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); + #include "exec/cpu-all.h" =20 #endif /* RISCV_CPU_H */ diff --git a/target/riscv/csr.c b/target/riscv/csr.c index da66908..25a7e26 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -23,28 +23,29 @@ #include "qemu/main-loop.h" #include "exec/exec-all.h" =20 +/* CSR function table */ =20 -/* Control and Status Register function table forward declaration */ +static riscv_csr_operations csr_ops[]; =20 -typedef int (*riscv_csr_predicate_fn)(CPURISCVState *env, int csrno); -typedef int (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, - target_ulong *ret_value); -typedef int (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, - target_ulong new_value); -typedef int (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, - target_ulong *ret_value, target_ulong new_value, target_ulong write_ma= sk); +/* CSR function table constants */ =20 -typedef struct { - riscv_csr_predicate_fn predicate; - riscv_csr_read_fn read; - riscv_csr_write_fn write; - riscv_csr_op_fn op; -} riscv_csr_operations; +enum { + CSR_TABLE_SIZE =3D 0xfff +}; + +/* CSR function table public API */ =20 -static const riscv_csr_operations csr_ops[]; +void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops) +{ + *ops =3D csr_ops[csrno & CSR_TABLE_SIZE]; +} =20 +void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops) +{ + csr_ops[csrno & CSR_TABLE_SIZE] =3D *ops; +} =20 -/* Predicates */ +/* CSR function table predicates (private) */ =20 static int fs(CPURISCVState *env, int csrno) { @@ -780,7 +781,7 @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_u= long *ret_value, =20 /* Control and Status Register function table */ =20 -static const riscv_csr_operations csr_ops[0xfff] =3D { +static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { /* User Floating-Point CSRs */ [CSR_FFLAGS] =3D { fs, read_fflags, write_fflags = }, [CSR_FRM] =3D { fs, read_frm, write_frm = }, --=20 2.7.0