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[122.58.167.38]) by smtp.gmail.com with ESMTPSA id e10sm29577549pfn.67.2018.04.25.16.48.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 25 Apr 2018 16:48:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=3LuVaax1i8UgwGY8lXKu/Vav3ij166aw/lwDm/z4Kec=; b=RNgoV2+6cVfZMWTSKrgDOonQkB26XiUnZLElHBkYOoRhc8igV+h59FmlvDhKORl4GF kwhDArLYcLGHpLLMEvOhyyGJsBVpKcWfmRbtLECYxReV4Vpo+4P44+Fo33CmqSsXHwrG LMnuOex3GJqEv0hKsD8QdWVKCRYIK2MovP1j9RYTUbBJluffxprGkYyQwMJV1d+6QMK6 F9H7Slcwu094Sm8ChiGULcDFyl2GdViKvUb/7P99vBfGA0HA1SeQmYK4hhzJxDtRsTMY cvtkM9P2cVVKIBjHadb//gnwU3+T3i/ZaGB0HGLzzuXPSy474kG4w12dMy3xqvRV7DdF mT2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=3LuVaax1i8UgwGY8lXKu/Vav3ij166aw/lwDm/z4Kec=; b=DwXhhGsUuUYBQPH5n/JtGhE93slRWvdmmp/y4QSP17cZddqixE5Swi1DthDDNLv8lp EZ+Axnt5XA5VsqXFMBE3EswjZ4piwI1jmxMaQ41gZnpUrdf/bxTM5g+4xO6WbRkP/sMu ZiWXhcqxUJcet8sHmPmGJpMKLhHt9Dzoq9Kkbf/NSEqQXyJROaoGUqRNIhRP+MJIFlHz 6I4RyB6A+bwawWRlxLhQ8mtk03FBz4tKcwlESRhZqYYc1N4+v9SvPsv13yEoT811/2+u OFjgLj/7MhZbZdl8THH1rbtOp2zCRp+b6QnKkTPc7he59wQyQYG1TKf9eftooy99aoTc kJoA== X-Gm-Message-State: ALQs6tBHUG+ilcnIx+bovBdwx+jnIKRdi+ds3MwpkErID4OlCJ70GqiV 6TT/uvg58ZwCgfuWexRimVlYds7Wsw0= X-Google-Smtp-Source: AIpwx48BzhjI8PyWgJ5ZI4cMAKPJVlpTemStVWAFQPknfbEzUuviiFyuDBDrYwXTnmHnhiQ5FuXB+Q== X-Received: by 2002:a17:902:67c2:: with SMTP id g2-v6mr31202333pln.93.1524700114329; Wed, 25 Apr 2018 16:48:34 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Thu, 26 Apr 2018 11:45:27 +1200 Message-Id: <1524699938-6764-25-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1524699938-6764-1-git-send-email-mjc@sifive.com> References: <1524699938-6764-1-git-send-email-mjc@sifive.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [PATCH v8 24/35] RISC-V: Allow setting and clearing multiple irqs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Bastian Koppelmann , Palmer Dabbelt , Michael Clark , Alistair Francis , patches@groups.riscv.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Change the API of riscv_set_local_interrupt to take a write mask and value to allow setting and clearing of multiple local interrupts atomically in a single call. Rename the new function to riscv_cpu_update_mip. Cc: Sagar Karandikar Cc: Bastian Koppelmann Cc: Palmer Dabbelt Cc: Alistair Francis Signed-off-by: Michael Clark --- hw/riscv/sifive_clint.c | 8 ++++---- hw/riscv/sifive_plic.c | 4 ++-- target/riscv/cpu.h | 8 +++----- target/riscv/op_helper.c | 23 ++++++++++++++--------- 4 files changed, 23 insertions(+), 20 deletions(-) diff --git a/hw/riscv/sifive_clint.c b/hw/riscv/sifive_clint.c index 7cc606e..909929b 100644 --- a/hw/riscv/sifive_clint.c +++ b/hw/riscv/sifive_clint.c @@ -47,12 +47,12 @@ static void sifive_clint_write_timecmp(RISCVCPU *cpu, u= int64_t value) if (cpu->env.timecmp <=3D rtc_r) { /* if we're setting an MTIMECMP value in the "past", immediately raise the timer interrupt */ - riscv_set_local_interrupt(cpu, MIP_MTIP, 1); + riscv_cpu_update_mip(cpu, MIP_MTIP, -1); return; } =20 /* otherwise, set up the future timer interrupt */ - riscv_set_local_interrupt(cpu, MIP_MTIP, 0); + riscv_cpu_update_mip(cpu, MIP_MTIP, 0); diff =3D cpu->env.timecmp - rtc_r; /* back to ns (note args switched in muldiv64) */ next =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + @@ -67,7 +67,7 @@ static void sifive_clint_write_timecmp(RISCVCPU *cpu, uin= t64_t value) static void sifive_clint_timer_cb(void *opaque) { RISCVCPU *cpu =3D opaque; - riscv_set_local_interrupt(cpu, MIP_MTIP, 1); + riscv_cpu_update_mip(cpu, MIP_MTIP, -1); } =20 /* CPU wants to read rtc or timecmp register */ @@ -132,7 +132,7 @@ static void sifive_clint_write(void *opaque, hwaddr add= r, uint64_t value, if (!env) { error_report("clint: invalid timecmp hartid: %zu", hartid); } else if ((addr & 0x3) =3D=3D 0) { - riscv_set_local_interrupt(RISCV_CPU(cpu), MIP_MSIP, value !=3D= 0); + riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_MSIP, -!!value); } else { error_report("clint: invalid sip write: %08x", (uint32_t)addr); } diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c index 04e39e4..fa0298d 100644 --- a/hw/riscv/sifive_plic.c +++ b/hw/riscv/sifive_plic.c @@ -141,10 +141,10 @@ static void sifive_plic_update(SiFivePLICState *plic) int level =3D sifive_plic_irqs_pending(plic, addrid); switch (mode) { case PLICMode_M: - riscv_set_local_interrupt(RISCV_CPU(cpu), MIP_MEIP, level); + riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_MEIP, -!!level); break; case PLICMode_S: - riscv_set_local_interrupt(RISCV_CPU(cpu), MIP_SEIP, level); + riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_SEIP, -!!level); break; default: break; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index e0608e6..5ac1482 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -247,7 +247,6 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr= addr, uintptr_t retaddr); int riscv_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw, int mmu_idx); - char *riscv_isa_string(RISCVCPU *cpu); void riscv_cpu_list(FILE *f, fprintf_function cpu_fprintf); =20 @@ -256,6 +255,9 @@ void riscv_cpu_list(FILE *f, fprintf_function cpu_fprin= tf); #define cpu_list riscv_cpu_list #define cpu_mmu_index riscv_cpu_mmu_index =20 +#ifndef CONFIG_USER_ONLY +uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value= ); +#endif void riscv_set_mode(CPURISCVState *env, target_ulong newpriv); =20 void riscv_translate_init(void); @@ -286,10 +288,6 @@ void csr_write_helper(CPURISCVState *env, target_ulong= val_to_write, target_ulong csrno); target_ulong csr_read_helper(CPURISCVState *env, target_ulong csrno); =20 -#ifndef CONFIG_USER_ONLY -void riscv_set_local_interrupt(RISCVCPU *cpu, target_ulong mask, int value= ); -#endif - #include "exec/cpu-all.h" =20 #endif /* RISCV_CPU_H */ diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 7d3f1ee..2a7f045 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -171,10 +171,8 @@ void csr_write_helper(CPURISCVState *env, target_ulong= val_to_write, */ qemu_mutex_lock_iothread(); RISCVCPU *cpu =3D riscv_env_get_cpu(env); - riscv_set_local_interrupt(cpu, MIP_SSIP, - (val_to_write & MIP_SSIP) !=3D 0); - riscv_set_local_interrupt(cpu, MIP_STIP, - (val_to_write & MIP_STIP) !=3D 0); + riscv_cpu_update_mip(cpu, MIP_SSIP | MIP_STIP, + (val_to_write & (MIP_SSIP | MIP_STIP))); /* * csrs, csrc on mip.SEIP is not decomposable into separate read a= nd * write steps, so a different implementation is needed @@ -643,16 +641,23 @@ target_ulong helper_csrrc(CPURISCVState *env, target_= ulong src, #ifndef CONFIG_USER_ONLY =20 /* iothread_mutex must be held */ -void riscv_set_local_interrupt(RISCVCPU *cpu, target_ulong mask, int value) +uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value) { - target_ulong old_mip =3D cpu->env.mip; - cpu->env.mip =3D (old_mip & ~mask) | (value ? mask : 0); + CPURISCVState *env =3D &cpu->env; + uint32_t old_mip, new_mip; =20 - if (cpu->env.mip && !old_mip) { + do { + old_mip =3D atomic_read(&env->mip); + new_mip =3D (old_mip & ~mask) | (value & mask); + } while (atomic_cmpxchg(&env->mip, old_mip, new_mip) !=3D old_mip); + + if (new_mip && !old_mip) { cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD); - } else if (!cpu->env.mip && old_mip) { + } else if (!new_mip && old_mip) { cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_HARD); } + + return old_mip; } =20 void riscv_set_mode(CPURISCVState *env, target_ulong newpriv) --=20 2.7.0