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[122.58.167.38]) by smtp.gmail.com with ESMTPSA id e10sm29577549pfn.67.2018.04.25.16.48.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 25 Apr 2018 16:48:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=poslSpMX+IotLKyB57Civ9YJWdexzRi4MqE6wAUeshA=; b=DyULQDaaVwyxyuTSVl/vUUG7zQg4V/0a6jGyigxRLVoPPK86lx3QgwKloQ/Fx4V4Ty 02lYd01aCyYJ2SZ6RmECWglB4uVOK5kcXbKGhW5iuXz5k+omy+WvtID5DdaazHcSJeoc hl4H+FRfSLFHsYNPkI0Qcdib1ldk0LQOKA6KASZXnE4F9en7u74TSvTGo38/Cyn47NPy ckrUrr36PQ1veLuWraTpTXo3xzhU3oKQUNrOKh/9kBtO6KhwmOxyL77pdbnS6zQlTZJl fB/lWYXEsR90hZG62fKKrTb3Z0iyxTXLcKdldBFbsq1NIOwakdkwIgDJwdtB+oBmu8jr z7tg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=poslSpMX+IotLKyB57Civ9YJWdexzRi4MqE6wAUeshA=; b=GMfim7xZAmbNR3zuqpYG+6yh+YviSmlyiYByvnc0EftD97s342nB+qqUHWVpkBJSM9 Ke/9lxsai98J2TqJ85itcvSbz5LrqHrjyrLcYJvNTYsGjBAszLehZrCvQeYWZbHZk9Zk /pgS8lHZFHOytISbBJ71dErf55x5E23Dgug7Ld/TDjW4VbERjK49TgCpQL/aJUyQbQlv aKJbWu/akx05QGlhzGtNjMq+BgCMsYJhz5lFQzgTybmZDLfFAFpDvRYpRZ5FjDaou/N3 S3zuWtU1OO5bJCgaW4o/3zP+5/W+dFEhQcP8lMnzHro+lGcIPUywNloHHK7g6+hygehu LYRg== X-Gm-Message-State: ALQs6tC9rhC5HufIyPhMJ7WXh0ukB4I4qLP0h4kfsfAKY3zsR9jg5tgv obGzQb0jch36nxeRa31GG9em3lqFDZY= X-Google-Smtp-Source: AIpwx4+BTmSS9K7kj8fTZxIVQUle/uLAqDxOnGiKWZ829qe8Jzd/H5p0aKUiYqukgML8eqNb/qG2wg== X-Received: by 10.99.122.67 with SMTP id j3mr25088171pgn.172.1524700099472; Wed, 25 Apr 2018 16:48:19 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Thu, 26 Apr 2018 11:45:23 +1200 Message-Id: <1524699938-6764-21-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1524699938-6764-1-git-send-email-mjc@sifive.com> References: <1524699938-6764-1-git-send-email-mjc@sifive.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH v8 20/35] RISC-V: Use [ms]counteren CSRs when priv ISA >= v1.10 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Bastian Koppelmann , Palmer Dabbelt , Michael Clark , Alistair Francis , patches@groups.riscv.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Privileged ISA v1.9.1 defines mscounteren and mucounteren: * mscounteren contains a mask of counters available to S-mode * mucounteren contains a mask of counters available to U-mode Privileged ISA v1.10 defines mcounteren and scounteren: * mcounteren contains a mask of counters available to S-mode * scounteren contains a mask of counters available to U-mode mcounteren and scounteren CSR registers were implemented however they were not honoured for counter accesses when the privilege ISA was >=3D v1.10. This fix solves the issue by coalescing the counter enable registers. In addition the code now generates illegal instruction exceptions for accesses to the counter enabled registers depending on the privileged ISA version. - Coalesce mscounteren and mcounteren into one variable - Coalesce mucounteren and scounteren into one variable - Makes mcounteren and scounteren CSR accesses generate illegal instructions when the privileged ISA <=3D v1.9.1 - Makes mscounteren and mucounteren CSR accesses generate illegal instructions when the privileged ISA >=3D v1.10 Cc: Sagar Karandikar Cc: Bastian Koppelmann Cc: Palmer Dabbelt Cc: Alistair Francis Signed-off-by: Michael Clark --- target/riscv/cpu.h | 6 ++--- target/riscv/op_helper.c | 63 +++++++++++++++++++++++++++++++++++++-------= ---- 2 files changed, 51 insertions(+), 18 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 890cd96..e0608e6 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -151,10 +151,8 @@ struct CPURISCVState { target_ulong mcause; target_ulong mtval; /* since: priv-1.10.0 */ =20 - uint32_t mucounteren; - uint32_t mscounteren; - target_ulong scounteren; /* since: priv-1.10.0 */ - target_ulong mcounteren; /* since: priv-1.10.0 */ + target_ulong scounteren; + target_ulong mcounteren; =20 target_ulong sscratch; target_ulong mscratch; diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 88c263a..2daf07c 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -227,11 +227,19 @@ void csr_write_helper(CPURISCVState *env, target_ulon= g val_to_write, break; #endif case CSR_MUCOUNTEREN: - env->mucounteren =3D val_to_write; - break; + if (env->priv_ver <=3D PRIV_VERSION_1_09_1) { + env->scounteren =3D val_to_write; + break; + } else { + goto do_illegal; + } case CSR_MSCOUNTEREN: - env->mscounteren =3D val_to_write; - break; + if (env->priv_ver <=3D PRIV_VERSION_1_09_1) { + env->mcounteren =3D val_to_write; + break; + } else { + goto do_illegal; + } case CSR_SSTATUS: { target_ulong ms =3D env->mstatus; target_ulong mask =3D SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_UIE @@ -287,8 +295,12 @@ void csr_write_helper(CPURISCVState *env, target_ulong= val_to_write, } break; case CSR_SCOUNTEREN: - env->scounteren =3D val_to_write; - break; + if (env->priv_ver >=3D PRIV_VERSION_1_10_0) { + env->scounteren =3D val_to_write; + break; + } else { + goto do_illegal; + } case CSR_SSCRATCH: env->sscratch =3D val_to_write; break; @@ -308,8 +320,12 @@ void csr_write_helper(CPURISCVState *env, target_ulong= val_to_write, } break; case CSR_MCOUNTEREN: - env->mcounteren =3D val_to_write; - break; + if (env->priv_ver >=3D PRIV_VERSION_1_10_0) { + env->mcounteren =3D val_to_write; + break; + } else { + goto do_illegal; + } case CSR_MSCRATCH: env->mscratch =3D val_to_write; break; @@ -347,6 +363,9 @@ void csr_write_helper(CPURISCVState *env, target_ulong = val_to_write, pmpaddr_csr_write(env, csrno - CSR_PMPADDR0, val_to_write); break; #endif +#if !defined(CONFIG_USER_ONLY) + do_illegal: +#endif default: do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); } @@ -360,8 +379,8 @@ void csr_write_helper(CPURISCVState *env, target_ulong = val_to_write, target_ulong csr_read_helper(CPURISCVState *env, target_ulong csrno) { #ifndef CONFIG_USER_ONLY - target_ulong ctr_en =3D env->priv =3D=3D PRV_U ? env->mucounteren : - env->priv =3D=3D PRV_S ? env->mscounteren : -1U; + target_ulong ctr_en =3D env->priv =3D=3D PRV_U ? env->scounteren : + env->priv =3D=3D PRV_S ? env->mcounteren : -1U; #else target_ulong ctr_en =3D -1; #endif @@ -436,9 +455,17 @@ target_ulong csr_read_helper(CPURISCVState *env, targe= t_ulong csrno) #endif break; case CSR_MUCOUNTEREN: - return env->mucounteren; + if (env->priv_ver <=3D PRIV_VERSION_1_09_1) { + return env->scounteren; + } else { + break; /* illegal instruction */ + } case CSR_MSCOUNTEREN: - return env->mscounteren; + if (env->priv_ver <=3D PRIV_VERSION_1_09_1) { + return env->mcounteren; + } else { + break; /* illegal instruction */ + } case CSR_SSTATUS: { target_ulong mask =3D SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS @@ -463,7 +490,11 @@ target_ulong csr_read_helper(CPURISCVState *env, targe= t_ulong csrno) case CSR_STVEC: return env->stvec; case CSR_SCOUNTEREN: - return env->scounteren; + if (env->priv_ver >=3D PRIV_VERSION_1_10_0) { + return env->scounteren; + } else { + break; /* illegal instruction */ + } case CSR_SCAUSE: return env->scause; case CSR_SATP: /* CSR_SPTBR */ @@ -508,7 +539,11 @@ target_ulong csr_read_helper(CPURISCVState *env, targe= t_ulong csrno) case CSR_MTVEC: return env->mtvec; case CSR_MCOUNTEREN: - return env->mcounteren; + if (env->priv_ver >=3D PRIV_VERSION_1_10_0) { + return env->mcounteren; + } else { + break; /* illegal instruction */ + } case CSR_MEDELEG: return env->medeleg; case CSR_MIDELEG: --=20 2.7.0