From nobody Tue Feb 10 08:27:08 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 15228836857618.144152547554427; Wed, 4 Apr 2018 16:14:45 -0700 (PDT) Received: from localhost ([::1]:37781 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f3rbg-0005eb-45 for importer@patchew.org; Wed, 04 Apr 2018 19:14:20 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54580) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f3rZh-0004Qm-Nu for qemu-devel@nongnu.org; Wed, 04 Apr 2018 19:12:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1f3rZg-00048M-8e for qemu-devel@nongnu.org; Wed, 04 Apr 2018 19:12:17 -0400 Received: from out5-smtp.messagingengine.com ([66.111.4.29]:44687) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1f3rZg-00047g-3T for qemu-devel@nongnu.org; Wed, 04 Apr 2018 19:12:16 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id C587D21B6D; Wed, 4 Apr 2018 19:11:18 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute4.internal (MEProxy); Wed, 04 Apr 2018 19:11:18 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 81439E43C8; Wed, 4 Apr 2018 19:11:18 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc; s=mesmtp; bh=7cOVQIGpNqSEIO h+M1rVhj0yoehwA4kwYTXYU8bkJUs=; b=HCbSMbXeDeZj06b+gWXTdmNka5QW0S XFiRiiQybshKuOssF+riELwOKMrXF0ABQ3TByCPX9SqFIlpSBqMj6qIc5Jtn/s9d 5o+mvpc0d46drRHxbxFhpD4lMNSyHQVvLpd9HfheUsWrYN8u10E1njq73aAH96DY cv1bOIAL08Zss= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc; s= fm2; bh=7cOVQIGpNqSEIOh+M1rVhj0yoehwA4kwYTXYU8bkJUs=; b=RZkMChsR AZWsaw+Zxgm0V/vxMiQ8wrwK3jUtsuWYYBnc+3exkWrYVn1FPKbakXeEVwmjz1DM 2w5drGW85zptM99lg2CUbycgxALXF8gtkaB+5aM7lBpfVyVHmhAAT/ej9iLLlfi9 urLxazR07z+wC1oPRbhlz5I8pq8zGC++ABFprswT/a4jPOZAiNENYO9a2D87P7v+ UZ3M/stpQzP3zHSUQt/seRY/4vb7FDjVbfKnb+uNln1d8u0SbCrkz2Q9Bd2sCEJG yvXrjMYpR2FY1cgLurnSQMYPtgCP+bvo4gFh6tDqgH2LPB5AMol9hqNUPrOK8QCZ MnZ+OEuOdhFxJA== X-ME-Sender: From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Wed, 4 Apr 2018 19:11:13 -0400 Message-Id: <1522883475-27858-14-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1522883475-27858-1-git-send-email-cota@braap.org> References: <1522883475-27858-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.29 Subject: [Qemu-devel] [PATCH v3 13/15] hardfloat: support float32/64 fused multiply-add X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Mark Cave-Ayland , Richard Henderson , Laurent Vivier , Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Performance results for fp-bench: 1. Intel(R) Core(TM) i7-6700K CPU @ 4.00GHz - before: fma-single: 74.73 MFlops fma-double: 74.54 MFlops - after: fma-single: 203.37 MFlops fma-double: 169.37 MFlops 2. ARM Aarch64 A57 @ 2.4GHz - before: fma-single: 23.24 MFlops fma-double: 23.70 MFlops - after: fma-single: 66.14 MFlops fma-double: 63.10 MFlops 3. IBM POWER8E @ 2.1 GHz - before: fma-single: 37.26 MFlops fma-double: 37.29 MFlops - after: fma-single: 48.90 MFlops fma-double: 59.51 MFlops Here having 3FP64 set to 1 pays off for x86_64: [1] 170.15 vs [0] 153.12 MFlops Signed-off-by: Emilio G. Cota --- fpu/softfloat.c | 169 ++++++++++++++++++++++++++++++++++++++++++++++++++++= ++-- 1 file changed, 165 insertions(+), 4 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 4323dc2..ce14c87 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -1574,8 +1574,9 @@ float16 __attribute__((flatten)) float16_muladd(float= 16 a, float16 b, float16 c, return float16_round_pack_canonical(pr, status); } =20 -float32 __attribute__((flatten)) float32_muladd(float32 a, float32 b, floa= t32 c, - int flags, float_status *s= tatus) +static float32 QEMU_SOFTFLOAT_ATTR +soft_float32_muladd(float32 a, float32 b, float32 c, int flags, + float_status *status) { FloatParts pa =3D float32_unpack_canonical(a, status); FloatParts pb =3D float32_unpack_canonical(b, status); @@ -1585,8 +1586,9 @@ float32 __attribute__((flatten)) float32_muladd(float= 32 a, float32 b, float32 c, return float32_round_pack_canonical(pr, status); } =20 -float64 __attribute__((flatten)) float64_muladd(float64 a, float64 b, floa= t64 c, - int flags, float_status *s= tatus) +static float64 QEMU_SOFTFLOAT_ATTR +soft_float64_muladd(float64 a, float64 b, float64 c, int flags, + float_status *status) { FloatParts pa =3D float64_unpack_canonical(a, status); FloatParts pb =3D float64_unpack_canonical(b, status); @@ -1597,6 +1599,165 @@ float64 __attribute__((flatten)) float64_muladd(flo= at64 a, float64 b, float64 c, } =20 /* + * FMA generator for softfloat-based condition checks. + * + * When (a || b) =3D=3D 0, there's no need to check for under/over flow, + * since we know the addend is (normal || 0) and the product is 0. + */ +#define GEN_FMA_SF(name, soft_t, host_t, host_fma_f, host_abs_f, min_norma= l) \ + static soft_t \ + name(soft_t a, soft_t b, soft_t c, int flags, float_status *s) \ + { \ + if (QEMU_NO_HARDFLOAT) { \ + goto soft; \ + } \ + soft_t ## _input_flush3(&a, &b, &c, s); \ + if (likely((soft_t ## _is_normal(a) || soft_t ## _is_zero(a)) && \ + (soft_t ## _is_normal(b) || soft_t ## _is_zero(b)) && \ + (soft_t ## _is_normal(c) || soft_t ## _is_zero(c)) && \ + !(flags & float_muladd_halve_result) && \ + can_use_fpu(s))) { \ + if (soft_t ## _is_zero(a) || soft_t ## _is_zero(b)) { \ + soft_t p, r; \ + host_t hp, hc, hr; \ + bool prod_sign; \ + \ + prod_sign =3D soft_t ## _is_neg(a) ^ soft_t ## _is_neg(b);= \ + prod_sign ^=3D !!(flags & float_muladd_negate_product); \ + p =3D soft_t ## _set_sign(soft_t ## _zero, prod_sign); \ + \ + if (flags & float_muladd_negate_c) { \ + c =3D soft_t ## _chs(c); \ + } \ + \ + hp =3D soft_t ## _to_ ## host_t(p); \ + hc =3D soft_t ## _to_ ## host_t(c); \ + hr =3D hp + hc; \ + r =3D host_t ## _to_ ## soft_t(hr); \ + return flags & float_muladd_negate_result ? \ + soft_t ## _chs(r) : r; \ + } else { \ + host_t ha, hb, hc, hr; \ + soft_t r; \ + soft_t sa =3D flags & float_muladd_negate_product ? \ + soft_t ## _chs(a) : a; \ + soft_t sc =3D flags & float_muladd_negate_c ? \ + soft_t ## _chs(c) : c; \ + \ + ha =3D soft_t ## _to_ ## host_t(sa); \ + hb =3D soft_t ## _to_ ## host_t(b); \ + hc =3D soft_t ## _to_ ## host_t(sc); \ + hr =3D host_fma_f(ha, hb, hc); \ + r =3D host_t ## _to_ ## soft_t(hr); \ + \ + if (unlikely(isinf(hr))) { \ + s->float_exception_flags |=3D float_flag_overflow; \ + } else if (unlikely(host_abs_f(hr) <=3D min_normal)) { \ + goto soft; \ + } \ + return flags & float_muladd_negate_result ? \ + soft_t ## _chs(r) : r; \ + } \ + } \ + soft: \ + return soft_ ## soft_t ## _muladd(a, b, c, flags, s); \ + } + +/* FMA generator for native floating point condition checks */ +#define GEN_FMA_FP(name, soft_t, host_t, host_fma_f, host_abs_f, min_norma= l) \ + static soft_t \ + name(soft_t a, soft_t b, soft_t c, int flags, float_status *s) \ + { \ + host_t ha, hb, hc; \ + \ + if (QEMU_NO_HARDFLOAT) { \ + goto soft; \ + } \ + soft_t ## _input_flush3(&a, &b, &c, s); \ + ha =3D soft_t ## _to_ ## host_t(a); \ + hb =3D soft_t ## _to_ ## host_t(b); \ + hc =3D soft_t ## _to_ ## host_t(c); \ + if (likely((fpclassify(ha) =3D=3D FP_NORMAL || = \ + fpclassify(ha) =3D=3D FP_ZERO) && = \ + (fpclassify(hb) =3D=3D FP_NORMAL || = \ + fpclassify(hb) =3D=3D FP_ZERO) && = \ + (fpclassify(hc) =3D=3D FP_NORMAL || = \ + fpclassify(hc) =3D=3D FP_ZERO) && = \ + !(flags & float_muladd_halve_result) && \ + can_use_fpu(s))) { \ + if (soft_t ## _is_zero(a) || soft_t ## _is_zero(b)) { \ + soft_t p, r; \ + host_t hp, hc, hr; \ + bool prod_sign; \ + \ + prod_sign =3D soft_t ## _is_neg(a) ^ soft_t ## _is_neg(b);= \ + prod_sign ^=3D !!(flags & float_muladd_negate_product); \ + p =3D soft_t ## _set_sign(soft_t ## _zero, prod_sign); \ + \ + if (flags & float_muladd_negate_c) { \ + c =3D soft_t ## _chs(c); \ + } \ + \ + hp =3D soft_t ## _to_ ## host_t(p); \ + hc =3D soft_t ## _to_ ## host_t(c); \ + hr =3D hp + hc; \ + r =3D host_t ## _to_ ## soft_t(hr); \ + return flags & float_muladd_negate_result ? \ + soft_t ## _chs(r) : r; \ + } else { \ + host_t hr; \ + \ + if (flags & float_muladd_negate_product) { \ + ha =3D -ha; \ + } \ + if (flags & float_muladd_negate_c) { \ + hc =3D -hc; \ + } \ + hr =3D host_fma_f(ha, hb, hc); \ + if (unlikely(isinf(hr))) { \ + s->float_exception_flags |=3D float_flag_overflow; \ + } else if (unlikely(host_abs_f(hr) <=3D min_normal)) { \ + goto soft; \ + } \ + if (flags & float_muladd_negate_result) { \ + hr =3D -hr; \ + } \ + return host_t ## _to_ ## soft_t(hr); \ + } \ + } \ + soft: \ + return soft_ ## soft_t ## _muladd(a, b, c, flags, s); \ + } + +GEN_FMA_SF(f32_muladd, float32, float, fmaf, fabsf, FLT_MIN) +GEN_FMA_SF(f64_muladd, float64, double, fma, fabs, DBL_MIN) +#undef GEN_FMA_SF + +GEN_FMA_FP(float_muladd, float32, float, fmaf, fabsf, FLT_MIN) +GEN_FMA_FP(double_muladd, float64, double, fma, fabs, DBL_MIN) +#undef GEN_FMA_FP + +float32 __attribute__((flatten)) +float32_muladd(float32 a, float32 b, float32 c, int flags, float_status *s) +{ + if (QEMU_HARDFLOAT_3F32_USE_FP) { + return float_muladd(a, b, c, flags, s); + } else { + return f32_muladd(a, b, c, flags, s); + } +} + +float64 __attribute__((flatten)) +float64_muladd(float64 a, float64 b, float64 c, int flags, float_status *s) +{ + if (QEMU_HARDFLOAT_3F64_USE_FP) { + return double_muladd(a, b, c, flags, s); + } else { + return f64_muladd(a, b, c, flags, s); + } +} + +/* * Returns the result of dividing the floating-point value `a' by the * corresponding value `b'. The operation is performed according to * the IEC/IEEE Standard for Binary Floating-Point Arithmetic. --=20 2.7.4