From nobody Sun Feb 8 23:28:44 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1522160436259714.9092657071881; Tue, 27 Mar 2018 07:20:36 -0700 (PDT) Received: from localhost ([::1]:34546 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f0pSl-0000GT-47 for importer@patchew.org; Tue, 27 Mar 2018 10:20:35 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45813) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f0pOO-0003JW-Vj for qemu-devel@nongnu.org; Tue, 27 Mar 2018 10:16:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1f0pOI-0006ka-Pg for qemu-devel@nongnu.org; Tue, 27 Mar 2018 10:16:04 -0400 Received: from mx3-rdu2.redhat.com ([66.187.233.73]:60758 helo=mx1.redhat.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1f0pO5-0006Ut-MM; Tue, 27 Mar 2018 10:15:45 -0400 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.rdu2.redhat.com [10.11.54.5]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 031084068026; Tue, 27 Mar 2018 14:15:45 +0000 (UTC) Received: from localhost.localdomain.com (ovpn-116-135.ams2.redhat.com [10.36.116.135]) by smtp.corp.redhat.com (Postfix) with ESMTP id 1A5FA6F9E4; Tue, 27 Mar 2018 14:15:42 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org Date: Tue, 27 Mar 2018 16:15:18 +0200 Message-Id: <1522160122-10744-5-git-send-email-eric.auger@redhat.com> In-Reply-To: <1522160122-10744-1-git-send-email-eric.auger@redhat.com> References: <1522160122-10744-1-git-send-email-eric.auger@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.11.54.5 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.5]); Tue, 27 Mar 2018 14:15:45 +0000 (UTC) X-Greylist: inspected by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.5]); Tue, 27 Mar 2018 14:15:45 +0000 (UTC) for IP:'10.11.54.5' DOMAIN:'int-mx05.intmail.prod.int.rdu2.redhat.com' HELO:'smtp.corp.redhat.com' FROM:'eric.auger@redhat.com' RCPT:'' X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.187.233.73 Subject: [Qemu-devel] [RFC 4/8] hw/intc/arm_gicv3: Implement register_redist_region API X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wei@redhat.com, marc.zyngier@arm.com, drjones@redhat.com, cdall@kernel.org, zhaoshenglong@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This patch defines and implements the register_redist_region() API for both arm_gicv3 and arm_gicv3_kvm. Virt machine now directly calls the function to set the single redistributor region. The associated memory region init is removed from gicv3_init_irqs_and_mmio. Signed-off-by: Eric Auger --- hw/arm/virt.c | 6 +++++- hw/intc/arm_gicv3.c | 21 +++++++++++++++++++++ hw/intc/arm_gicv3_common.c | 10 ++++++---- hw/intc/arm_gicv3_kvm.c | 38 ++++++++++++++++++++++++++++++++++= +--- include/hw/intc/arm_gicv3_common.h | 5 +++-- 5 files changed, 70 insertions(+), 10 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 94dcb12..0eef6aa 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -526,7 +526,11 @@ static void create_gic(VirtMachineState *vms, qemu_irq= *pic) gicbusdev =3D SYS_BUS_DEVICE(gicdev); sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base); if (type =3D=3D 3) { - sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base); + ARMGICv3CommonClass *agcc =3D ARM_GICV3_COMMON_GET_CLASS(gicdev); + + agcc->register_redist_region((GICv3State *)gicdev, + vms->memmap[VIRT_GIC_REDIST].base, + vms->memmap[VIRT_GIC_REDIST].size >> 17); } else { sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base); } diff --git a/hw/intc/arm_gicv3.c b/hw/intc/arm_gicv3.c index 479c667..37f7564 100644 --- a/hw/intc/arm_gicv3.c +++ b/hw/intc/arm_gicv3.c @@ -378,6 +378,26 @@ static void arm_gic_realize(DeviceState *dev, Error **= errp) gicv3_init_cpuif(s); } =20 +static int arm_gicv3_register_redist_region(GICv3State *s, hwaddr base, + uint32_t count) +{ + SysBusDevice *sbd =3D SYS_BUS_DEVICE(s); + + if (s->nb_redist_regions > 0) { + return -EINVAL; + } + + s->redist_region[s->nb_redist_regions].base =3D base; + s->redist_region[s->nb_redist_regions].count =3D count; + memory_region_init_io(&s->redist_region[s->nb_redist_regions].mr, OBJE= CT(s), + gic_ops, s, "gicv3_redist", 0x20000 * count); + sysbus_init_mmio(sbd, &s->redist_region[s->nb_redist_regions].mr); + sysbus_mmio_map(sbd, 1, base); + s->nb_redist_regions++; + + return 0; +} + static void arm_gicv3_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); @@ -385,6 +405,7 @@ static void arm_gicv3_class_init(ObjectClass *klass, vo= id *data) ARMGICv3Class *agc =3D ARM_GICV3_CLASS(klass); =20 agcc->post_load =3D arm_gicv3_post_load; + agcc->register_redist_region =3D arm_gicv3_register_redist_region; device_class_set_parent_realize(dc, arm_gic_realize, &agc->parent_real= ize); } =20 diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c index cb4ee0e..c662e06 100644 --- a/hw/intc/arm_gicv3_common.c +++ b/hw/intc/arm_gicv3_common.c @@ -199,12 +199,8 @@ void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_= handler handler, =20 memory_region_init_io(&s->iomem_dist, OBJECT(s), ops, s, "gicv3_dist", 0x10000); - memory_region_init_io(&s->redist_region[0].mr, OBJECT(s), - ops ? &ops[1] : NULL, s, - "gicv3_redist", 0x20000 * s->num_cpu); =20 sysbus_init_mmio(sbd, &s->iomem_dist); - sysbus_init_mmio(sbd, &s->redist_region[0].mr); } =20 static void arm_gicv3_common_realize(DeviceState *dev, Error **errp) @@ -384,6 +380,12 @@ static void arm_gic_common_linux_init(ARMLinuxBootIf *= obj, } } =20 +static inline +bool arm_gicv3_common_support_multiple_redist_regions(GICv3State *s) +{ + return s->support_multiple_redist_regions; +} + static Property arm_gicv3_common_properties[] =3D { DEFINE_PROP_UINT32("num-cpu", GICv3State, num_cpu, 1), DEFINE_PROP_UINT32("num-irq", GICv3State, num_irq, 32), diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c index a07bc55..b6a3faf 100644 --- a/hw/intc/arm_gicv3_kvm.c +++ b/hw/intc/arm_gicv3_kvm.c @@ -755,9 +755,6 @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Err= or **errp) =20 kvm_arm_register_device(&s->iomem_dist, -1, KVM_DEV_ARM_VGIC_GRP_ADDR, KVM_VGIC_V3_ADDR_TYPE_DIST, s->dev_fd); - kvm_arm_register_device(&s->redist_region[0].mr, -1, - KVM_DEV_ARM_VGIC_GRP_ADDR, - KVM_VGIC_V3_ADDR_TYPE_REDIST, s->dev_fd); =20 if (kvm_has_gsi_routing()) { /* set up irq routing */ @@ -788,6 +785,40 @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Er= ror **errp) } } =20 +static int kvm_arm_gicv3_register_redist_region(GICv3State *s, hwaddr base, + uint32_t count) +{ + SysBusDevice *sbd =3D SYS_BUS_DEVICE(s); + int n =3D s->nb_redist_regions; + char *name; + + if (!s->dev_fd) { + return -ENODEV; + } + + if (n > 0) { + return -EINVAL; + } + + name =3D g_strdup_printf("gicv3_redist_region[%d]", n); + + s->redist_region[n].base =3D base; + s->redist_region[n].count =3D count; + memory_region_init_io(&s->redist_region[n].mr, OBJECT(s), + NULL, s, name, count * 0x20000); + sysbus_init_mmio(sbd, &s->redist_region[n].mr); + + kvm_arm_register_device(&s->redist_region[n].mr, -1, + KVM_DEV_ARM_VGIC_GRP_ADDR, + KVM_VGIC_V3_ADDR_TYPE_REDIST, s->dev_fd); + + sysbus_mmio_map(sbd, n + 1, base); /* first region is DIST */ + + s->nb_redist_regions++; + g_free(name); + return 0; +} + static void kvm_arm_gicv3_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); @@ -796,6 +827,7 @@ static void kvm_arm_gicv3_class_init(ObjectClass *klass= , void *data) =20 agcc->pre_save =3D kvm_arm_gicv3_get; agcc->post_load =3D kvm_arm_gicv3_put; + agcc->register_redist_region =3D kvm_arm_gicv3_register_redist_region; device_class_set_parent_realize(dc, kvm_arm_gicv3_realize, &kgc->parent_realize); device_class_set_parent_reset(dc, kvm_arm_gicv3_reset, &kgc->parent_re= set); diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3= _common.h index 3cf132f..549ccc3 100644 --- a/include/hw/intc/arm_gicv3_common.h +++ b/include/hw/intc/arm_gicv3_common.h @@ -220,6 +220,7 @@ struct GICv3State { MemoryRegion iomem_dist; /* Distributor */ GICv3RDISTRegion redist_region[GICV3_MAX_RDIST_REGIONS]; uint32_t nb_redist_regions; + bool support_multiple_redist_regions; =20 uint32_t num_cpu; uint32_t num_irq; @@ -297,8 +298,8 @@ typedef struct ARMGICv3CommonClass { =20 void (*pre_save)(GICv3State *s); void (*post_load)(GICv3State *s); - /* register an RDIST region at @base, containing @pfns 64kB pages */ - int (*register_redist_region)(GICv3State *s, hwaddr base, uint32_t pfn= s); + /* register an RDIST region at @base, containing @count redistributors= */ + int (*register_redist_region)(GICv3State *s, hwaddr base, uint32_t cou= nt); } ARMGICv3CommonClass; =20 void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler, --=20 2.5.5