From nobody Sun Oct 26 00:02:39 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1521665585989712.6285513474963; Wed, 21 Mar 2018 13:53:05 -0700 (PDT) Received: from localhost ([::1]:57370 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eykjJ-0006Jg-4I for importer@patchew.org; Wed, 21 Mar 2018 16:53:05 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53036) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eykeM-00020s-Cg for qemu-devel@nongnu.org; Wed, 21 Mar 2018 16:47:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eykeK-00024u-Pt for qemu-devel@nongnu.org; Wed, 21 Mar 2018 16:47:58 -0400 Received: from mail-pf0-x244.google.com ([2607:f8b0:400e:c00::244]:35494) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eykeK-00024g-I2 for qemu-devel@nongnu.org; Wed, 21 Mar 2018 16:47:56 -0400 Received: by mail-pf0-x244.google.com with SMTP id y186so2468424pfb.2 for ; Wed, 21 Mar 2018 13:47:56 -0700 (PDT) Received: from monty.com ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id w10sm8244499pgr.57.2018.03.21.13.47.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 21 Mar 2018 13:47:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=padGfaTjE2O1uLxXu2zV1PLt8Xu8ywDzhXT0Yc4WBlY=; b=MKYc/XEd4dEd2mENL05LRE6Rqp3DNw8+OqKOLQREKn+pg6+ddXsmh+EC1HY2OFc7bg 78l5JKQr/XSxCwPhKiIeCL+j/xrMW0izMuJa2vr85o6mXvJ4juKFLaCLqgo/OCjQ/bq8 StRDMv+41wqsbpstXeJs/rGJelEopfkf7LkUZ5L9O4C+zEaas2PjjCp7X7EExMvERF7s n/44DHchf7kazcBzoAufJE0nG3Xh+1TQ+jKYfqi/pkpNHl3bQaaHrauhnECbXUbbK0s4 787NUuT/qymz9tn+cgO18yCL6AjTZEY1LpmzgAJWBY7C26PaHl2clgWWj7/bgiAT566Z NqPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=padGfaTjE2O1uLxXu2zV1PLt8Xu8ywDzhXT0Yc4WBlY=; b=hH/wmvT5FFxSBiins/AlZ/y2BVcvcmOcS7W5wRBbZ9TADEiAdpmUBowByqvV3w6EDh JMCp2hNk6LT/dESOSkWeAgtwvgmWp7ZYB9ae3gCdD8fGEglR2Y4Pi10Cjt7wl7MWPaCM mmjKWXgwBaUyiwn90okJ8ZPjK1OeytFZyAncAN5Tu9nN9xx8Sb6JxiOMBKg57HxZUPo5 +fuQPCKyTVXWOgdW5VGV/83UAV2vY45UZBVeuzPQmAD+Oh19PRIiSzLJh27z2eqsOfMs 1+viWIQMSQdpz3gydYlDLTG5BTfP4RRq3teuqn75yt+oJHXa0gcLC3GbYn9QQ2oJEPNo vt2A== X-Gm-Message-State: AElRT7G7ZcTMr16KsoeYaxdSYrADVPu2khA+gZ9KCRUWyIxQGww9qABh IzvS8trF8ZWp/iSUOtv8grtT1f4lTgc= X-Google-Smtp-Source: AG47ELudTvH/GwBiLm/5XDs0PD9fk/xMX4MU4sXsJMC6r3Rnd6Jirfa1+QX8QbMmxdYK5XZpTGhMzg== X-Received: by 10.101.83.75 with SMTP id w11mr15643211pgr.197.1521665275286; Wed, 21 Mar 2018 13:47:55 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Wed, 21 Mar 2018 13:46:43 -0700 Message-Id: <1521665220-3869-8-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1521665220-3869-1-git-send-email-mjc@sifive.com> References: <1521665220-3869-1-git-send-email-mjc@sifive.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PULL 07/24] RISC-V: Remove unused class definitions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@groups.riscv.org, Michael Clark , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Removes a whole lot of unnecessary boilerplate code. Machines don't need to be objects. The expansion of the SOC object model for the RISC-V machines will happen in the future as SiFive plans to add their FE310 and FU540 SOCs to QEMU. However, it seems that this present boilerplate is complete unnecessary. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/riscv/riscv_hart.c | 6 ------ hw/riscv/sifive_e.c | 25 ------------------------- hw/riscv/sifive_u.c | 25 ------------------------- hw/riscv/spike.c | 20 -------------------- hw/riscv/virt.c | 25 ------------------------- include/hw/riscv/sifive_e.h | 5 ----- include/hw/riscv/sifive_u.h | 5 ----- include/hw/riscv/spike.h | 7 ++++--- include/hw/riscv/virt.h | 5 ----- 9 files changed, 4 insertions(+), 119 deletions(-) diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c index 14e3c18..75ba7ed 100644 --- a/hw/riscv/riscv_hart.c +++ b/hw/riscv/riscv_hart.c @@ -68,16 +68,10 @@ static void riscv_harts_class_init(ObjectClass *klass, = void *data) dc->realize =3D riscv_harts_realize; } =20 -static void riscv_harts_init(Object *obj) -{ - /* RISCVHartArrayState *s =3D SIFIVE_COREPLEX(obj); */ -} - static const TypeInfo riscv_harts_info =3D { .name =3D TYPE_RISCV_HART_ARRAY, .parent =3D TYPE_SYS_BUS_DEVICE, .instance_size =3D sizeof(RISCVHartArrayState), - .instance_init =3D riscv_harts_init, .class_init =3D riscv_harts_class_init, }; =20 diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 09c9d49..4872b68 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -194,24 +194,6 @@ static void riscv_sifive_e_init(MachineState *machine) } } =20 -static int riscv_sifive_e_sysbus_device_init(SysBusDevice *sysbusdev) -{ - return 0; -} - -static void riscv_sifive_e_class_init(ObjectClass *klass, void *data) -{ - SysBusDeviceClass *k =3D SYS_BUS_DEVICE_CLASS(klass); - k->init =3D riscv_sifive_e_sysbus_device_init; -} - -static const TypeInfo riscv_sifive_e_device =3D { - .name =3D TYPE_SIFIVE_E, - .parent =3D TYPE_SYS_BUS_DEVICE, - .instance_size =3D sizeof(SiFiveEState), - .class_init =3D riscv_sifive_e_class_init, -}; - static void riscv_sifive_e_machine_init(MachineClass *mc) { mc->desc =3D "RISC-V Board compatible with SiFive E SDK"; @@ -220,10 +202,3 @@ static void riscv_sifive_e_machine_init(MachineClass *= mc) } =20 DEFINE_MACHINE("sifive_e", riscv_sifive_e_machine_init) - -static void riscv_sifive_e_register_types(void) -{ - type_register_static(&riscv_sifive_e_device); -} - -type_init(riscv_sifive_e_register_types); diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 25df16c..083043a 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -302,31 +302,6 @@ static void riscv_sifive_u_init(MachineState *machine) SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE); } =20 -static int riscv_sifive_u_sysbus_device_init(SysBusDevice *sysbusdev) -{ - return 0; -} - -static void riscv_sifive_u_class_init(ObjectClass *klass, void *data) -{ - SysBusDeviceClass *k =3D SYS_BUS_DEVICE_CLASS(klass); - k->init =3D riscv_sifive_u_sysbus_device_init; -} - -static const TypeInfo riscv_sifive_u_device =3D { - .name =3D TYPE_SIFIVE_U, - .parent =3D TYPE_SYS_BUS_DEVICE, - .instance_size =3D sizeof(SiFiveUState), - .class_init =3D riscv_sifive_u_class_init, -}; - -static void riscv_sifive_u_register_types(void) -{ - type_register_static(&riscv_sifive_u_device); -} - -type_init(riscv_sifive_u_register_types); - static void riscv_sifive_u_machine_init(MachineClass *mc) { mc->desc =3D "RISC-V Board compatible with SiFive U SDK"; diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 74edf33..64e585e 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -336,18 +336,6 @@ static void spike_v1_09_1_board_init(MachineState *mac= hine) smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE); } =20 -static const TypeInfo spike_v_1_09_1_device =3D { - .name =3D TYPE_RISCV_SPIKE_V1_09_1_BOARD, - .parent =3D TYPE_SYS_BUS_DEVICE, - .instance_size =3D sizeof(SpikeState), -}; - -static const TypeInfo spike_v_1_10_0_device =3D { - .name =3D TYPE_RISCV_SPIKE_V1_10_0_BOARD, - .parent =3D TYPE_SYS_BUS_DEVICE, - .instance_size =3D sizeof(SpikeState), -}; - static void spike_v1_09_1_machine_init(MachineClass *mc) { mc->desc =3D "RISC-V Spike Board (Privileged ISA v1.9.1)"; @@ -365,11 +353,3 @@ static void spike_v1_10_0_machine_init(MachineClass *m= c) =20 DEFINE_MACHINE("spike_v1.9.1", spike_v1_09_1_machine_init) DEFINE_MACHINE("spike_v1.10", spike_v1_10_0_machine_init) - -static void riscv_spike_board_register_types(void) -{ - type_register_static(&spike_v_1_09_1_device); - type_register_static(&spike_v_1_10_0_device); -} - -type_init(riscv_spike_board_register_types); diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index f1e3641..5913100 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -380,24 +380,6 @@ static void riscv_virt_board_init(MachineState *machin= e) serial_hds[0], DEVICE_LITTLE_ENDIAN); } =20 -static int riscv_virt_board_sysbus_device_init(SysBusDevice *sysbusdev) -{ - return 0; -} - -static void riscv_virt_board_class_init(ObjectClass *klass, void *data) -{ - SysBusDeviceClass *k =3D SYS_BUS_DEVICE_CLASS(klass); - k->init =3D riscv_virt_board_sysbus_device_init; -} - -static const TypeInfo riscv_virt_board_device =3D { - .name =3D TYPE_RISCV_VIRT_BOARD, - .parent =3D TYPE_SYS_BUS_DEVICE, - .instance_size =3D sizeof(RISCVVirtState), - .class_init =3D riscv_virt_board_class_init, -}; - static void riscv_virt_board_machine_init(MachineClass *mc) { mc->desc =3D "RISC-V VirtIO Board (Privileged ISA v1.10)"; @@ -406,10 +388,3 @@ static void riscv_virt_board_machine_init(MachineClass= *mc) } =20 DEFINE_MACHINE("virt", riscv_virt_board_machine_init) - -static void riscv_virt_board_register_types(void) -{ - type_register_static(&riscv_virt_board_device); -} - -type_init(riscv_virt_board_register_types); diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h index 0aebc57..12ad6d2 100644 --- a/include/hw/riscv/sifive_e.h +++ b/include/hw/riscv/sifive_e.h @@ -19,11 +19,6 @@ #ifndef HW_SIFIVE_E_H #define HW_SIFIVE_E_H =20 -#define TYPE_SIFIVE_E "riscv.sifive_e" - -#define SIFIVE_E(obj) \ - OBJECT_CHECK(SiFiveEState, (obj), TYPE_SIFIVE_E) - typedef struct SiFiveEState { /*< private >*/ SysBusDevice parent_obj; diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index be38aa0..94a3905 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -19,11 +19,6 @@ #ifndef HW_SIFIVE_U_H #define HW_SIFIVE_U_H =20 -#define TYPE_SIFIVE_U "riscv.sifive_u" - -#define SIFIVE_U(obj) \ - OBJECT_CHECK(SiFiveUState, (obj), TYPE_SIFIVE_U) - typedef struct SiFiveUState { /*< private >*/ SysBusDevice parent_obj; diff --git a/include/hw/riscv/spike.h b/include/hw/riscv/spike.h index 179b6cf..8410430 100644 --- a/include/hw/riscv/spike.h +++ b/include/hw/riscv/spike.h @@ -19,10 +19,11 @@ #ifndef HW_SPIKE_H #define HW_SPIKE_H =20 -#define TYPE_RISCV_SPIKE_V1_09_1_BOARD "riscv.spike_v1_9_1" -#define TYPE_RISCV_SPIKE_V1_10_0_BOARD "riscv.spike_v1_10" - typedef struct { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ RISCVHartArrayState soc; void *fdt; int fdt_size; diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index 655e85d..b91a412 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -19,10 +19,6 @@ #ifndef HW_VIRT_H #define HW_VIRT_H =20 -#define TYPE_RISCV_VIRT_BOARD "riscv.virt" -#define VIRT(obj) \ - OBJECT_CHECK(RISCVVirtState, (obj), TYPE_RISCV_VIRT_BOARD) - typedef struct { /*< private >*/ SysBusDevice parent_obj; @@ -45,7 +41,6 @@ enum { VIRT_DRAM }; =20 - enum { UART0_IRQ =3D 10, VIRTIO_IRQ =3D 1, /* 1 to 8 */ --=20 2.7.0