From nobody Sun Oct 26 00:02:41 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1521665925252817.2207193797445; Wed, 21 Mar 2018 13:58:45 -0700 (PDT) Received: from localhost ([::1]:57402 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eykol-0003QP-ML for importer@patchew.org; Wed, 21 Mar 2018 16:58:44 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53028) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eykeL-00020m-E3 for qemu-devel@nongnu.org; Wed, 21 Mar 2018 16:47:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eykeJ-00024c-Qt for qemu-devel@nongnu.org; Wed, 21 Mar 2018 16:47:57 -0400 Received: from mail-pg0-x243.google.com ([2607:f8b0:400e:c05::243]:44140) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eykeJ-00024D-JZ for qemu-devel@nongnu.org; Wed, 21 Mar 2018 16:47:55 -0400 Received: by mail-pg0-x243.google.com with SMTP id l4so2399542pgp.11 for ; Wed, 21 Mar 2018 13:47:55 -0700 (PDT) Received: from monty.com ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id w10sm8244499pgr.57.2018.03.21.13.47.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 21 Mar 2018 13:47:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=KXs31ZQPDLR7Vw784vZDJ7FehxZMGqH0wnzWcDgDVRA=; b=ltL1lpuX5006IKYk2V81kkYOU8RBkI0jqO+qg/5Cr89LGbM3UBz+G7FksrQMAEno5n 2O1+/342hii1G72uu+fIEOg9aQPe1ESSqocayLm98lfXAdfeisdDdQ4F5quZuJN7zCUG HGdwPZSFOJU9wt+RSt3out2hEUjTEVYBo4QNr8CW43g96EUHDSlA+25XcCO2sXRUU2iq jplyt0qnk63ia3fdPNmF+8CK1K4zgkAiSiVN5DjR3EjPPuzpnEtFAPJ+3K5Cxrh8DJ5t pCOK8Pnwgjkv788X0sq+jVF6yG1Xcj2hobMQDHBDCG4oDwjblAVyTLWPj0qazHHrBa1T Vz/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=KXs31ZQPDLR7Vw784vZDJ7FehxZMGqH0wnzWcDgDVRA=; b=tj7gkqQVtKUjYP14cT16cU3hrkDEKh1qb82SF/aI11FGR0aqjaBS4HxzjIaFI8FV4G +u9bE5iqAb4eq9u5KiqnXfDoYrcp3UWm5zzvTdOpsEEQZ710sqwO5pO+C73/o3Y+pcHt QFvc43Cmkkv86nswYrj6Ss4Dk/FZ1zo8kE2fC/ioia0jK9J3/mkH7qvJ6dFs9k0mp0An eca92ODaP1z8L5CPXEXA/tJpys+gTIBK3JZHZhMAIZPnKttiRyG2toJVfqDZ2jBxznpi B3R02YwY8jaFzOahRKhlQ2CdjjHYi8n/kqlTbk6tZGu4asc7WZtouy9jR2U3ZkPZGnoZ 83OA== X-Gm-Message-State: AElRT7Ek/8iI08gcyFF73Zrx9bfGr0k7L6AnCGL+66KhPa5qvFz/HecX ES0k4C0zFYyNd1V8CwezNTSYm79iZ7E= X-Google-Smtp-Source: AG47ELuussUv9DXfP/CzXfGP3AKoC478HLQNBasF8rOLsLIkeJVfyQIVPSg0vUExpKD8zugq1b0KrQ== X-Received: by 10.99.128.67 with SMTP id j64mr15589533pgd.55.1521665274375; Wed, 21 Mar 2018 13:47:54 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Wed, 21 Mar 2018 13:46:42 -0700 Message-Id: <1521665220-3869-7-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1521665220-3869-1-git-send-email-mjc@sifive.com> References: <1521665220-3869-1-git-send-email-mjc@sifive.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PULL 06/24] RISC-V: Mark ROM read-only after copying in code X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@groups.riscv.org, Michael Clark , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The sifive_u machine already marks its ROM readonly. This fixes the remaining boards. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt --- hw/riscv/sifive_u.c | 9 +++++---- hw/riscv/spike.c | 18 ++++++++++-------- hw/riscv/virt.c | 7 ++++--- include/hw/riscv/spike.h | 8 -------- 4 files changed, 19 insertions(+), 23 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 6116c38..25df16c 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -223,7 +223,7 @@ static void riscv_sifive_u_init(MachineState *machine) SiFiveUState *s =3D g_new0(SiFiveUState, 1); MemoryRegion *sys_memory =3D get_system_memory(); MemoryRegion *main_mem =3D g_new(MemoryRegion, 1); - MemoryRegion *boot_rom =3D g_new(MemoryRegion, 1); + MemoryRegion *mask_rom =3D g_new(MemoryRegion, 1); =20 /* Initialize SOC */ object_initialize(&s->soc, sizeof(s->soc), TYPE_RISCV_HART_ARRAY); @@ -246,10 +246,10 @@ static void riscv_sifive_u_init(MachineState *machine) create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); =20 /* boot rom */ - memory_region_init_ram(boot_rom, NULL, "riscv.sifive.u.mrom", + memory_region_init_ram(mask_rom, NULL, "riscv.sifive.u.mrom", memmap[SIFIVE_U_MROM].base, &error_fatal); - memory_region_set_readonly(boot_rom, true); - memory_region_add_subregion(sys_memory, 0x0, boot_rom); + memory_region_set_readonly(mask_rom, true); + memory_region_add_subregion(sys_memory, 0x0, mask_rom); =20 if (machine->kernel_filename) { load_kernel(machine->kernel_filename); @@ -279,6 +279,7 @@ static void riscv_sifive_u_init(MachineState *machine) qemu_fdt_dumpdtb(s->fdt, s->fdt_size); cpu_physical_memory_write(memmap[SIFIVE_U_MROM].base + sizeof(reset_vec), s->fdt, s->fdt_size); + memory_region_set_readonly(mask_rom, true); =20 /* MMIO */ s->plic =3D sifive_plic_create(memmap[SIFIVE_U_PLIC].base, diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 7710333..74edf33 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -173,7 +173,7 @@ static void spike_v1_10_0_board_init(MachineState *mach= ine) SpikeState *s =3D g_new0(SpikeState, 1); MemoryRegion *system_memory =3D get_system_memory(); MemoryRegion *main_mem =3D g_new(MemoryRegion, 1); - MemoryRegion *boot_rom =3D g_new(MemoryRegion, 1); + MemoryRegion *mask_rom =3D g_new(MemoryRegion, 1); =20 /* Initialize SOC */ object_initialize(&s->soc, sizeof(s->soc), TYPE_RISCV_HART_ARRAY); @@ -196,9 +196,9 @@ static void spike_v1_10_0_board_init(MachineState *mach= ine) create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); =20 /* boot rom */ - memory_region_init_ram(boot_rom, NULL, "riscv.spike.bootrom", + memory_region_init_ram(mask_rom, NULL, "riscv.spike.mrom", s->fdt_size + 0x2000, &error_fatal); - memory_region_add_subregion(system_memory, 0x0, boot_rom); + memory_region_add_subregion(system_memory, 0x0, mask_rom); =20 if (machine->kernel_filename) { load_kernel(machine->kernel_filename); @@ -228,9 +228,10 @@ static void spike_v1_10_0_board_init(MachineState *mac= hine) qemu_fdt_dumpdtb(s->fdt, s->fdt_size); cpu_physical_memory_write(memmap[SPIKE_MROM].base + sizeof(reset_vec), s->fdt, s->fdt_size); + memory_region_set_readonly(mask_rom, true); =20 /* initialize HTIF using symbols found in load_kernel */ - htif_mm_init(system_memory, boot_rom, &s->soc.harts[0].env, serial_hds= [0]); + htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hds= [0]); =20 /* Core Local Interruptor (timer and IPI) */ sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size, @@ -244,7 +245,7 @@ static void spike_v1_09_1_board_init(MachineState *mach= ine) SpikeState *s =3D g_new0(SpikeState, 1); MemoryRegion *system_memory =3D get_system_memory(); MemoryRegion *main_mem =3D g_new(MemoryRegion, 1); - MemoryRegion *boot_rom =3D g_new(MemoryRegion, 1); + MemoryRegion *mask_rom =3D g_new(MemoryRegion, 1); =20 /* Initialize SOC */ object_initialize(&s->soc, sizeof(s->soc), TYPE_RISCV_HART_ARRAY); @@ -264,9 +265,9 @@ static void spike_v1_09_1_board_init(MachineState *mach= ine) main_mem); =20 /* boot rom */ - memory_region_init_ram(boot_rom, NULL, "riscv.spike.bootrom", + memory_region_init_ram(mask_rom, NULL, "riscv.spike.mrom", 0x40000, &error_fatal); - memory_region_add_subregion(system_memory, 0x0, boot_rom); + memory_region_add_subregion(system_memory, 0x0, mask_rom); =20 if (machine->kernel_filename) { load_kernel(machine->kernel_filename); @@ -325,9 +326,10 @@ static void spike_v1_09_1_board_init(MachineState *mac= hine) /* copy in the config string */ cpu_physical_memory_write(memmap[SPIKE_MROM].base + sizeof(reset_vec), config_string, config_string_len); + memory_region_set_readonly(mask_rom, true); =20 /* initialize HTIF using symbols found in load_kernel */ - htif_mm_init(system_memory, boot_rom, &s->soc.harts[0].env, serial_hds= [0]); + htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hds= [0]); =20 /* Core Local Interruptor (timer and IPI) */ sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size, diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index f8c19b4..f1e3641 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -270,7 +270,7 @@ static void riscv_virt_board_init(MachineState *machine) RISCVVirtState *s =3D g_new0(RISCVVirtState, 1); MemoryRegion *system_memory =3D get_system_memory(); MemoryRegion *main_mem =3D g_new(MemoryRegion, 1); - MemoryRegion *boot_rom =3D g_new(MemoryRegion, 1); + MemoryRegion *mask_rom =3D g_new(MemoryRegion, 1); char *plic_hart_config; size_t plic_hart_config_len; int i; @@ -296,9 +296,9 @@ static void riscv_virt_board_init(MachineState *machine) create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); =20 /* boot rom */ - memory_region_init_ram(boot_rom, NULL, "riscv_virt_board.bootrom", + memory_region_init_ram(mask_rom, NULL, "riscv_virt_board.mrom", s->fdt_size + 0x2000, &error_fatal); - memory_region_add_subregion(system_memory, 0x0, boot_rom); + memory_region_add_subregion(system_memory, 0x0, mask_rom); =20 if (machine->kernel_filename) { uint64_t kernel_entry =3D load_kernel(machine->kernel_filename); @@ -339,6 +339,7 @@ static void riscv_virt_board_init(MachineState *machine) qemu_fdt_dumpdtb(s->fdt, s->fdt_size); cpu_physical_memory_write(memmap[VIRT_MROM].base + sizeof(reset_vec), s->fdt, s->fdt_size); + memory_region_set_readonly(mask_rom, true); =20 /* create PLIC hart topology configuration string */ plic_hart_config_len =3D (strlen(VIRT_PLIC_HART_CONFIG) + 1) * smp_cpu= s; diff --git a/include/hw/riscv/spike.h b/include/hw/riscv/spike.h index d85a64e..179b6cf 100644 --- a/include/hw/riscv/spike.h +++ b/include/hw/riscv/spike.h @@ -22,20 +22,12 @@ #define TYPE_RISCV_SPIKE_V1_09_1_BOARD "riscv.spike_v1_9_1" #define TYPE_RISCV_SPIKE_V1_10_0_BOARD "riscv.spike_v1_10" =20 -#define SPIKE(obj) \ - OBJECT_CHECK(SpikeState, (obj), TYPE_RISCV_SPIKE_BOARD) - typedef struct { - /*< private >*/ - SysBusDevice parent_obj; - - /*< public >*/ RISCVHartArrayState soc; void *fdt; int fdt_size; } SpikeState; =20 - enum { SPIKE_MROM, SPIKE_CLINT, --=20 2.7.0