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X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PULL 22/24] RISC-V: Convert cpu definition towards future model X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Bastian Koppelmann , Palmer Dabbelt , Michael Clark , Igor Mammedov , patches@groups.riscv.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 - Model borrowed from target/sh4/cpu.c - Rewrote riscv_cpu_list to use object_class_get_list - Dropped 'struct RISCVCPUInfo' and used TypeInfo array - Replaced riscv_cpu_register_types with DEFINE_TYPES - Marked base class as abstract Cc: Igor Mammedov Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Palmer Dabbelt Signed-off-by: Michael Clark Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Igor Mammedov --- target/riscv/cpu.c | 123 ++++++++++++++++++++++++++++++-------------------= ---- 1 file changed, 69 insertions(+), 54 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ad65b39..4e5a56d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -115,6 +115,8 @@ static void riscv_any_cpu_init(Object *obj) set_resetvec(env, DEFAULT_RSTVEC); } =20 +#if defined(TARGET_RISCV32) + static void rv32gcsu_priv1_09_1_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; @@ -141,6 +143,8 @@ static void rv32imacu_nommu_cpu_init(Object *obj) set_resetvec(env, DEFAULT_RSTVEC); } =20 +#elif defined(TARGET_RISCV64) + static void rv64gcsu_priv1_09_1_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; @@ -167,20 +171,7 @@ static void rv64imacu_nommu_cpu_init(Object *obj) set_resetvec(env, DEFAULT_RSTVEC); } =20 -static const RISCVCPUInfo riscv_cpus[] =3D { - { 96, TYPE_RISCV_CPU_ANY, riscv_any_cpu_init }, - { 32, TYPE_RISCV_CPU_RV32GCSU_V1_09_1, rv32gcsu_priv1_09_1_cpu_init }, - { 32, TYPE_RISCV_CPU_RV32GCSU_V1_10_0, rv32gcsu_priv1_10_0_cpu_init }, - { 32, TYPE_RISCV_CPU_RV32IMACU_NOMMU, rv32imacu_nommu_cpu_init }, - { 32, TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init }, - { 32, TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_init }, - { 64, TYPE_RISCV_CPU_RV64GCSU_V1_09_1, rv64gcsu_priv1_09_1_cpu_init }, - { 64, TYPE_RISCV_CPU_RV64GCSU_V1_10_0, rv64gcsu_priv1_10_0_cpu_init }, - { 64, TYPE_RISCV_CPU_RV64IMACU_NOMMU, rv64imacu_nommu_cpu_init }, - { 64, TYPE_RISCV_CPU_SIFIVE_E51, rv64imacu_nommu_cpu_init }, - { 64, TYPE_RISCV_CPU_SIFIVE_U54, rv64gcsu_priv1_10_0_cpu_init }, - { 0, NULL, NULL } -}; +#endif =20 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) { @@ -366,28 +357,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void = *data) cc->vmsd =3D &vmstate_riscv_cpu; } =20 -static void cpu_register(const RISCVCPUInfo *info) -{ - TypeInfo type_info =3D { - .name =3D info->name, - .parent =3D TYPE_RISCV_CPU, - .instance_size =3D sizeof(RISCVCPU), - .instance_init =3D info->initfn, - }; - - type_register(&type_info); -} - -static const TypeInfo riscv_cpu_type_info =3D { - .name =3D TYPE_RISCV_CPU, - .parent =3D TYPE_CPU, - .instance_size =3D sizeof(RISCVCPU), - .instance_init =3D riscv_cpu_init, - .abstract =3D false, - .class_size =3D sizeof(RISCVCPUClass), - .class_init =3D riscv_cpu_class_init, -}; - char *riscv_isa_string(RISCVCPU *cpu) { int i; @@ -403,30 +372,76 @@ char *riscv_isa_string(RISCVCPU *cpu) return isa_str; } =20 -void riscv_cpu_list(FILE *f, fprintf_function cpu_fprintf) +typedef struct RISCVCPUListState { + fprintf_function cpu_fprintf; + FILE *file; +} RISCVCPUListState; + +static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b) { - const RISCVCPUInfo *info =3D riscv_cpus; + ObjectClass *class_a =3D (ObjectClass *)a; + ObjectClass *class_b =3D (ObjectClass *)b; + const char *name_a, *name_b; =20 - while (info->name) { - if (info->bit_widths & TARGET_LONG_BITS) { - (*cpu_fprintf)(f, "%s\n", info->name); - } - info++; - } + name_a =3D object_class_get_name(class_a); + name_b =3D object_class_get_name(class_b); + return strcmp(name_a, name_b); } =20 -static void riscv_cpu_register_types(void) +static void riscv_cpu_list_entry(gpointer data, gpointer user_data) { - const RISCVCPUInfo *info =3D riscv_cpus; + RISCVCPUListState *s =3D user_data; + const char *typename =3D object_class_get_name(OBJECT_CLASS(data)); + int len =3D strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX); =20 - type_register_static(&riscv_cpu_type_info); + (*s->cpu_fprintf)(s->file, "%.*s\n", len, typename); +} =20 - while (info->name) { - if (info->bit_widths & TARGET_LONG_BITS) { - cpu_register(info); - } - info++; - } +void riscv_cpu_list(FILE *f, fprintf_function cpu_fprintf) +{ + RISCVCPUListState s =3D { + .cpu_fprintf =3D cpu_fprintf, + .file =3D f, + }; + GSList *list; + + list =3D object_class_get_list(TYPE_RISCV_CPU, false); + list =3D g_slist_sort(list, riscv_cpu_list_compare); + g_slist_foreach(list, riscv_cpu_list_entry, &s); + g_slist_free(list); } =20 -type_init(riscv_cpu_register_types) +#define DEFINE_CPU(type_name, initfn) \ + { \ + .name =3D type_name, \ + .parent =3D TYPE_RISCV_CPU, \ + .instance_init =3D initfn \ + } + +static const TypeInfo riscv_cpu_type_infos[] =3D { + { + .name =3D TYPE_RISCV_CPU, + .parent =3D TYPE_CPU, + .instance_size =3D sizeof(RISCVCPU), + .instance_init =3D riscv_cpu_init, + .abstract =3D true, + .class_size =3D sizeof(RISCVCPUClass), + .class_init =3D riscv_cpu_class_init, + }, + DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), +#if defined(TARGET_RISCV32) + DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_09_1, rv32gcsu_priv1_09_1_cpu_in= it), + DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_10_0, rv32gcsu_priv1_10_0_cpu_in= it), + DEFINE_CPU(TYPE_RISCV_CPU_RV32IMACU_NOMMU, rv32imacu_nommu_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_in= it) +#elif defined(TARGET_RISCV64) + DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_09_1, rv64gcsu_priv1_09_1_cpu_in= it), + DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_10_0, rv64gcsu_priv1_10_0_cpu_in= it), + DEFINE_CPU(TYPE_RISCV_CPU_RV64IMACU_NOMMU, rv64imacu_nommu_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64imacu_nommu_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64gcsu_priv1_10_0_cpu_in= it) +#endif +}; + +DEFINE_TYPES(riscv_cpu_type_infos) --=20 2.7.0