From nobody Sat Oct 25 02:28:14 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1521531018175624.559689411478; Tue, 20 Mar 2018 00:30:18 -0700 (PDT) Received: from localhost ([::1]:46623 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eyBil-0002R0-UT for importer@patchew.org; Tue, 20 Mar 2018 03:30:11 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47882) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eyBgW-0001Bs-Ea for qemu-devel@nongnu.org; Tue, 20 Mar 2018 03:27:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eyBgV-00006X-IO for qemu-devel@nongnu.org; Tue, 20 Mar 2018 03:27:52 -0400 Received: from [45.249.212.35] (port=43375 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eyBgQ-0008PZ-7q; Tue, 20 Mar 2018 03:27:46 -0400 Received: from DGGEMS414-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 4446877A7E910; Tue, 20 Mar 2018 15:27:41 +0800 (CST) Received: from HGHY1Z002260041.china.huawei.com (10.177.16.142) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.361.1; Tue, 20 Mar 2018 15:27:35 +0800 From: Shannon Zhao To: Date: Tue, 20 Mar 2018 15:26:48 +0800 Message-ID: <1521530809-11780-2-git-send-email-zhaoshenglong@huawei.com> X-Mailer: git-send-email 1.9.0.msysgit.0 In-Reply-To: <1521530809-11780-1-git-send-email-zhaoshenglong@huawei.com> References: <1521530809-11780-1-git-send-email-zhaoshenglong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.16.142] X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 45.249.212.35 Subject: [Qemu-devel] [PATCH v2 1/2] arm_gicv3_kvm: increase clroffset accordingly X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-devel@nongnu.org, eric.auger@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" It forgot to increase clroffset during the loop. So it only clear the first 4 bytes. Signed-off-by: Shannon Zhao Reviewed-by: Eric Auger --- hw/intc/arm_gicv3_kvm.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c index ec37177..3536795 100644 --- a/hw/intc/arm_gicv3_kvm.c +++ b/hw/intc/arm_gicv3_kvm.c @@ -243,6 +243,7 @@ static void kvm_dist_putbmp(GICv3State *s, uint32_t off= set, if (clroffset !=3D 0) { reg =3D 0; kvm_gicd_access(s, clroffset, ®, true); + clroffset +=3D 4; } reg =3D *gic_bmp_ptr32(bmp, irq); kvm_gicd_access(s, offset, ®, true); --=20 2.0.4 From nobody Sat Oct 25 02:28:14 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1521531097582200.19068560019457; Tue, 20 Mar 2018 00:31:37 -0700 (PDT) Received: from localhost ([::1]:46631 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eyBk5-0003Bj-2V for importer@patchew.org; Tue, 20 Mar 2018 03:31:33 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47899) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eyBgX-0001CZ-HZ for qemu-devel@nongnu.org; Tue, 20 Mar 2018 03:27:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eyBgW-00007h-CV for qemu-devel@nongnu.org; Tue, 20 Mar 2018 03:27:53 -0400 Received: from [45.249.212.35] (port=43374 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eyBgQ-0008Pa-9H; Tue, 20 Mar 2018 03:27:46 -0400 Received: from DGGEMS414-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 52051C37BED46; Tue, 20 Mar 2018 15:27:41 +0800 (CST) Received: from HGHY1Z002260041.china.huawei.com (10.177.16.142) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.361.1; Tue, 20 Mar 2018 15:27:36 +0800 From: Shannon Zhao To: Date: Tue, 20 Mar 2018 15:26:49 +0800 Message-ID: <1521530809-11780-3-git-send-email-zhaoshenglong@huawei.com> X-Mailer: git-send-email 1.9.0.msysgit.0 In-Reply-To: <1521530809-11780-1-git-send-email-zhaoshenglong@huawei.com> References: <1521530809-11780-1-git-send-email-zhaoshenglong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.16.142] X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 45.249.212.35 Subject: [Qemu-devel] [PATCH v2 2/2] arm_gicv3_kvm: kvm_dist_get/put: skip the registers banked by GICR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-devel@nongnu.org, eric.auger@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" While we skip the GIC_INTERNAL irqs, we don't change the register offset accordingly. This will overlap the GICR registers value and leave the last GIC_INTERNAL irq's registers out of update. Fix this by skipping the registers banked by GICR. Signed-off-by: Shannon Zhao --- hw/intc/arm_gicv3_kvm.c | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c index 3536795..d423cba 100644 --- a/hw/intc/arm_gicv3_kvm.c +++ b/hw/intc/arm_gicv3_kvm.c @@ -136,6 +136,12 @@ static void kvm_dist_get_priority(GICv3State *s, uint3= 2_t offset, uint8_t *bmp) int irq; =20 field =3D (uint32_t *)bmp; + /* For the KVM GICv3, affinity routing is always enabled, and the firs= t 8 + * GICD_IPRIORITYR registers are always RAZ/WI. The corresponding + * functionality is replaced by GICR_IPRIORITYR. So it doesn't need= to + * sync them. + */ + offset +=3D (8 * sizeof(uint32_t)); for_each_dist_irq_reg(irq, s->num_irq, 8) { kvm_gicd_access(s, offset, ®, false); *field =3D reg; @@ -150,6 +156,12 @@ static void kvm_dist_put_priority(GICv3State *s, uint3= 2_t offset, uint8_t *bmp) int irq; =20 field =3D (uint32_t *)bmp; + /* For the KVM GICv3, affinity routing is always enabled, and the firs= t 8 + * GICD_IPRIORITYR registers are always RAZ/WI. The corresponding + * functionality is replaced by GICR_IPRIORITYR. So it doesn't need= to + * sync them. + */ + offset +=3D (8 * sizeof(uint32_t)); for_each_dist_irq_reg(irq, s->num_irq, 8) { reg =3D *field; kvm_gicd_access(s, offset, ®, true); @@ -164,6 +176,12 @@ static void kvm_dist_get_edge_trigger(GICv3State *s, u= int32_t offset, uint32_t reg; int irq; =20 + /* For the KVM GICv3, affinity routing is always enabled, and the firs= t 2 + * GICD_ICFGR registers are always RAZ/WI. The corresponding + * functionality is replaced by GICR_ICFGR. So it doesn't need to s= ync + * them. + */ + offset +=3D (2 * sizeof(uint32_t)); for_each_dist_irq_reg(irq, s->num_irq, 2) { kvm_gicd_access(s, offset, ®, false); reg =3D half_unshuffle32(reg >> 1); @@ -181,6 +199,12 @@ static void kvm_dist_put_edge_trigger(GICv3State *s, u= int32_t offset, uint32_t reg; int irq; =20 + /* For the KVM GICv3, affinity routing is always enabled, and the firs= t 2 + * GICD_ICFGR registers are always RAZ/WI. The corresponding + * functionality is replaced by GICR_ICFGR. So it doesn't need to s= ync + * them. + */ + offset +=3D (2 * sizeof(uint32_t)); for_each_dist_irq_reg(irq, s->num_irq, 2) { reg =3D *gic_bmp_ptr32(bmp, irq); if (irq % 32 !=3D 0) { @@ -222,6 +246,12 @@ static void kvm_dist_getbmp(GICv3State *s, uint32_t of= fset, uint32_t *bmp) uint32_t reg; int irq; =20 + /* For the KVM GICv3, affinity routing is always enabled, and the + * GICD_IGROUPR0/GICD_ISENABLER0/GICD_ISPENDR0/GICD_ISACTIVER0 registe= rs + * are always RAZ/WI. The corresponding functionality is replaced by t= he + * GICR registers. So it doesn't need to sync them. + */ + offset +=3D (1 * sizeof(uint32_t)); for_each_dist_irq_reg(irq, s->num_irq, 1) { kvm_gicd_access(s, offset, ®, false); *gic_bmp_ptr32(bmp, irq) =3D reg; @@ -235,6 +265,14 @@ static void kvm_dist_putbmp(GICv3State *s, uint32_t of= fset, uint32_t reg; int irq; =20 + /* For the KVM GICv3, affinity routing is always enabled, and the + * GICD_IGROUPR0/GICD_ISENABLER0/GICD_ISPENDR0/GICD_ISACTIVER0 registe= rs + * are always RAZ/WI. The corresponding functionality is replaced by t= he + * GICR registers. So it doesn't need to sync them. + */ + offset +=3D (1 * sizeof(uint32_t)); + if (clroffset !=3D 0) + clroffset +=3D (1 * sizeof(uint32_t)); for_each_dist_irq_reg(irq, s->num_irq, 1) { /* If this bitmap is a set/clear register pair, first write to the * clear-reg to clear all bits before using the set-reg to write --=20 2.0.4