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X-Received-From: 2607:f8b0:400e:c01::243 Subject: [Qemu-devel] [PATCH v4 01/26] RISC-V: Make virt create_fdt interface consistent X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@groups.riscv.org, Michael Clark , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 create_fdt sets the fdt variable on RISCVVirtState and this is used to access the fdt. This reverts a change introduced in https://github.com/riscv/riscv-qemu/pull/109 which introduced a redundant return value, overlooking the RISCVVirtState structure member that made create_fdt inconsistent with the other RISC-V machines. The other alternative is to change the other boards to return the fdt. Note: the RISCVVirtState also contains fdt_size. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/riscv/virt.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index e2c214e..37968d2 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -108,7 +108,7 @@ static hwaddr load_initrd(const char *filename, uint64_= t mem_size, return *start + size; } =20 -static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memma= p, +static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, uint64_t mem_size, const char *cmdline) { void *fdt; @@ -264,8 +264,6 @@ static void *create_fdt(RISCVVirtState *s, const struct= MemmapEntry *memmap, qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename); qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); g_free(nodename); - - return fdt; } =20 static void riscv_virt_board_init(MachineState *machine) @@ -279,7 +277,6 @@ static void riscv_virt_board_init(MachineState *machine) char *plic_hart_config; size_t plic_hart_config_len; int i; - void *fdt; =20 /* Initialize SOC */ object_initialize(&s->soc, sizeof(s->soc), TYPE_RISCV_HART_ARRAY); @@ -299,7 +296,7 @@ static void riscv_virt_board_init(MachineState *machine) main_mem); =20 /* create device tree */ - fdt =3D create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdli= ne); + create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); =20 /* boot rom */ memory_region_init_ram(boot_rom, NULL, "riscv_virt_board.bootrom", @@ -314,9 +311,9 @@ static void riscv_virt_board_init(MachineState *machine) hwaddr end =3D load_initrd(machine->initrd_filename, machine->ram_size, kernel_entry, &start); - qemu_fdt_setprop_cell(fdt, "/chosen", - "linux,initrd-start", start); - qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", + qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-start", + start); + qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end", end); } } --=20 2.7.0 From nobody Sun Feb 8 16:34:30 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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X-Received-From: 2607:f8b0:400e:c01::244 Subject: [Qemu-devel] [PATCH v4 02/26] RISC-V: Replace hardcoded constants with enum values X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@groups.riscv.org, Michael Clark , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 The RISC-V device-tree code has a number of hard-coded constants and this change moves them into header enums. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/riscv/sifive_clint.c | 9 +++------ hw/riscv/sifive_u.c | 6 ++++-- hw/riscv/spike.c | 6 ++++-- hw/riscv/virt.c | 6 ++++-- include/hw/riscv/sifive_clint.h | 4 ++++ include/hw/riscv/sifive_u.h | 4 ++++ include/hw/riscv/spike.h | 4 ++++ include/hw/riscv/virt.h | 4 ++++ 8 files changed, 31 insertions(+), 12 deletions(-) diff --git a/hw/riscv/sifive_clint.c b/hw/riscv/sifive_clint.c index 4893453..7cc606e 100644 --- a/hw/riscv/sifive_clint.c +++ b/hw/riscv/sifive_clint.c @@ -26,13 +26,10 @@ #include "hw/riscv/sifive_clint.h" #include "qemu/timer.h" =20 -/* See: riscv-pk/machine/sbi_entry.S and arch/riscv/kernel/time.c */ -#define TIMER_FREQ (10 * 1000 * 1000) - static uint64_t cpu_riscv_read_rtc(void) { - return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), TIMER_FREQ, - NANOSECONDS_PER_SECOND); + return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), + SIFIVE_CLINT_TIMEBASE_FREQ, NANOSECONDS_PER_SECOND); } =20 /* @@ -59,7 +56,7 @@ static void sifive_clint_write_timecmp(RISCVCPU *cpu, uin= t64_t value) diff =3D cpu->env.timecmp - rtc_r; /* back to ns (note args switched in muldiv64) */ next =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + - muldiv64(diff, NANOSECONDS_PER_SECOND, TIMER_FREQ); + muldiv64(diff, NANOSECONDS_PER_SECOND, SIFIVE_CLINT_TIMEBASE_FREQ); timer_mod(cpu->env.timer, next); } =20 diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 1c2deef..f3f7615 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -122,7 +122,8 @@ static void create_fdt(SiFiveUState *s, const struct Me= mmapEntry *memmap, g_free(nodename); =20 qemu_fdt_add_subnode(fdt, "/cpus"); - qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", 10000000); + qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", + SIFIVE_CLINT_TIMEBASE_FREQ); qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); =20 @@ -131,7 +132,8 @@ static void create_fdt(SiFiveUState *s, const struct Me= mmapEntry *memmap, char *intc =3D g_strdup_printf("/cpus/cpu@%d/interrupt-controller"= , cpu); char *isa =3D riscv_isa_string(&s->soc.harts[cpu]); qemu_fdt_add_subnode(fdt, nodename); - qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 1000000000= ); + qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", + SIFIVE_U_CLOCK_FREQ); qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48"); qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa); qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv"); diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 2d1f114..4c233ec 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -115,7 +115,8 @@ static void create_fdt(SpikeState *s, const struct Memm= apEntry *memmap, g_free(nodename); =20 qemu_fdt_add_subnode(fdt, "/cpus"); - qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", 10000000); + qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", + SIFIVE_CLINT_TIMEBASE_FREQ); qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); =20 @@ -124,7 +125,8 @@ static void create_fdt(SpikeState *s, const struct Memm= apEntry *memmap, char *intc =3D g_strdup_printf("/cpus/cpu@%d/interrupt-controller"= , cpu); char *isa =3D riscv_isa_string(&s->soc.harts[cpu]); qemu_fdt_add_subnode(fdt, nodename); - qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 1000000000= ); + qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", + SPIKE_CLOCK_FREQ); qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48"); qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa); qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv"); diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 37968d2..a402856 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -145,7 +145,8 @@ static void create_fdt(RISCVVirtState *s, const struct = MemmapEntry *memmap, g_free(nodename); =20 qemu_fdt_add_subnode(fdt, "/cpus"); - qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", 10000000); + qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", + SIFIVE_CLINT_TIMEBASE_FREQ); qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); =20 @@ -155,7 +156,8 @@ static void create_fdt(RISCVVirtState *s, const struct = MemmapEntry *memmap, char *intc =3D g_strdup_printf("/cpus/cpu@%d/interrupt-controller"= , cpu); char *isa =3D riscv_isa_string(&s->soc.harts[cpu]); qemu_fdt_add_subnode(fdt, nodename); - qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 1000000000= ); + qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", + VIRT_CLOCK_FREQ); qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48"); qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa); qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv"); diff --git a/include/hw/riscv/sifive_clint.h b/include/hw/riscv/sifive_clin= t.h index aaa2a58..e2865be 100644 --- a/include/hw/riscv/sifive_clint.h +++ b/include/hw/riscv/sifive_clint.h @@ -47,4 +47,8 @@ enum { SIFIVE_TIME_BASE =3D 0xBFF8 }; =20 +enum { + SIFIVE_CLINT_TIMEBASE_FREQ =3D 10000000 +}; + #endif diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 662e8a1..be38aa0 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -50,6 +50,10 @@ enum { SIFIVE_U_UART1_IRQ =3D 4 }; =20 +enum { + SIFIVE_U_CLOCK_FREQ =3D 1000000000 +}; + #define SIFIVE_U_PLIC_HART_CONFIG "MS" #define SIFIVE_U_PLIC_NUM_SOURCES 127 #define SIFIVE_U_PLIC_NUM_PRIORITIES 7 diff --git a/include/hw/riscv/spike.h b/include/hw/riscv/spike.h index cb55a14..d85a64e 100644 --- a/include/hw/riscv/spike.h +++ b/include/hw/riscv/spike.h @@ -42,6 +42,10 @@ enum { SPIKE_DRAM }; =20 +enum { + SPIKE_CLOCK_FREQ =3D 1000000000 +}; + #if defined(TARGET_RISCV32) #define SPIKE_V1_09_1_CPU TYPE_RISCV_CPU_RV32GCSU_V1_09_1 #define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_RV32GCSU_V1_10_0 diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index 7525647..2fbe808 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -55,6 +55,10 @@ enum { VIRTIO_NDEV =3D 10 }; =20 +enum { + VIRT_CLOCK_FREQ =3D 1000000000 +}; + #define VIRT_PLIC_HART_CONFIG "MS" #define VIRT_PLIC_NUM_SOURCES 127 #define VIRT_PLIC_NUM_PRIORITIES 7 --=20 2.7.0 From nobody Sun Feb 8 16:34:30 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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X-Received-From: 2607:f8b0:400e:c01::242 Subject: [Qemu-devel] [PATCH v4 03/26] RISC-V: Make virt board description match spike X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@groups.riscv.org, Michael Clark , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 This makes 'qemu-system-riscv64 -machine help' output more tidy and consistent. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/riscv/virt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index a402856..0055439 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -404,7 +404,7 @@ static const TypeInfo riscv_virt_board_device =3D { =20 static void riscv_virt_board_machine_init(MachineClass *mc) { - mc->desc =3D "RISC-V VirtIO Board (Privileged spec v1.10)"; + mc->desc =3D "RISC-V VirtIO Board (Privileged ISA v1.10)"; mc->init =3D riscv_virt_board_init; mc->max_cpus =3D 8; /* hardcoded limit in BBL */ } --=20 2.7.0 From nobody Sun Feb 8 16:34:30 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1521494692547756.6037351207268; Mon, 19 Mar 2018 14:24:52 -0700 (PDT) Received: from localhost ([::1]:43998 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ey2Gx-0005Kz-Lv for importer@patchew.org; Mon, 19 Mar 2018 17:24:51 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33156) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ey2C5-0001Jz-3Z for qemu-devel@nongnu.org; Mon, 19 Mar 2018 17:19:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ey2C0-0002YE-UZ for qemu-devel@nongnu.org; Mon, 19 Mar 2018 17:19:49 -0400 Received: from mail-pl0-x244.google.com ([2607:f8b0:400e:c01::244]:45259) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ey2C0-0002XY-O0 for qemu-devel@nongnu.org; Mon, 19 Mar 2018 17:19:44 -0400 Received: by mail-pl0-x244.google.com with SMTP id n15-v6so3304565plp.12 for ; Mon, 19 Mar 2018 14:19:44 -0700 (PDT) Received: from monty.com ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id i127sm120500pfc.136.2018.03.19.14.19.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 19 Mar 2018 14:19:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=etZGfs2I6eIUVzklmG0XvLcDBBdWMcIvQq939Ceof5k=; b=Y0i/h+X1mffp4L4rDr3yne65XU9zfEN8m/QzVPqfR8/YnOr1XxTSmP8MTrdzFWeJ20 2Rt3MadUcsfcLtMQdOI+gsloGauhjT5i34LCmp1noDkE6hFePrH4myT+MDP74XZ5F+Ne QQiXRWazWiJ9WEp5cbs8RV11Mc2M1qZAph71K0/8XbYqCSRQ0rhrX4bBwNN22WyXlXir UdW1eNCWnZTh3mp4lK+9Qcb4a4okvj5yAvzNeya+knqqg/Ph02X7l5oQNwMdwAHTyCjA 9agDP8P9dp2qPBA0/VEAI49wLA1waFc2g5l7aMFSPhWM5NOAuzpaaZsVOR0bzU0un5bv 2Jgg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=etZGfs2I6eIUVzklmG0XvLcDBBdWMcIvQq939Ceof5k=; b=hOPI3boh+MSJN55QWJQQPj/zFZZBDzVcezqPVjYrcfO7Szkv5aR5EmguaNJxyrT1EQ HJi4DiRUvusqXk42r8O0tWjDN9Ie10w041tJxr3MgNlKzCQiBS5DNAgM1C5EC9nPc5Pl ss2oZnAc+JEgOifX0GZj94HpfiyQc/d+0dUnKz/KD2Ygm0r0mb9oPpNxVARweN2nKEtl g8yUs8XEXLfRrE6dT9v/dgNf2wEr6YmoBOQYu2anxtwQrlA0F37TVFfSNkKFtBgrholY BJ+XpzlCs9Eux9YdAwEUFvvhRef+dupJPBivlSGZATMnb11vhK9nyKf4f6nbDikKYfcU JRow== X-Gm-Message-State: AElRT7GCHPPBICbyRVj3j7SWhdIUDofB69285+M4zMtpk9GV7onONvuB sluaqK+1UAGrn5V7gccR+wg4sTncd8M= X-Google-Smtp-Source: AG47ELuKrkUWRjYP5rv8GvKS4fRfh4wj1JbCh87LnCxdQK4ERj0Sfuw+ihEo2mYUSq844MQbfF8g+g== X-Received: by 2002:a17:902:7b95:: with SMTP id w21-v6mr14222096pll.260.1521494383869; Mon, 19 Mar 2018 14:19:43 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Mon, 19 Mar 2018 14:18:27 -0700 Message-Id: <1521494329-19546-5-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1521494329-19546-1-git-send-email-mjc@sifive.com> References: <1521494329-19546-1-git-send-email-mjc@sifive.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::244 Subject: [Qemu-devel] [PATCH v4 04/26] RISC-V: Use ROM base address and size from memmap X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@groups.riscv.org, Michael Clark , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Another case of replacing hard coded constants, this time referring to the definition in the virt machine's memmap. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/riscv/virt.c | 4 ++-- include/hw/riscv/virt.h | 2 -- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 0055439..0d101fc 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -338,11 +338,11 @@ static void riscv_virt_board_init(MachineState *machi= ne) }; =20 /* copy in the reset vector */ - copy_le32_to_phys(ROM_BASE, reset_vec, sizeof(reset_vec)); + copy_le32_to_phys(memmap[VIRT_MROM].base, reset_vec, sizeof(reset_vec)= ); =20 /* copy in the device tree */ qemu_fdt_dumpdtb(s->fdt, s->fdt_size); - cpu_physical_memory_write(ROM_BASE + sizeof(reset_vec), + cpu_physical_memory_write(memmap[VIRT_MROM].base + sizeof(reset_vec), s->fdt, s->fdt_size); =20 /* create PLIC hart topology configuration string */ diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index 2fbe808..655e85d 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -23,8 +23,6 @@ #define VIRT(obj) \ OBJECT_CHECK(RISCVVirtState, (obj), TYPE_RISCV_VIRT_BOARD) =20 -enum { ROM_BASE =3D 0x1000 }; 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Mon, 19 Mar 2018 14:19:44 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Mon, 19 Mar 2018 14:18:28 -0700 Message-Id: <1521494329-19546-6-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1521494329-19546-1-git-send-email-mjc@sifive.com> References: <1521494329-19546-1-git-send-email-mjc@sifive.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::241 Subject: [Qemu-devel] [PATCH v4 05/26] RISC-V: Remove identity_translate from load_elf X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@groups.riscv.org, Michael Clark , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 When load_elf is called with NULL as an argument to the address translate callback, it does an identity translation. This commit removes the redundant identity_translate callback. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/riscv/sifive_e.c | 7 +------ hw/riscv/sifive_u.c | 7 +------ hw/riscv/spike.c | 7 +------ hw/riscv/virt.c | 7 +------ 4 files changed, 4 insertions(+), 24 deletions(-) diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 19eca36..09c9d49 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -82,16 +82,11 @@ static void copy_le32_to_phys(hwaddr pa, uint32_t *rom,= size_t len) } } =20 -static uint64_t identity_translate(void *opaque, uint64_t addr) -{ - return addr; -} - static uint64_t load_kernel(const char *kernel_filename) { uint64_t kernel_entry, kernel_high; =20 - if (load_elf(kernel_filename, identity_translate, NULL, + if (load_elf(kernel_filename, NULL, NULL, &kernel_entry, NULL, &kernel_high, 0, ELF_MACHINE, 1, 0) < 0) { error_report("qemu: could not load kernel '%s'", kernel_filename); diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index f3f7615..6116c38 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -68,16 +68,11 @@ static void copy_le32_to_phys(hwaddr pa, uint32_t *rom,= size_t len) } } =20 -static uint64_t identity_translate(void *opaque, uint64_t addr) -{ - return addr; -} - static uint64_t load_kernel(const char *kernel_filename) { uint64_t kernel_entry, kernel_high; =20 - if (load_elf(kernel_filename, identity_translate, NULL, + if (load_elf(kernel_filename, NULL, NULL, &kernel_entry, NULL, &kernel_high, 0, ELF_MACHINE, 1, 0) < 0) { error_report("qemu: could not load kernel '%s'", kernel_filename); diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 4c233ec..7710333 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -59,16 +59,11 @@ static void copy_le32_to_phys(hwaddr pa, uint32_t *rom,= size_t len) } } =20 -static uint64_t identity_translate(void *opaque, uint64_t addr) -{ - return addr; -} - static uint64_t load_kernel(const char *kernel_filename) { uint64_t kernel_entry, kernel_high; =20 - if (load_elf_ram_sym(kernel_filename, identity_translate, NULL, + if (load_elf_ram_sym(kernel_filename, NULL, NULL, &kernel_entry, NULL, &kernel_high, 0, ELF_MACHINE, 1, 0, NULL, true, htif_symbol_callback) < 0) { error_report("qemu: could not load kernel '%s'", kernel_filename); diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 0d101fc..f8c19b4 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -62,16 +62,11 @@ static void copy_le32_to_phys(hwaddr pa, uint32_t *rom,= size_t len) } } =20 -static uint64_t identity_translate(void *opaque, uint64_t addr) -{ - return addr; -} - static uint64_t load_kernel(const char *kernel_filename) { uint64_t kernel_entry, kernel_high; =20 - if (load_elf(kernel_filename, identity_translate, NULL, + if (load_elf(kernel_filename, NULL, NULL, &kernel_entry, NULL, &kernel_high, 0, ELF_MACHINE, 1, 0) < 0) { error_report("qemu: could not load kernel '%s'", kernel_filename); --=20 2.7.0 From nobody Sun Feb 8 16:34:30 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 152149506723634.95721636362657; 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Mon, 19 Mar 2018 14:19:45 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Mon, 19 Mar 2018 14:18:29 -0700 Message-Id: <1521494329-19546-7-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1521494329-19546-1-git-send-email-mjc@sifive.com> References: <1521494329-19546-1-git-send-email-mjc@sifive.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::243 Subject: [Qemu-devel] [PATCH v4 06/26] RISC-V: Mark ROM read-only after copying in code X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@groups.riscv.org, Michael Clark , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The sifive_u machine already marks its ROM readonly. This fixes the remaining boards. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt --- hw/riscv/sifive_u.c | 9 +++++---- hw/riscv/spike.c | 18 ++++++++++-------- hw/riscv/virt.c | 7 ++++--- include/hw/riscv/spike.h | 8 -------- 4 files changed, 19 insertions(+), 23 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 6116c38..25df16c 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -223,7 +223,7 @@ static void riscv_sifive_u_init(MachineState *machine) SiFiveUState *s =3D g_new0(SiFiveUState, 1); MemoryRegion *sys_memory =3D get_system_memory(); MemoryRegion *main_mem =3D g_new(MemoryRegion, 1); - MemoryRegion *boot_rom =3D g_new(MemoryRegion, 1); + MemoryRegion *mask_rom =3D g_new(MemoryRegion, 1); =20 /* Initialize SOC */ object_initialize(&s->soc, sizeof(s->soc), TYPE_RISCV_HART_ARRAY); @@ -246,10 +246,10 @@ static void riscv_sifive_u_init(MachineState *machine) create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); =20 /* boot rom */ - memory_region_init_ram(boot_rom, NULL, "riscv.sifive.u.mrom", + memory_region_init_ram(mask_rom, NULL, "riscv.sifive.u.mrom", memmap[SIFIVE_U_MROM].base, &error_fatal); - memory_region_set_readonly(boot_rom, true); - memory_region_add_subregion(sys_memory, 0x0, boot_rom); + memory_region_set_readonly(mask_rom, true); + memory_region_add_subregion(sys_memory, 0x0, mask_rom); =20 if (machine->kernel_filename) { load_kernel(machine->kernel_filename); @@ -279,6 +279,7 @@ static void riscv_sifive_u_init(MachineState *machine) qemu_fdt_dumpdtb(s->fdt, s->fdt_size); cpu_physical_memory_write(memmap[SIFIVE_U_MROM].base + sizeof(reset_vec), s->fdt, s->fdt_size); + memory_region_set_readonly(mask_rom, true); =20 /* MMIO */ s->plic =3D sifive_plic_create(memmap[SIFIVE_U_PLIC].base, diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 7710333..74edf33 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -173,7 +173,7 @@ static void spike_v1_10_0_board_init(MachineState *mach= ine) SpikeState *s =3D g_new0(SpikeState, 1); MemoryRegion *system_memory =3D get_system_memory(); MemoryRegion *main_mem =3D g_new(MemoryRegion, 1); - MemoryRegion *boot_rom =3D g_new(MemoryRegion, 1); + MemoryRegion *mask_rom =3D g_new(MemoryRegion, 1); =20 /* Initialize SOC */ object_initialize(&s->soc, sizeof(s->soc), TYPE_RISCV_HART_ARRAY); @@ -196,9 +196,9 @@ static void spike_v1_10_0_board_init(MachineState *mach= ine) create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); =20 /* boot rom */ - memory_region_init_ram(boot_rom, NULL, "riscv.spike.bootrom", + memory_region_init_ram(mask_rom, NULL, "riscv.spike.mrom", s->fdt_size + 0x2000, &error_fatal); - memory_region_add_subregion(system_memory, 0x0, boot_rom); + memory_region_add_subregion(system_memory, 0x0, mask_rom); =20 if (machine->kernel_filename) { load_kernel(machine->kernel_filename); @@ -228,9 +228,10 @@ static void spike_v1_10_0_board_init(MachineState *mac= hine) qemu_fdt_dumpdtb(s->fdt, s->fdt_size); cpu_physical_memory_write(memmap[SPIKE_MROM].base + sizeof(reset_vec), s->fdt, s->fdt_size); + memory_region_set_readonly(mask_rom, true); =20 /* initialize HTIF using symbols found in load_kernel */ - htif_mm_init(system_memory, boot_rom, &s->soc.harts[0].env, serial_hds= [0]); + htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hds= [0]); =20 /* Core Local Interruptor (timer and IPI) */ sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size, @@ -244,7 +245,7 @@ static void spike_v1_09_1_board_init(MachineState *mach= ine) SpikeState *s =3D g_new0(SpikeState, 1); MemoryRegion *system_memory =3D get_system_memory(); MemoryRegion *main_mem =3D g_new(MemoryRegion, 1); - MemoryRegion *boot_rom =3D g_new(MemoryRegion, 1); + MemoryRegion *mask_rom =3D g_new(MemoryRegion, 1); =20 /* Initialize SOC */ object_initialize(&s->soc, sizeof(s->soc), TYPE_RISCV_HART_ARRAY); @@ -264,9 +265,9 @@ static void spike_v1_09_1_board_init(MachineState *mach= ine) main_mem); =20 /* boot rom */ - memory_region_init_ram(boot_rom, NULL, "riscv.spike.bootrom", + memory_region_init_ram(mask_rom, NULL, "riscv.spike.mrom", 0x40000, &error_fatal); - memory_region_add_subregion(system_memory, 0x0, boot_rom); + memory_region_add_subregion(system_memory, 0x0, mask_rom); =20 if (machine->kernel_filename) { load_kernel(machine->kernel_filename); @@ -325,9 +326,10 @@ static void spike_v1_09_1_board_init(MachineState *mac= hine) /* copy in the config string */ cpu_physical_memory_write(memmap[SPIKE_MROM].base + sizeof(reset_vec), config_string, config_string_len); + memory_region_set_readonly(mask_rom, true); =20 /* initialize HTIF using symbols found in load_kernel */ - htif_mm_init(system_memory, boot_rom, &s->soc.harts[0].env, serial_hds= [0]); + htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hds= [0]); =20 /* Core Local Interruptor (timer and IPI) */ sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size, diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index f8c19b4..f1e3641 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -270,7 +270,7 @@ static void riscv_virt_board_init(MachineState *machine) RISCVVirtState *s =3D g_new0(RISCVVirtState, 1); MemoryRegion *system_memory =3D get_system_memory(); MemoryRegion *main_mem =3D g_new(MemoryRegion, 1); - MemoryRegion *boot_rom =3D g_new(MemoryRegion, 1); + MemoryRegion *mask_rom =3D g_new(MemoryRegion, 1); char *plic_hart_config; size_t plic_hart_config_len; int i; @@ -296,9 +296,9 @@ static void riscv_virt_board_init(MachineState *machine) create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); =20 /* boot rom */ - memory_region_init_ram(boot_rom, NULL, "riscv_virt_board.bootrom", + memory_region_init_ram(mask_rom, NULL, "riscv_virt_board.mrom", s->fdt_size + 0x2000, &error_fatal); - memory_region_add_subregion(system_memory, 0x0, boot_rom); + memory_region_add_subregion(system_memory, 0x0, mask_rom); =20 if (machine->kernel_filename) { uint64_t kernel_entry =3D load_kernel(machine->kernel_filename); @@ -339,6 +339,7 @@ static void riscv_virt_board_init(MachineState *machine) qemu_fdt_dumpdtb(s->fdt, s->fdt_size); cpu_physical_memory_write(memmap[VIRT_MROM].base + sizeof(reset_vec), s->fdt, s->fdt_size); + memory_region_set_readonly(mask_rom, true); =20 /* create PLIC hart topology configuration string */ plic_hart_config_len =3D (strlen(VIRT_PLIC_HART_CONFIG) + 1) * smp_cpu= s; diff --git a/include/hw/riscv/spike.h b/include/hw/riscv/spike.h index d85a64e..179b6cf 100644 --- a/include/hw/riscv/spike.h +++ b/include/hw/riscv/spike.h @@ -22,20 +22,12 @@ #define TYPE_RISCV_SPIKE_V1_09_1_BOARD "riscv.spike_v1_9_1" #define TYPE_RISCV_SPIKE_V1_10_0_BOARD "riscv.spike_v1_10" =20 -#define SPIKE(obj) \ - OBJECT_CHECK(SpikeState, (obj), TYPE_RISCV_SPIKE_BOARD) - typedef struct { - /*< private >*/ - SysBusDevice parent_obj; - - /*< public >*/ RISCVHartArrayState soc; void *fdt; int fdt_size; } SpikeState; =20 - enum { SPIKE_MROM, SPIKE_CLINT, --=20 2.7.0 From nobody Sun Feb 8 16:34:30 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1521495254458266.41993147524977; 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Mon, 19 Mar 2018 14:19:46 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Mon, 19 Mar 2018 14:18:30 -0700 Message-Id: <1521494329-19546-8-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1521494329-19546-1-git-send-email-mjc@sifive.com> References: <1521494329-19546-1-git-send-email-mjc@sifive.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::244 Subject: [Qemu-devel] [PATCH v4 07/26] RISC-V: Remove unused class definitions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@groups.riscv.org, Michael Clark , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Removes a whole lot of unnecessary boilerplate code. Machines don't need to be objects. The expansion of the SOC object model for the RISC-V machines will happen in the future as SiFive plans to add their FE310 and FU540 SOCs to QEMU. However, it seems that this present boilerplate is complete unnecessary. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/riscv/riscv_hart.c | 6 ------ hw/riscv/sifive_e.c | 25 ------------------------- hw/riscv/sifive_u.c | 25 ------------------------- hw/riscv/spike.c | 20 -------------------- hw/riscv/virt.c | 25 ------------------------- include/hw/riscv/sifive_e.h | 5 ----- include/hw/riscv/sifive_u.h | 5 ----- include/hw/riscv/spike.h | 7 ++++--- include/hw/riscv/virt.h | 5 ----- 9 files changed, 4 insertions(+), 119 deletions(-) diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c index 14e3c18..75ba7ed 100644 --- a/hw/riscv/riscv_hart.c +++ b/hw/riscv/riscv_hart.c @@ -68,16 +68,10 @@ static void riscv_harts_class_init(ObjectClass *klass, = void *data) dc->realize =3D riscv_harts_realize; } =20 -static void riscv_harts_init(Object *obj) -{ - /* RISCVHartArrayState *s =3D SIFIVE_COREPLEX(obj); */ -} - static const TypeInfo riscv_harts_info =3D { .name =3D TYPE_RISCV_HART_ARRAY, .parent =3D TYPE_SYS_BUS_DEVICE, .instance_size =3D sizeof(RISCVHartArrayState), - .instance_init =3D riscv_harts_init, .class_init =3D riscv_harts_class_init, }; =20 diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 09c9d49..4872b68 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -194,24 +194,6 @@ static void riscv_sifive_e_init(MachineState *machine) } } =20 -static int riscv_sifive_e_sysbus_device_init(SysBusDevice *sysbusdev) -{ - return 0; -} - -static void riscv_sifive_e_class_init(ObjectClass *klass, void *data) -{ - SysBusDeviceClass *k =3D SYS_BUS_DEVICE_CLASS(klass); - k->init =3D riscv_sifive_e_sysbus_device_init; -} - -static const TypeInfo riscv_sifive_e_device =3D { - .name =3D TYPE_SIFIVE_E, - .parent =3D TYPE_SYS_BUS_DEVICE, - .instance_size =3D sizeof(SiFiveEState), - .class_init =3D riscv_sifive_e_class_init, -}; - static void riscv_sifive_e_machine_init(MachineClass *mc) { mc->desc =3D "RISC-V Board compatible with SiFive E SDK"; @@ -220,10 +202,3 @@ static void riscv_sifive_e_machine_init(MachineClass *= mc) } =20 DEFINE_MACHINE("sifive_e", riscv_sifive_e_machine_init) - -static void riscv_sifive_e_register_types(void) -{ - type_register_static(&riscv_sifive_e_device); -} - -type_init(riscv_sifive_e_register_types); diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 25df16c..083043a 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -302,31 +302,6 @@ static void riscv_sifive_u_init(MachineState *machine) SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE); } =20 -static int riscv_sifive_u_sysbus_device_init(SysBusDevice *sysbusdev) -{ - return 0; -} - -static void riscv_sifive_u_class_init(ObjectClass *klass, void *data) -{ - SysBusDeviceClass *k =3D SYS_BUS_DEVICE_CLASS(klass); - k->init =3D riscv_sifive_u_sysbus_device_init; -} - -static const TypeInfo riscv_sifive_u_device =3D { - .name =3D TYPE_SIFIVE_U, - .parent =3D TYPE_SYS_BUS_DEVICE, - .instance_size =3D sizeof(SiFiveUState), - .class_init =3D riscv_sifive_u_class_init, -}; - -static void riscv_sifive_u_register_types(void) -{ - type_register_static(&riscv_sifive_u_device); -} - -type_init(riscv_sifive_u_register_types); - static void riscv_sifive_u_machine_init(MachineClass *mc) { mc->desc =3D "RISC-V Board compatible with SiFive U SDK"; diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 74edf33..64e585e 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -336,18 +336,6 @@ static void spike_v1_09_1_board_init(MachineState *mac= hine) smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE); } =20 -static const TypeInfo spike_v_1_09_1_device =3D { - .name =3D TYPE_RISCV_SPIKE_V1_09_1_BOARD, - .parent =3D TYPE_SYS_BUS_DEVICE, - .instance_size =3D sizeof(SpikeState), -}; - -static const TypeInfo spike_v_1_10_0_device =3D { - .name =3D TYPE_RISCV_SPIKE_V1_10_0_BOARD, - .parent =3D TYPE_SYS_BUS_DEVICE, - .instance_size =3D sizeof(SpikeState), -}; - static void spike_v1_09_1_machine_init(MachineClass *mc) { mc->desc =3D "RISC-V Spike Board (Privileged ISA v1.9.1)"; @@ -365,11 +353,3 @@ static void spike_v1_10_0_machine_init(MachineClass *m= c) =20 DEFINE_MACHINE("spike_v1.9.1", spike_v1_09_1_machine_init) DEFINE_MACHINE("spike_v1.10", spike_v1_10_0_machine_init) - -static void riscv_spike_board_register_types(void) -{ - type_register_static(&spike_v_1_09_1_device); - type_register_static(&spike_v_1_10_0_device); -} - -type_init(riscv_spike_board_register_types); diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index f1e3641..5913100 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -380,24 +380,6 @@ static void riscv_virt_board_init(MachineState *machin= e) serial_hds[0], DEVICE_LITTLE_ENDIAN); } =20 -static int riscv_virt_board_sysbus_device_init(SysBusDevice *sysbusdev) -{ - return 0; -} - -static void riscv_virt_board_class_init(ObjectClass *klass, void *data) -{ - SysBusDeviceClass *k =3D SYS_BUS_DEVICE_CLASS(klass); - k->init =3D riscv_virt_board_sysbus_device_init; -} - -static const TypeInfo riscv_virt_board_device =3D { - .name =3D TYPE_RISCV_VIRT_BOARD, - .parent =3D TYPE_SYS_BUS_DEVICE, - .instance_size =3D sizeof(RISCVVirtState), - .class_init =3D riscv_virt_board_class_init, -}; - static void riscv_virt_board_machine_init(MachineClass *mc) { mc->desc =3D "RISC-V VirtIO Board (Privileged ISA v1.10)"; @@ -406,10 +388,3 @@ static void riscv_virt_board_machine_init(MachineClass= *mc) } =20 DEFINE_MACHINE("virt", riscv_virt_board_machine_init) - -static void riscv_virt_board_register_types(void) -{ - type_register_static(&riscv_virt_board_device); -} - -type_init(riscv_virt_board_register_types); diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h index 0aebc57..12ad6d2 100644 --- a/include/hw/riscv/sifive_e.h +++ b/include/hw/riscv/sifive_e.h @@ -19,11 +19,6 @@ #ifndef HW_SIFIVE_E_H #define HW_SIFIVE_E_H =20 -#define TYPE_SIFIVE_E "riscv.sifive_e" - -#define SIFIVE_E(obj) \ - OBJECT_CHECK(SiFiveEState, (obj), TYPE_SIFIVE_E) - typedef struct SiFiveEState { /*< private >*/ SysBusDevice parent_obj; diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index be38aa0..94a3905 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -19,11 +19,6 @@ #ifndef HW_SIFIVE_U_H #define HW_SIFIVE_U_H =20 -#define TYPE_SIFIVE_U "riscv.sifive_u" - -#define SIFIVE_U(obj) \ - OBJECT_CHECK(SiFiveUState, (obj), TYPE_SIFIVE_U) - typedef struct SiFiveUState { /*< private >*/ SysBusDevice parent_obj; diff --git a/include/hw/riscv/spike.h b/include/hw/riscv/spike.h index 179b6cf..8410430 100644 --- a/include/hw/riscv/spike.h +++ b/include/hw/riscv/spike.h @@ -19,10 +19,11 @@ #ifndef HW_SPIKE_H #define HW_SPIKE_H =20 -#define TYPE_RISCV_SPIKE_V1_09_1_BOARD "riscv.spike_v1_9_1" -#define TYPE_RISCV_SPIKE_V1_10_0_BOARD "riscv.spike_v1_10" - typedef struct { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ RISCVHartArrayState soc; void *fdt; int fdt_size; diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index 655e85d..b91a412 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -19,10 +19,6 @@ #ifndef HW_VIRT_H #define HW_VIRT_H =20 -#define TYPE_RISCV_VIRT_BOARD "riscv.virt" -#define VIRT(obj) \ - OBJECT_CHECK(RISCVVirtState, (obj), TYPE_RISCV_VIRT_BOARD) - typedef struct { /*< private >*/ SysBusDevice parent_obj; @@ -45,7 +41,6 @@ enum { VIRT_DRAM }; =20 - enum { UART0_IRQ =3D 10, VIRTIO_IRQ =3D 1, /* 1 to 8 */ --=20 2.7.0 From nobody Sun Feb 8 16:34:30 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1521494855646248.04762582277328; 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Mon, 19 Mar 2018 14:19:47 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Mon, 19 Mar 2018 14:18:31 -0700 Message-Id: <1521494329-19546-9-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1521494329-19546-1-git-send-email-mjc@sifive.com> References: <1521494329-19546-1-git-send-email-mjc@sifive.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::241 Subject: [Qemu-devel] [PATCH v4 08/26] RISC-V: Make sure rom has space for fdt X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@groups.riscv.org, Michael Clark , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Remove a potential buffer overflow (not seen in practice). Perhaps cpu_physical_memory_write already has bound checks. This change however makes space for the maximum device tree size and adds an explicit bounds check and error message. It doesn't trigger, but it may help in the future if the device-tree size is exceeded. e.g. large bootargs. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt --- hw/riscv/sifive_u.c | 20 ++++++++++++-------- hw/riscv/spike.c | 16 +++++++++++----- hw/riscv/virt.c | 13 +++++++++---- 3 files changed, 32 insertions(+), 17 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 083043a..57b4f4f 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -52,7 +52,7 @@ static const struct MemmapEntry { hwaddr size; } sifive_u_memmap[] =3D { [SIFIVE_U_DEBUG] =3D { 0x0, 0x100 }, - [SIFIVE_U_MROM] =3D { 0x1000, 0x2000 }, + [SIFIVE_U_MROM] =3D { 0x1000, 0x11000 }, [SIFIVE_U_CLINT] =3D { 0x2000000, 0x10000 }, [SIFIVE_U_PLIC] =3D { 0xc000000, 0x4000000 }, [SIFIVE_U_UART0] =3D { 0x10013000, 0x1000 }, @@ -221,7 +221,7 @@ static void riscv_sifive_u_init(MachineState *machine) const struct MemmapEntry *memmap =3D sifive_u_memmap; =20 SiFiveUState *s =3D g_new0(SiFiveUState, 1); - MemoryRegion *sys_memory =3D get_system_memory(); + MemoryRegion *system_memory =3D get_system_memory(); MemoryRegion *main_mem =3D g_new(MemoryRegion, 1); MemoryRegion *mask_rom =3D g_new(MemoryRegion, 1); =20 @@ -239,7 +239,7 @@ static void riscv_sifive_u_init(MachineState *machine) /* register RAM */ memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram", machine->ram_size, &error_fatal); - memory_region_add_subregion(sys_memory, memmap[SIFIVE_U_DRAM].base, + memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DRAM].base, main_mem); =20 /* create device tree */ @@ -247,9 +247,9 @@ static void riscv_sifive_u_init(MachineState *machine) =20 /* boot rom */ memory_region_init_ram(mask_rom, NULL, "riscv.sifive.u.mrom", - memmap[SIFIVE_U_MROM].base, &error_fatal); - memory_region_set_readonly(mask_rom, true); - memory_region_add_subregion(sys_memory, 0x0, mask_rom); + memmap[SIFIVE_U_MROM].size, &error_fatal); + memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base, + mask_rom); =20 if (machine->kernel_filename) { load_kernel(machine->kernel_filename); @@ -276,6 +276,10 @@ static void riscv_sifive_u_init(MachineState *machine) copy_le32_to_phys(memmap[SIFIVE_U_MROM].base, reset_vec, sizeof(reset_= vec)); =20 /* copy in the device tree */ + if (s->fdt_size >=3D memmap[SIFIVE_U_MROM].size - sizeof(reset_vec)) { + error_report("qemu: not enough space to store device-tree"); + exit(1); + } qemu_fdt_dumpdtb(s->fdt, s->fdt_size); cpu_physical_memory_write(memmap[SIFIVE_U_MROM].base + sizeof(reset_vec), s->fdt, s->fdt_size); @@ -293,9 +297,9 @@ static void riscv_sifive_u_init(MachineState *machine) SIFIVE_U_PLIC_CONTEXT_BASE, SIFIVE_U_PLIC_CONTEXT_STRIDE, memmap[SIFIVE_U_PLIC].size); - sifive_uart_create(sys_memory, memmap[SIFIVE_U_UART0].base, + sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base, serial_hds[0], SIFIVE_PLIC(s->plic)->irqs[SIFIVE_U_UART0_IRQ]); - /* sifive_uart_create(sys_memory, memmap[SIFIVE_U_UART1].base, + /* sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base, serial_hds[1], SIFIVE_PLIC(s->plic)->irqs[SIFIVE_U_UART1_IRQ]); */ sifive_clint_create(memmap[SIFIVE_U_CLINT].base, memmap[SIFIVE_U_CLINT].size, smp_cpus, diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 64e585e..c7d937b 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -46,7 +46,7 @@ static const struct MemmapEntry { hwaddr base; hwaddr size; } spike_memmap[] =3D { - [SPIKE_MROM] =3D { 0x1000, 0x2000 }, + [SPIKE_MROM] =3D { 0x1000, 0x11000 }, [SPIKE_CLINT] =3D { 0x2000000, 0x10000 }, [SPIKE_DRAM] =3D { 0x80000000, 0x0 }, }; @@ -197,8 +197,9 @@ static void spike_v1_10_0_board_init(MachineState *mach= ine) =20 /* boot rom */ memory_region_init_ram(mask_rom, NULL, "riscv.spike.mrom", - s->fdt_size + 0x2000, &error_fatal); - memory_region_add_subregion(system_memory, 0x0, mask_rom); + memmap[SPIKE_MROM].size, &error_fatal); + memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base, + mask_rom); =20 if (machine->kernel_filename) { load_kernel(machine->kernel_filename); @@ -225,6 +226,10 @@ static void spike_v1_10_0_board_init(MachineState *mac= hine) copy_le32_to_phys(memmap[SPIKE_MROM].base, reset_vec, sizeof(reset_vec= )); =20 /* copy in the device tree */ + if (s->fdt_size >=3D memmap[SPIKE_MROM].size - sizeof(reset_vec)) { + error_report("qemu: not enough space to store device-tree"); + exit(1); + } qemu_fdt_dumpdtb(s->fdt, s->fdt_size); cpu_physical_memory_write(memmap[SPIKE_MROM].base + sizeof(reset_vec), s->fdt, s->fdt_size); @@ -266,8 +271,9 @@ static void spike_v1_09_1_board_init(MachineState *mach= ine) =20 /* boot rom */ memory_region_init_ram(mask_rom, NULL, "riscv.spike.mrom", - 0x40000, &error_fatal); - memory_region_add_subregion(system_memory, 0x0, mask_rom); + memmap[SPIKE_MROM].size, &error_fatal); + memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base, + mask_rom); =20 if (machine->kernel_filename) { load_kernel(machine->kernel_filename); diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 5913100..d680cbd 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -45,8 +45,8 @@ static const struct MemmapEntry { hwaddr size; } virt_memmap[] =3D { [VIRT_DEBUG] =3D { 0x0, 0x100 }, - [VIRT_MROM] =3D { 0x1000, 0x2000 }, - [VIRT_TEST] =3D { 0x4000, 0x1000 }, + [VIRT_MROM] =3D { 0x1000, 0x11000 }, + [VIRT_TEST] =3D { 0x100000, 0x1000 }, [VIRT_CLINT] =3D { 0x2000000, 0x10000 }, [VIRT_PLIC] =3D { 0xc000000, 0x4000000 }, [VIRT_UART0] =3D { 0x10000000, 0x100 }, @@ -297,8 +297,9 @@ static void riscv_virt_board_init(MachineState *machine) =20 /* boot rom */ memory_region_init_ram(mask_rom, NULL, "riscv_virt_board.mrom", - s->fdt_size + 0x2000, &error_fatal); - memory_region_add_subregion(system_memory, 0x0, mask_rom); + memmap[VIRT_MROM].size, &error_fatal); + memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base, + mask_rom); =20 if (machine->kernel_filename) { uint64_t kernel_entry =3D load_kernel(machine->kernel_filename); @@ -336,6 +337,10 @@ static void riscv_virt_board_init(MachineState *machin= e) copy_le32_to_phys(memmap[VIRT_MROM].base, reset_vec, sizeof(reset_vec)= ); =20 /* copy in the device tree */ + if (s->fdt_size >=3D memmap[VIRT_MROM].size - sizeof(reset_vec)) { + error_report("qemu: not enough space to store device-tree"); + exit(1); + } qemu_fdt_dumpdtb(s->fdt, s->fdt_size); cpu_physical_memory_write(memmap[VIRT_MROM].base + sizeof(reset_vec), s->fdt, s->fdt_size); --=20 2.7.0 From nobody Sun Feb 8 16:34:30 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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X-Received-From: 2607:f8b0:400e:c01::243 Subject: [Qemu-devel] [PATCH v4 09/26] RISC-V: Include intruction hex in disassembly X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@groups.riscv.org, Michael Clark , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 This was added to help debug issues using -d in_asm. It is useful to see the instruction bytes, as one can detect if one is trying to execute ASCII or device-tree magic. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- disas/riscv.c | 39 ++++++++++++++++++++------------------- 1 file changed, 20 insertions(+), 19 deletions(-) diff --git a/disas/riscv.c b/disas/riscv.c index 3c17501..4580308 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -2769,25 +2769,6 @@ static void format_inst(char *buf, size_t buflen, si= ze_t tab, rv_decode *dec) char tmp[64]; const char *fmt; =20 - if (dec->op =3D=3D rv_op_illegal) { - size_t len =3D inst_length(dec->inst); - switch (len) { - case 2: - snprintf(buf, buflen, "(0x%04" PRIx64 ")", dec->inst); - break; - case 4: - snprintf(buf, buflen, "(0x%08" PRIx64 ")", dec->inst); - break; - case 6: - snprintf(buf, buflen, "(0x%012" PRIx64 ")", dec->inst); - break; - default: - snprintf(buf, buflen, "(0x%016" PRIx64 ")", dec->inst); - break; - } - return; - } - fmt =3D opcode_data[dec->op].format; while (*fmt) { switch (*fmt) { @@ -3004,6 +2985,11 @@ disasm_inst(char *buf, size_t buflen, rv_isa isa, ui= nt64_t pc, rv_inst inst) format_inst(buf, buflen, 16, &dec); } =20 +#define INST_FMT_2 "%04" PRIx64 " " +#define INST_FMT_4 "%08" PRIx64 " " +#define INST_FMT_6 "%012" PRIx64 " " +#define INST_FMT_8 "%016" PRIx64 " " + static int print_insn_riscv(bfd_vma memaddr, struct disassemble_info *info, rv_isa is= a) { @@ -3031,6 +3017,21 @@ print_insn_riscv(bfd_vma memaddr, struct disassemble= _info *info, rv_isa isa) } } =20 + switch (len) { + case 2: + (*info->fprintf_func)(info->stream, INST_FMT_2, inst); + break; + case 4: + (*info->fprintf_func)(info->stream, INST_FMT_4, inst); + break; + case 6: + (*info->fprintf_func)(info->stream, INST_FMT_6, inst); + break; + default: + (*info->fprintf_func)(info->stream, INST_FMT_8, inst); + break; + } + disasm_inst(buf, sizeof(buf), isa, memaddr, inst); (*info->fprintf_func)(info->stream, "%s", buf); =20 --=20 2.7.0 From nobody Sun Feb 8 16:34:30 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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X-Received-From: 2607:f8b0:400e:c01::241 Subject: [Qemu-devel] [PATCH v4 10/26] RISC-V: Hold rcu_read_lock when accessing memory X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@groups.riscv.org, Michael Clark , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From reading other code that accesses memory regions directly, it appears that the rcu_read_lock needs to be held. Note: the original code for accessing RAM directly was added because there is no other way to use atomic_cmpxchg on guest physical address space. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt --- target/riscv/helper.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/target/riscv/helper.c b/target/riscv/helper.c index 02cbcea..d148bed 100644 --- a/target/riscv/helper.c +++ b/target/riscv/helper.c @@ -209,6 +209,9 @@ restart: as the PTE is no longer valid */ MemoryRegion *mr; hwaddr l =3D sizeof(target_ulong), addr1; + enum { success, translate_fail, restart_walk} action =3D s= uccess; + + rcu_read_lock(); mr =3D address_space_translate(cs->as, pte_addr, &addr1, &l, false); if (memory_access_is_direct(mr, true)) { @@ -222,7 +225,7 @@ restart: target_ulong old_pte =3D atomic_cmpxchg(pte_pa, pte, updated_pte); if (old_pte !=3D pte) { - goto restart; + action =3D restart_walk; } else { pte =3D updated_pte; } @@ -230,7 +233,17 @@ restart: } else { /* misconfigured PTE in ROM (AD bits are not preset) or * PTE is in IO space and can't be updated atomically = */ + action =3D translate_fail; + } + rcu_read_unlock(); + + switch (action) { + case success: + break; + case translate_fail: return TRANSLATE_FAIL; + case restart_walk: + goto restart; } } =20 --=20 2.7.0 From nobody Sun Feb 8 16:34:30 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1521495004417722.3208484176264; Mon, 19 Mar 2018 14:30:04 -0700 (PDT) Received: from localhost ([::1]:44028 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ey2Lz-0001sk-Eo for importer@patchew.org; Mon, 19 Mar 2018 17:30:03 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33243) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ey2C9-0001Ng-N7 for qemu-devel@nongnu.org; Mon, 19 Mar 2018 17:19:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ey2C8-0002ez-74 for qemu-devel@nongnu.org; Mon, 19 Mar 2018 17:19:53 -0400 Received: from mail-pg0-x241.google.com ([2607:f8b0:400e:c05::241]:41568) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ey2C7-0002eA-SM for qemu-devel@nongnu.org; Mon, 19 Mar 2018 17:19:52 -0400 Received: by mail-pg0-x241.google.com with SMTP id m24so1750449pgv.8 for ; Mon, 19 Mar 2018 14:19:51 -0700 (PDT) Received: from monty.com ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id i127sm120500pfc.136.2018.03.19.14.19.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 19 Mar 2018 14:19:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=d+r4xPkbAJrkiFVFuCCGsm8x868xSaeLvaLnPtnLoW8=; b=Aihcn3aR0VMP3CAv1LVnuHN1fey590vSZHFcewVvql8r+zqS6S0r8nQ86Yf58PutSy bYIgzLglC0EqOm6gsLmWYsrQk5jRWgZSurbFJWmeJVrQXOSnbbBnPT+8wxzdeFox/iBo ZRxjWHU8q2kkZLgn9Mzljm8z3yZXBA+vGcIk3du2m3QWca+b35bxQIAUNcCskpFxacHM Z2fe7Yrk92ElkAAMhZ7KZW0FUFP1q+86WKkZoI0hqIqI4UH2ajXC7qajqGcw+kT3qZhV CWQRXIC15w3DSVsFgRHwSeCZsp9Gx9MUSTm/SVlNXdZ4aIm8b+b04tklr45jkPsxYwmA oFQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=d+r4xPkbAJrkiFVFuCCGsm8x868xSaeLvaLnPtnLoW8=; b=NQhjxlw9OMlfI7V1EG3ZygU3Q64JEkoryRtgDUqxyuRycjm1r0jxJmGd6szFDjhDo0 WjQc9FzFCqL1Xdwc1Lvs/Zxed0yUSghlZt+AoE332RznJ6tv2pTjexFtLYVC1nQol1Tu 5U9c1NZWNA7xREwkPBn9jhXBffGOGjWgmCcVZYbxgo3QxIF/5ttqlnwAJ9RWPOAbG0up 6YXZM3KqxV1ZNnUPruIwaCNW3UtgOIv/etX+Wn3iNHSi/e0HNQkUWIAjDBv4TNNQK3Gr whgBFMJv5nwjv+v4Qz/vKqMXUacacOo2t7/GWX6PFRinVKcZqBq8SqhjhuOQnd5GoVi7 WzHA== X-Gm-Message-State: AElRT7GNheqazbJev+/XRkcyyYNR4Px4v0NS0Uu6eEhtXVw1TrDIzG0y GxnmWdpMYsGFp9Wsk9gXr2JcI34HjEg= X-Google-Smtp-Source: AG47ELtPWbVDKBfPyPAwiX760Kl64f+4JWdz6GigMjLX5to/N/dANvTiCqSbAewxBci/xmZMUN5gCw== X-Received: by 10.99.150.2 with SMTP id c2mr10270017pge.352.1521494390580; Mon, 19 Mar 2018 14:19:50 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Mon, 19 Mar 2018 14:18:34 -0700 Message-Id: <1521494329-19546-12-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1521494329-19546-1-git-send-email-mjc@sifive.com> References: <1521494329-19546-1-git-send-email-mjc@sifive.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PATCH v4 11/26] RISC-V: Improve page table walker spec compliance X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@groups.riscv.org, Michael Clark , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" - Inline PTE_TABLE check for better readability - Improve readibility of User page U mode and SUM test - Disallow non U mode from fetching from User pages - Add reserved PTE flag check: W or W|X - Add misaligned PPN check - Set READ flag for PTE X flag if mstatus.mxr is in effect - Change access checks from ternary operator to if statements - Improves page walker comments - No measurable performance impact on dd test Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt --- target/riscv/cpu_bits.h | 2 -- target/riscv/helper.c | 59 ++++++++++++++++++++++++++++++++++-----------= ---- 2 files changed, 41 insertions(+), 20 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 64aa097..12b4757 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -407,5 +407,3 @@ #define PTE_SOFT 0x300 /* Reserved for Software */ =20 #define PTE_PPN_SHIFT 10 - -#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) =3D=3D P= TE_V) diff --git a/target/riscv/helper.c b/target/riscv/helper.c index d148bed..c68826b 100644 --- a/target/riscv/helper.c +++ b/target/riscv/helper.c @@ -185,16 +185,36 @@ restart: #endif target_ulong ppn =3D pte >> PTE_PPN_SHIFT; =20 - if (PTE_TABLE(pte)) { /* next level of page table */ + if (!(pte & PTE_V)) { + /* Invalid PTE */ + return TRANSLATE_FAIL; + } else if (!(pte & (PTE_R | PTE_W | PTE_X))) { + /* Inner PTE, continue walking */ base =3D ppn << PGSHIFT; - } else if ((pte & PTE_U) ? (mode =3D=3D PRV_S) && !sum : !(mode = =3D=3D PRV_S)) { - break; - } else if (!(pte & PTE_V) || (!(pte & PTE_R) && (pte & PTE_W))) { - break; - } else if (access_type =3D=3D MMU_INST_FETCH ? !(pte & PTE_X) : - access_type =3D=3D MMU_DATA_LOAD ? !(pte & PTE_R) && - !(mxr && (pte & PTE_X)) : !((pte & PTE_R) && (pte & PTE_= W))) { - break; + } else if ((pte & (PTE_R | PTE_W | PTE_X)) =3D=3D PTE_W) { + /* Reserved leaf PTE flags: PTE_W */ + return TRANSLATE_FAIL; + } else if ((pte & (PTE_R | PTE_W | PTE_X)) =3D=3D (PTE_W | PTE_X))= { + /* Reserved leaf PTE flags: PTE_W + PTE_X */ + return TRANSLATE_FAIL; + } else if ((pte & PTE_U) && ((mode !=3D PRV_U) && + (!sum || access_type =3D=3D MMU_INST_FETCH))) { + /* User PTE flags when not U mode and mstatus.SUM is not set, + or the access type is an instruction fetch */ + return TRANSLATE_FAIL; + } else if (ppn & ((1ULL << ptshift) - 1)) { + /* Misasligned PPN */ + return TRANSLATE_FAIL; + } else if (access_type =3D=3D MMU_DATA_LOAD && !((pte & PTE_R) || + ((pte & PTE_X) && mxr))) { + /* Read access check failed */ + return TRANSLATE_FAIL; + } else if (access_type =3D=3D MMU_DATA_STORE && !(pte & PTE_W)) { + /* Write access check failed */ + return TRANSLATE_FAIL; + } else if (access_type =3D=3D MMU_INST_FETCH && !(pte & PTE_X)) { + /* Fetch access check failed */ + return TRANSLATE_FAIL; } else { /* if necessary, set accessed and dirty bits. */ target_ulong updated_pte =3D pte | PTE_A | @@ -202,11 +222,14 @@ restart: =20 /* Page table updates need to be atomic with MTTCG enabled */ if (updated_pte !=3D pte) { - /* if accessed or dirty bits need updating, and the PTE is - * in RAM, then we do so atomically with a compare and swa= p. - * if the PTE is in IO space, then it can't be updated. - * if the PTE changed, then we must re-walk the page table - as the PTE is no longer valid */ + /* + * - if accessed or dirty bits need updating, and the PTE = is + * in RAM, then we do so atomically with a compare and s= wap. + * - if the PTE is in IO space or ROM, then it can't be up= dated + * and we return TRANSLATE_FAIL. + * - if the PTE changed by the time we went to update it, = then + * it is no longer valid and we must re-walk the page ta= ble. + */ MemoryRegion *mr; hwaddr l =3D sizeof(target_ulong), addr1; enum { success, translate_fail, restart_walk} action =3D s= uccess; @@ -252,15 +275,15 @@ restart: target_ulong vpn =3D addr >> PGSHIFT; *physical =3D (ppn | (vpn & ((1L << ptshift) - 1))) << PGSHIFT; =20 - if ((pte & PTE_R)) { + /* set permissions on the TLB entry */ + if ((pte & PTE_R) || (mode !=3D PRV_U && (pte & PTE_X) && mxr)= ) { *prot |=3D PAGE_READ; } if ((pte & PTE_X)) { *prot |=3D PAGE_EXEC; } - /* only add write permission on stores or if the page - is already dirty, so that we don't miss further - page table walks to update the dirty bit */ + /* add write permission on stores or if the page is already di= rty, + so that we TLB miss on later writes to update the dirty bit= */ if ((pte & PTE_W) && (access_type =3D=3D MMU_DATA_STORE || (pte & PTE_D))) { *prot |=3D PAGE_WRITE; --=20 2.7.0 From nobody Sun Feb 8 16:34:30 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [PATCH v4 12/26] RISC-V: Update E order and I extension order X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@groups.riscv.org, Michael Clark , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Section 22.8 Subset Naming Convention of the RISC-V ISA Specification defines the canonical order for extensions in the ISA string. It is silent on the position of the E extension however E is a substitute for I so it must come early in the extension list order. A comment is added to state E and I are mutually exclusive, as the E extension will be added to the RISC-V port in the future. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt --- target/riscv/cpu.c | 2 +- target/riscv/cpu.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 4851890..d2ae56a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -26,7 +26,7 @@ =20 /* RISC-V CPU definitions */ =20 -static const char riscv_exts[26] =3D "IMAFDQECLBJTPVNSUHKORWXYZG"; +static const char riscv_exts[26] =3D "IEMAFDQCLBJTPVNSUHKORWXYZG"; =20 const char * const riscv_int_regnames[] =3D { "zero", "ra ", "sp ", "gp ", "tp ", "t0 ", "t1 ", "t2 ", diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index cff02a2..3a0ca2f 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -71,6 +71,7 @@ #define RV(x) ((target_ulong)1 << (x - 'A')) =20 #define RVI RV('I') +#define RVE RV('E') /* E and I are mutually exclusive */ #define RVM RV('M') #define RVA RV('A') #define RVF RV('F') --=20 2.7.0 From nobody Sun Feb 8 16:34:30 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1521495007011290.8916176168277; Mon, 19 Mar 2018 14:30:07 -0700 (PDT) Received: from localhost ([::1]:44030 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ey2M1-0001wG-VT for importer@patchew.org; Mon, 19 Mar 2018 17:30:06 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33268) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ey2CA-0001P0-Ry for qemu-devel@nongnu.org; Mon, 19 Mar 2018 17:19:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ey2C9-0002gL-Oa for qemu-devel@nongnu.org; Mon, 19 Mar 2018 17:19:54 -0400 Received: from mail-pg0-x242.google.com ([2607:f8b0:400e:c05::242]:43727) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ey2C9-0002fk-Ic for qemu-devel@nongnu.org; Mon, 19 Mar 2018 17:19:53 -0400 Received: by mail-pg0-x242.google.com with SMTP id i9so1324393pgq.10 for ; Mon, 19 Mar 2018 14:19:53 -0700 (PDT) Received: from monty.com ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id i127sm120500pfc.136.2018.03.19.14.19.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 19 Mar 2018 14:19:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BzoWDjqOkLr1gXTgXEqkRe19OYL1d4M1Ffyez2Cfl2s=; b=k60vjQ9b7Q6mqe7eckCKXSZxX5PFYLkzTK+y+8IPcyxO93fPaGTYukIugn7jqyJQsE vGyA97nlw1v5LBGrfzYMbsebbQEkJrqF1C6vgNcmcuSv3XZ1440Y58c6eTz92RFndyXz lKX0PZEPJZGCOibsqaxnCKHj1/Q/faX2EoLZMS2XbH6LaIaytEzZqOyQFJ4u2B8sMET9 RftMMaFbfFl9M20MmHodv+uNrkBBxukz2CfrM+asbkJFqZHsEPO1+TLa0CMMNOmwN3mP rqS+s8PBRgOVJtRtw6RvPEx2fInSHROndes+dwVutXHJtr+weXcbHaCYZHgjjldpUlmF qDBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BzoWDjqOkLr1gXTgXEqkRe19OYL1d4M1Ffyez2Cfl2s=; b=E+LeLc9HGeFPZuQuEpQyKLKzGooo878mKRwBeCXv5uFOyooNwpE5iOtqk1JJLnUwXa 4vOKl5qeQJh1mNq9ZotSLowPfiAa5qTME5NpC31C/ZIB7rDZ4tyfAmjjdULDWySiCJ/T gRZl09ndMpquXVBpF5kCwwguf5HDRTzoUT/QRXzfKE0WMvqZh0LThPp8KmQnnWUQTTuK qji6d6kNkrMUqatljosZNx/cXM26ZJFPuSNU5ctsCF1Xvudq8ce0y55dli/iuL69mil6 QolQd7PK5XeFgdlMPtC3juYmRPuOj6MrgimSia9CigulphKXWVYhEvWZgKhYw2zxa2SS LZSA== X-Gm-Message-State: AElRT7E2yejt6cfyKW3RPazdDCrxrLTllAQ/v7SDWEnz0hoFuT7+SgHq 8akWWW3TcKE2vITXZs745OcPGuB22Oc= X-Google-Smtp-Source: AG47ELtlfd9ZS03s7Z2QMj8xlEvKUb4xz5DpkeUjywv00lD7Wu+txt0SYtGQN+suyJB0DE1CobZYpQ== X-Received: by 10.101.87.201 with SMTP id q9mr10338981pgr.215.1521494392558; Mon, 19 Mar 2018 14:19:52 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Mon, 19 Mar 2018 14:18:36 -0700 Message-Id: <1521494329-19546-14-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1521494329-19546-1-git-send-email-mjc@sifive.com> References: <1521494329-19546-1-git-send-email-mjc@sifive.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH v4 13/26] RISC-V: Make some header guards more specific X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@groups.riscv.org, Michael Clark , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/riscv/spike.h | 4 ++-- include/hw/riscv/virt.h | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/include/hw/riscv/spike.h b/include/hw/riscv/spike.h index 8410430..641b70d 100644 --- a/include/hw/riscv/spike.h +++ b/include/hw/riscv/spike.h @@ -16,8 +16,8 @@ * this program. If not, see . */ =20 -#ifndef HW_SPIKE_H -#define HW_SPIKE_H +#ifndef HW_RISCV_SPIKE_H +#define HW_RISCV_SPIKE_H =20 typedef struct { /*< private >*/ diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index b91a412..3a4f23e 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -16,8 +16,8 @@ * this program. If not, see . */ =20 -#ifndef HW_VIRT_H -#define HW_VIRT_H +#ifndef HW_RISCV_VIRT_H +#define HW_RISCV_VIRT_H =20 typedef struct { /*< private >*/ --=20 2.7.0 From nobody Sun Feb 8 16:34:30 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1521494692459227.23249798809002; Mon, 19 Mar 2018 14:24:52 -0700 (PDT) Received: from localhost ([::1]:43997 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ey2Gx-0005Ka-K7 for importer@patchew.org; Mon, 19 Mar 2018 17:24:51 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33281) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ey2CB-0001Pk-Ha for qemu-devel@nongnu.org; Mon, 19 Mar 2018 17:19:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ey2CA-0002gx-Lu for qemu-devel@nongnu.org; Mon, 19 Mar 2018 17:19:55 -0400 Received: from mail-pf0-x241.google.com ([2607:f8b0:400e:c00::241]:46093) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ey2CA-0002gc-GW for qemu-devel@nongnu.org; Mon, 19 Mar 2018 17:19:54 -0400 Received: by mail-pf0-x241.google.com with SMTP id z10so7541937pfh.13 for ; Mon, 19 Mar 2018 14:19:54 -0700 (PDT) Received: from monty.com ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id i127sm120500pfc.136.2018.03.19.14.19.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 19 Mar 2018 14:19:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=TFCFcsCRDnpWhlR6rxqM+6PUN3Eyxuzs8Kg/VUBrDgg=; b=USQhkawzx0EKJ5B7MngDcTl6pwz0fGRvN28aoH9j0mE2In5x9V/KZJLYmZ4v7DAvJ3 FLJP9NsBPTSwZuOg0BDKU5l7+304UBpu5WGDPvSmLZY9D0aRkFa+4zkOxPCQjr7Q58ef iRdFRxnJk2Ru/T0YYpm6bwng0tI++DfLNaB18OxSpSRmnuoKJq7k3CAXYdPaEgo5EsDe RXsBLU1UOOfLrwL4eAg3vVum0LcygKTSM7Yxjm8fJZ5xggOEylbdGtjvbxHVzf0pJyRm JSkeebNcPVsVNmmoxT40hzFkeIcd0F6qTypupkOwPop8JwOvJ0O4z1HBuX0zaD0PrX+4 xA1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TFCFcsCRDnpWhlR6rxqM+6PUN3Eyxuzs8Kg/VUBrDgg=; b=DOZ6Q5t9qrBatJe1kSXdczfr1McWGj+gnT8YJq7F3KSwciqCityHHU5+NwHeZZlMk8 FjhsPzlh5uX5j49lacLE1QJn+si4ntyx3SijeHmRdoc9lqtuYlT+RQO10TkJZx06EnZx UecaPnP7Pg0dqa2OlhIB/UtABTbLDaUOvWQhfjFvb0YIgxyj5AUbksXEhZV8QNRA3dBu NwnPVHBdkH4yjKb1ZNwKNBbOkt8wgxEDFC7jI2v04m9ErRRYILOw3rlYB7FUxkyJBdQu X+7OXac4/myv1f6wLY519m9tt5a+HiCOnzaZo4K/5cvgD4sBqgJ+xxzdQVPLAkDdiGmA qPkg== X-Gm-Message-State: AElRT7HLof5sRZmtsFLdd/rXNYPiB7GV3mWin5pLLQB8uGtsEtZnrrtm TlnPWxxwE47kIekM3rcgCoGYCvdrilE= X-Google-Smtp-Source: AG47ELv9ZB5DUltm6Nsh3dzFC8YAfFnqgej5wFY3iMu448I3xxxBoTTyhWogReJEATp/tUV6u3gIuA== X-Received: by 10.167.131.199 with SMTP id j7mr11293070pfn.99.1521494393588; Mon, 19 Mar 2018 14:19:53 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Mon, 19 Mar 2018 14:18:37 -0700 Message-Id: <1521494329-19546-15-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1521494329-19546-1-git-send-email-mjc@sifive.com> References: <1521494329-19546-1-git-send-email-mjc@sifive.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::241 Subject: [Qemu-devel] [PATCH v4 14/26] RISC-V: Make virt header comment title consistent X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@groups.riscv.org, Michael Clark , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/riscv/virt.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index 3a4f23e..91163d6 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -1,5 +1,5 @@ /* - * SiFive VirtIO Board + * QEMU RISC-V VirtIO machine interface * * Copyright (c) 2017 SiFive, Inc. * --=20 2.7.0 From nobody Sun Feb 8 16:34:30 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1521495192967277.63817235625913; Mon, 19 Mar 2018 14:33:12 -0700 (PDT) Received: from localhost ([::1]:44051 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ey2Os-0004Mb-Oi for importer@patchew.org; Mon, 19 Mar 2018 17:33:02 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33302) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ey2CC-0001Qq-Av for qemu-devel@nongnu.org; Mon, 19 Mar 2018 17:19:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ey2CB-0002he-HF for qemu-devel@nongnu.org; Mon, 19 Mar 2018 17:19:56 -0400 Received: from mail-pg0-x243.google.com ([2607:f8b0:400e:c05::243]:40252) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ey2CB-0002hH-BN for qemu-devel@nongnu.org; Mon, 19 Mar 2018 17:19:55 -0400 Received: by mail-pg0-x243.google.com with SMTP id g8so7423106pgv.7 for ; Mon, 19 Mar 2018 14:19:55 -0700 (PDT) Received: from monty.com ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id i127sm120500pfc.136.2018.03.19.14.19.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 19 Mar 2018 14:19:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=w9WsqLi+36GH5HBFoHBihcbZkY4SSijk4a3jyX/eVfA=; b=jiVp0G0ArYGyeYkvPeGBIVEA1BQ1cOz04B4USN7VqWsUeMJQRV9egeIEIKiO5PfuW8 9UxiHHRGC2aa7cKSSFr1AqL4xpDzD5pP7zCpjbRs2QZ0GpWTaoQlKvqFUzyBRwsy7+Zc LmYMvZCTg5Ym4LSFB30CfwHjPtciZupLEe9rkW7NQ7fshZoUtOS/6qPl3ZNsjLMgDpvD IV5G8nbknMcj3FmGmK+vr5PRnu+P2pGGFkgaFMdD0yo9+OUfgPBeXOq/bFE703ZQ9E0W j9c+k12YbjHUb0qNPg15cM36qfkn7tthb+wUvpQ5lORlj6s875q/+BWY6V0UOIPhtSux Olmw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=w9WsqLi+36GH5HBFoHBihcbZkY4SSijk4a3jyX/eVfA=; b=ULPS17ir6QuUaij37lwfuCIqZrIlavNEr3rbtdGHhJ9FPZsNaRzN/ob7p+N/nAXRep IF6zx07rjHLacgFfLq/pTCCY5g9Zep6nHtnHKEGOL4QB77nLTVZyVcbYbaFY4TVQW34H wQiqRCbumgbRxr54253sdxRSvYKapCKMZmHJSo/LLfaSboALU43FJ3EKVDik393VX6sM 5TA8ykVPtYAjFd9qgm3hEnc3UvgmwmmLbuM+pCY1exIPlW3rW1Wm2AXgx5oUdrdDzsxg riYmLKr8Rl4/dBfRPNdY4gkfA83Aoth6L+oWBdO2sHWxMliphuXR6BlSAjCEBUnjb8gd uMRA== X-Gm-Message-State: AElRT7ERrVhYxn3ILWYmxFloDaxLIV2j7dcZ3YtC8+olh1n1ZPrZ+NP2 ajcHHbGbUFimxe6WLDSuN84IWVgWAmw= X-Google-Smtp-Source: AG47ELupQGNAWugbCqGCgz8+EnjwwaK4dCP7E6JFajjoIYdMmNey4PV0frUWlOE1qahOtOmu9c20Gw== X-Received: by 10.99.127.92 with SMTP id p28mr10378484pgn.305.1521494394412; Mon, 19 Mar 2018 14:19:54 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Mon, 19 Mar 2018 14:18:38 -0700 Message-Id: <1521494329-19546-16-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1521494329-19546-1-git-send-email-mjc@sifive.com> References: <1521494329-19546-1-git-send-email-mjc@sifive.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PATCH v4 15/26] RISC-V: Use memory_region_is_ram in pte update X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@groups.riscv.org, Michael Clark , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" After reading cpu_physical_memory_write and friends, it seems that memory_region_is_ram is a more appropriate interface, and matches the intent of the code that is calling it. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt --- target/riscv/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/helper.c b/target/riscv/helper.c index c68826b..cfbf1d1 100644 --- a/target/riscv/helper.c +++ b/target/riscv/helper.c @@ -237,7 +237,7 @@ restart: rcu_read_lock(); mr =3D address_space_translate(cs->as, pte_addr, &addr1, &l, false); - if (memory_access_is_direct(mr, true)) { + if (memory_region_is_ram(mr)) { target_ulong *pte_pa =3D qemu_map_ram_ptr(mr->ram_block, addr1); #if TCG_OVERSIZED_GUEST --=20 2.7.0 From nobody Sun Feb 8 16:34:30 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1521494855577549.3527101570716; Mon, 19 Mar 2018 14:27:35 -0700 (PDT) Received: from localhost ([::1]:44016 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ey2JU-0007nK-7U for importer@patchew.org; Mon, 19 Mar 2018 17:27:28 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33316) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ey2CD-0001SP-O4 for qemu-devel@nongnu.org; Mon, 19 Mar 2018 17:20:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ey2CC-0002iH-C1 for qemu-devel@nongnu.org; Mon, 19 Mar 2018 17:19:57 -0400 Received: from mail-pf0-x243.google.com ([2607:f8b0:400e:c00::243]:45126) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ey2CC-0002hr-76 for qemu-devel@nongnu.org; Mon, 19 Mar 2018 17:19:56 -0400 Received: by mail-pf0-x243.google.com with SMTP id l27so3030804pfk.12 for ; Mon, 19 Mar 2018 14:19:56 -0700 (PDT) Received: from monty.com ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id i127sm120500pfc.136.2018.03.19.14.19.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 19 Mar 2018 14:19:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JjGyplqqVlE4UQ9tNmqboa5lGCOAOgUeBOIRDmEp87s=; b=Ymnwap0L7OFjuUGBNuk5Eh7+6cSDJh2s/GQIE6qrFVgoB8G90t9Vvjj2azg6nvYpb+ Fp+ZnKSRTJJxPUbFBaZSnac1Y4nBmXalh3ZMmlxxzfnnAeBw1wGuV7tumDR/0S/gsgiS MQEpMIOevAKBfvJ2w4U7263IKU7hXIVhO109BbiDgPmPSA+L+WvyA49xV2+F0XOZhHkg 9iCHRUPpYYKP8NaztfFQehvnwHqbSzeUDRRLnJ66bButRuDesHTcJImFWa8i2qcr8CPr JpqDXrcWTOuDdWCSlHds9U5NsbtEp3K3sSp5kgDnBXSNWI0O3pc+mhLZcMsRvRFpIMeI tY7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JjGyplqqVlE4UQ9tNmqboa5lGCOAOgUeBOIRDmEp87s=; b=QLbb84JMJCUCDvk5Yh84WqJXNTbJgSLfK2OW8JHHuSvfY64inrYeNiGG63grzA93iE YeUXjrtOz13PJx28sQgU3KgsxY2Tr5DcttPE2OaOBRcObWW4Yavl07Exn+UtcHORhVdT 2lIQfW27YP80itpCZP2KPaKH5rqh3D3mHJdY7XdXxrYGU8kKJ3LmlET6brq2bQ9ImOGk EEwn4KosNploLrIT9f42BTpg89yqEayvUyuT2UxZLk0agqipjR0Q70rOXrov6Huf5/Lx GYYsvRKX8Slm6ClZukUKsUx2UdqQ0PxNJMHFsAhN5eMZ7t+UrD/zpkVUOz0jMwwy6COe XfzQ== X-Gm-Message-State: AElRT7GXzvvKpVeZS7pepof33RWLtsOT2QUxt2mxsK/i6Das3+FDIkbd MJ30QgejddRUz+CsVt/ajdoriMlcA54= X-Google-Smtp-Source: AG47ELv5IUZqQ1WbTupUWTGI8AJgzH1u8lPdzj30z7JezSMCeMUncwTmG+svHlkAr3A8QnWlhZFFLA== X-Received: by 10.99.186.72 with SMTP id l8mr10420116pgu.410.1521494395249; Mon, 19 Mar 2018 14:19:55 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Mon, 19 Mar 2018 14:18:39 -0700 Message-Id: <1521494329-19546-17-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1521494329-19546-1-git-send-email-mjc@sifive.com> References: <1521494329-19546-1-git-send-email-mjc@sifive.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [PATCH v4 16/26] RISC-V: Remove EM_RISCV ELF_MACHINE indirection X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@groups.riscv.org, Michael Clark , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Pointless indirection. Other ports use EM_ constants directly. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/riscv/sifive_e.c | 2 +- hw/riscv/sifive_u.c | 2 +- hw/riscv/spike.c | 2 +- hw/riscv/virt.c | 2 +- target/riscv/cpu.h | 1 - 5 files changed, 4 insertions(+), 5 deletions(-) diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 4872b68..39e4cb4 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -88,7 +88,7 @@ static uint64_t load_kernel(const char *kernel_filename) =20 if (load_elf(kernel_filename, NULL, NULL, &kernel_entry, NULL, &kernel_high, - 0, ELF_MACHINE, 1, 0) < 0) { + 0, EM_RISCV, 1, 0) < 0) { error_report("qemu: could not load kernel '%s'", kernel_filename); exit(1); } diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 57b4f4f..0e633a0 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -74,7 +74,7 @@ static uint64_t load_kernel(const char *kernel_filename) =20 if (load_elf(kernel_filename, NULL, NULL, &kernel_entry, NULL, &kernel_high, - 0, ELF_MACHINE, 1, 0) < 0) { + 0, EM_RISCV, 1, 0) < 0) { error_report("qemu: could not load kernel '%s'", kernel_filename); exit(1); } diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index c7d937b..70e697c 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -64,7 +64,7 @@ static uint64_t load_kernel(const char *kernel_filename) uint64_t kernel_entry, kernel_high; =20 if (load_elf_ram_sym(kernel_filename, NULL, NULL, - &kernel_entry, NULL, &kernel_high, 0, ELF_MACHINE, 1, 0, + &kernel_entry, NULL, &kernel_high, 0, EM_RISCV, 1, 0, NULL, true, htif_symbol_callback) < 0) { error_report("qemu: could not load kernel '%s'", kernel_filename); exit(1); diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index d680cbd..e3f8bb7 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -68,7 +68,7 @@ static uint64_t load_kernel(const char *kernel_filename) =20 if (load_elf(kernel_filename, NULL, NULL, &kernel_entry, NULL, &kernel_high, - 0, ELF_MACHINE, 1, 0) < 0) { + 0, EM_RISCV, 1, 0) < 0) { error_report("qemu: could not load kernel '%s'", kernel_filename); exit(1); } diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 3a0ca2f..7c4482b 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -34,7 +34,6 @@ =20 #define TCG_GUEST_DEFAULT_MO 0 =20 -#define ELF_MACHINE EM_RISCV #define CPUArchState struct CPURISCVState =20 #include "qemu-common.h" --=20 2.7.0 From nobody Sun Feb 8 16:34:30 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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Mon, 19 Mar 2018 17:19:57 -0400 Received: by mail-pg0-x243.google.com with SMTP id i9so1324506pgq.10 for ; Mon, 19 Mar 2018 14:19:56 -0700 (PDT) Received: from monty.com ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id i127sm120500pfc.136.2018.03.19.14.19.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 19 Mar 2018 14:19:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=skhNLehqLx7INkCfB7WkgTioVOYa2VI4KQLj/TiEtYM=; b=UA76l2jpaMaH69Y9df7gfWBFW64d59OIaBqkFvjxH8Di4oVEDP14pC/lBgxJvaloBc MZnFTzWugKswEDPKG3VSEuXZJ0gurFE2Ijjyb1ciIRNC051mPVKWd7Zxli38RW1qhoPY eSEFuk69Kxfq6dm1OCMfFdQC8VZVQKiEYJAwCEgaLIAGKtcAuyZfqrFHioiMfl9quX99 5Ghceb161+Jz91iTw/cU8muNLafyTq4o0UM8JJH0GrF3zg6cABn1gbFaWavSrnPtu1KZ jlXmJ6PmPmjO7priOpuQze9kYbAKuT4QmOMUjcPr6C0bH+Mo4Y5oJ1zNq3k9mtPb1M8z NJEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; 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X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PATCH v4 17/26] RISC-V: Hardwire satp to 0 for no-mmu case X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@groups.riscv.org, Michael Clark , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" satp is WARL so it should not trap on illegal writes, rather it can be hardwired to zero and silently ignore illegal writes. It seems the RISC-V WARL behaviour is preferred to having to trap overhead versus simply reading back the value and checking if the write took (saves hundreds of cycles and more complex trap handling code). Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt --- target/riscv/op_helper.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index e34715d..dd3e417 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -242,7 +242,7 @@ void csr_write_helper(CPURISCVState *env, target_ulong = val_to_write, } case CSR_SATP: /* CSR_SPTBR */ { if (!riscv_feature(env, RISCV_FEATURE_MMU)) { - goto do_illegal; + break; } if (env->priv_ver <=3D PRIV_VERSION_1_09_1 && (val_to_write ^ env-= >sptbr)) { @@ -452,7 +452,10 @@ target_ulong csr_read_helper(CPURISCVState *env, targe= t_ulong csrno) return env->scounteren; case CSR_SCAUSE: return env->scause; - case CSR_SPTBR: + case CSR_SATP: /* CSR_SPTBR */ + if (!riscv_feature(env, RISCV_FEATURE_MMU)) { + return 0; + } if (env->priv_ver >=3D PRIV_VERSION_1_10_0) { return env->satp; } else { --=20 2.7.0 From nobody Sun Feb 8 16:34:30 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1521495519210420.6479133614241; Mon, 19 Mar 2018 14:38:39 -0700 (PDT) Received: from localhost ([::1]:44084 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ey2UA-0000Nv-1T for importer@patchew.org; Mon, 19 Mar 2018 17:38:30 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33373) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ey2CI-0001Vf-7p for qemu-devel@nongnu.org; Mon, 19 Mar 2018 17:20:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ey2CE-0002jM-Bg for qemu-devel@nongnu.org; Mon, 19 Mar 2018 17:20:02 -0400 Received: from mail-pf0-x244.google.com ([2607:f8b0:400e:c00::244]:45127) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ey2CE-0002iy-3x for qemu-devel@nongnu.org; Mon, 19 Mar 2018 17:19:58 -0400 Received: by mail-pf0-x244.google.com with SMTP id l27so3030827pfk.12 for ; Mon, 19 Mar 2018 14:19:57 -0700 (PDT) Received: from monty.com ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id i127sm120500pfc.136.2018.03.19.14.19.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 19 Mar 2018 14:19:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UtDHM0IFsJP/nABkeJHaAyxMd9mnBAmwGcugxkD3tLA=; b=a5durCt/WW4k7QU+bFqo+AZ+CrtRJ/9NMppVX68UrzJY555CznTN7cMtq95uo5LsiA tmMiFzVCh1A6QteYdGy3+whPnihYxERyAnkPBgYv5mTH7eWW+sUOMmYWqsP+urwKM+WZ zaJSej9BBDCfIwUvSFcBuB0TlQJCz6fiMn/vAsAABPXga1N5M01xyUyk6NTQ6MuCyITD eM0vc3BFVfqianeLKTmTYJYGyFmzd49L+s+8j2Q0IWDZZcpXPdiXhmJKXcdNc5xYCXMu Dm2wfsLWpeMn7OwXPv1R8mPpHdipf2AeR88oju9v2rMj3rtsiPFuUkVcsBQVf2MgnDmE j0lQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UtDHM0IFsJP/nABkeJHaAyxMd9mnBAmwGcugxkD3tLA=; b=ajh4weIqbhsc2dW5+6ZDeZ9VpQyY5p+NdiFUWY3wYtfzKMwkFikSgnXFKUcs1GlbE2 wn7/UoIEZZn501nd+j4qEG/S0pjpsJ8NKAtuhaq3LghwQ3ewa8ftoWY9IhhWakfeyGGV LJ1Imvhy36bhereAPe4x5CfBg/RiqAVd0OYY3EKn1yPri21KRKa0ECJlqflNj0YptFha BNG0lrQ5IVHQ2fbxjsM5Hr8ltNEYlWPVlMoHjHsc6axcCxw51sHYFOMU0wQptxf4e2Z4 //k26ArZqGWAtj6IxG8UkQh5P5Ak4s5/S7GT2L61bZkvEfHD+ocCh2o/AmGBl6tJYNZJ bTvQ== X-Gm-Message-State: AElRT7HQgHhrmqOX9+EvSL2p8TqXpMrF14Tp7ySaCb6d6AuNbQr0JMSf ZfLnREErLdu/7RmCwDcobm/6bWNSTFw= X-Google-Smtp-Source: AG47ELsHZ9CsPNl3K+uHdwtTu3974U12C8oXW7ppI/huibAxqmcmTisEcJ1MqkT9bQf1tKmKo/RjKg== X-Received: by 10.99.107.6 with SMTP id g6mr10342518pgc.109.1521494396917; Mon, 19 Mar 2018 14:19:56 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Mon, 19 Mar 2018 14:18:41 -0700 Message-Id: <1521494329-19546-19-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1521494329-19546-1-git-send-email-mjc@sifive.com> References: <1521494329-19546-1-git-send-email-mjc@sifive.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PATCH v4 18/26] RISC-V: Remove braces from satp case statement X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@groups.riscv.org, Michael Clark , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/riscv/op_helper.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index dd3e417..f79716a 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -240,7 +240,7 @@ void csr_write_helper(CPURISCVState *env, target_ulong = val_to_write, csr_write_helper(env, next_mie, CSR_MIE); break; } - case CSR_SATP: /* CSR_SPTBR */ { + case CSR_SATP: /* CSR_SPTBR */ if (!riscv_feature(env, RISCV_FEATURE_MMU)) { break; } @@ -258,7 +258,6 @@ void csr_write_helper(CPURISCVState *env, target_ulong = val_to_write, env->satp =3D val_to_write; } break; - } case CSR_SEPC: env->sepc =3D val_to_write; break; --=20 2.7.0 From nobody Sun Feb 8 16:34:30 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1521495005894501.2476848269257; Mon, 19 Mar 2018 14:30:05 -0700 (PDT) Received: from localhost ([::1]:44029 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ey2M0-0001uT-Vb for importer@patchew.org; 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X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [PATCH v4 19/26] RISC-V: riscv-qemu port supports sv39 and sv48 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@groups.riscv.org, Michael Clark , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt --- target/riscv/cpu.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 7c4482b..f47fc9c 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -24,8 +24,8 @@ #define TARGET_PAGE_BITS 12 /* 4 KiB Pages */ #if defined(TARGET_RISCV64) #define TARGET_LONG_BITS 64 -#define TARGET_PHYS_ADDR_SPACE_BITS 50 -#define TARGET_VIRT_ADDR_SPACE_BITS 39 +#define TARGET_PHYS_ADDR_SPACE_BITS 52 +#define TARGET_VIRT_ADDR_SPACE_BITS 48 #elif defined(TARGET_RISCV32) #define TARGET_LONG_BITS 32 #define TARGET_PHYS_ADDR_SPACE_BITS 34 --=20 2.7.0 From nobody Sun Feb 8 16:34:30 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1521495669937338.58126952753855; Mon, 19 Mar 2018 14:41:09 -0700 (PDT) Received: from localhost ([::1]:44109 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ey2Wi-0002uk-QV for importer@patchew.org; Mon, 19 Mar 2018 17:41:08 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33374) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ey2CI-0001Vg-7o for qemu-devel@nongnu.org; Mon, 19 Mar 2018 17:20:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ey2CF-0002kj-Pk for qemu-devel@nongnu.org; Mon, 19 Mar 2018 17:20:02 -0400 Received: from mail-pf0-x244.google.com ([2607:f8b0:400e:c00::244]:36986) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ey2CF-0002kB-JF for qemu-devel@nongnu.org; Mon, 19 Mar 2018 17:19:59 -0400 Received: by mail-pf0-x244.google.com with SMTP id h11so7559028pfn.4 for ; Mon, 19 Mar 2018 14:19:59 -0700 (PDT) Received: from monty.com ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id i127sm120500pfc.136.2018.03.19.14.19.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 19 Mar 2018 14:19:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=t3lh++LxetnmSNNw07i/3UNn8XJU8Dt149LiPYmrn4o=; b=WZv05dJAc5zxetTiw9IGz1FNDn3TVloZvRlsgW5/oBwErjMFmIuB3SKoUrKUZbvkBd 5FXfWtmVqrM+OImoCeJOuwRw4470dk6B+8Th5TcpZDZ64NiOrgVUoNK92pOegBQhXeGF UPK8OGvtK1cR3BmG67yJVrGDWo68GGUNQEwvcpGmS8kADbqKPYaahNeIrxSRotlcKLsz nULXeviBOnDL+kucWCSRXp9P3m6Oy7ZnHauMkrqr/V4hAWfxWeuRKWCzVeVnLrFYxHZN HKA2Bsk0u+3eDXKMHgp1/SgoLfXKN/fMNUn20mKZgTWa56wEVEIR6WR5rJzQjYLHMWbL A8ew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=t3lh++LxetnmSNNw07i/3UNn8XJU8Dt149LiPYmrn4o=; b=TXEXti6iMZzc9CPeiPj80sc6s063Pgb2YzLdyerhCXApXiIWtWGtWYsHeebLz6uw8G UpNDSTW/OomvITvAf/ZjDLXC2YfXM5WRTOk8zrCcovhwBFBgjZ1rCZzoAHf8+iuVqzKk 1MyR4BKc2hsQ1Q+hwv+TO5bh3aJlHco1dOc59A2ZJ5fGcvAgYYUohAqn4kpIpYYU2h5S rERzB0gqp4pduk9cyK27ABoywvwFDVVtAqXFstYMICW462jFwxNNhgx54SAw772Y8fnE wWPdiRq5vXjcygSvUuXQ2j4ncS5uaaqq1nYmEOVzyGfAaR15fJVPkTQvtnH44inrb+BR ZVDg== X-Gm-Message-State: AElRT7HKUo2wIJj5fY/P/ULuFmuWcnACgtA0fGtogcQbNwd1rO/YOsHZ OOYaTIVj8y9q6pzOM+cghCdXSgRRCX4= X-Google-Smtp-Source: AG47ELvIA1sJgCR0tkZvUgiz0eIy6NPKGx69J3BOsTg115QzjeCn1SXeLEiLy7AU8KE8yUPtpV+wUg== X-Received: by 10.101.90.10 with SMTP id y10mr10179142pgs.34.1521494398710; Mon, 19 Mar 2018 14:19:58 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Mon, 19 Mar 2018 14:18:43 -0700 Message-Id: <1521494329-19546-21-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1521494329-19546-1-git-send-email-mjc@sifive.com> References: <1521494329-19546-1-git-send-email-mjc@sifive.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PATCH v4 20/26] RISC-V: vectored traps are optional X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@groups.riscv.org, Michael Clark , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Vectored traps for asynchrounous interrupts are optional. The mtvec/stvec mode field is WARL and hence does not trap if an illegal value is written. Illegal values are ignored. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt --- target/riscv/op_helper.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index f79716a..36b9e8e 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -262,11 +262,10 @@ void csr_write_helper(CPURISCVState *env, target_ulon= g val_to_write, env->sepc =3D val_to_write; break; case CSR_STVEC: - if (val_to_write & 1) { - qemu_log_mask(LOG_UNIMP, "CSR_STVEC: vectored traps not suppor= ted"); - goto do_illegal; + /* we do not support vectored traps for asynchrounous interrupts */ + if ((val_to_write & 3) =3D=3D 0) { + env->stvec =3D val_to_write >> 2 << 2; } - env->stvec =3D val_to_write >> 2 << 2; break; case CSR_SCOUNTEREN: env->scounteren =3D val_to_write; @@ -284,11 +283,10 @@ void csr_write_helper(CPURISCVState *env, target_ulon= g val_to_write, env->mepc =3D val_to_write; break; case CSR_MTVEC: - if (val_to_write & 1) { - qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: vectored traps not suppor= ted"); - goto do_illegal; + /* we do not support vectored traps for asynchrounous interrupts */ + if ((val_to_write & 3) =3D=3D 0) { + env->mtvec =3D val_to_write >> 2 << 2; } - env->mtvec =3D val_to_write >> 2 << 2; break; case CSR_MCOUNTEREN: env->mcounteren =3D val_to_write; --=20 2.7.0 From nobody Sun Feb 8 16:34:30 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1521495360466877.037208336785; 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Mon, 19 Mar 2018 14:19:59 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Mon, 19 Mar 2018 14:18:44 -0700 Message-Id: <1521494329-19546-22-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1521494329-19546-1-git-send-email-mjc@sifive.com> References: <1521494329-19546-1-git-send-email-mjc@sifive.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::242 Subject: [Qemu-devel] [PATCH v4 21/26] RISC-V: No traps on writes to misa, minstret, mcycle X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@groups.riscv.org, Michael Clark , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" These fields are marked WARL in the specification so illegal writes are silently dropped. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt --- target/riscv/op_helper.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 36b9e8e..ba3639d 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -200,17 +200,19 @@ void csr_write_helper(CPURISCVState *env, target_ulon= g val_to_write, break; } case CSR_MINSTRET: - qemu_log_mask(LOG_UNIMP, "CSR_MINSTRET: write not implemented"); - goto do_illegal; + /* minstret is WARL so unsupported writes are ignored */ + break; case CSR_MCYCLE: - qemu_log_mask(LOG_UNIMP, "CSR_MCYCLE: write not implemented"); - goto do_illegal; + /* mcycle is WARL so unsupported writes are ignored */ + break; +#if defined(TARGET_RISCV32) case CSR_MINSTRETH: - qemu_log_mask(LOG_UNIMP, "CSR_MINSTRETH: write not implemented"); - goto do_illegal; + /* minstreth is WARL so unsupported writes are ignored */ + break; case CSR_MCYCLEH: - qemu_log_mask(LOG_UNIMP, "CSR_MCYCLEH: write not implemented"); - goto do_illegal; + /* mcycleh is WARL so unsupported writes are ignored */ + break; +#endif case CSR_MUCOUNTEREN: env->mucounteren =3D val_to_write; break; @@ -300,10 +302,9 @@ void csr_write_helper(CPURISCVState *env, target_ulong= val_to_write, case CSR_MBADADDR: env->mbadaddr =3D val_to_write; break; - case CSR_MISA: { - qemu_log_mask(LOG_UNIMP, "CSR_MISA: misa writes not supported"); - goto do_illegal; - } + case CSR_MISA: + /* misa is WARL so unsupported writes are ignored */ + break; case CSR_PMPCFG0: case CSR_PMPCFG1: case CSR_PMPCFG2: @@ -328,7 +329,6 @@ void csr_write_helper(CPURISCVState *env, target_ulong = val_to_write, case CSR_PMPADDR15: pmpaddr_csr_write(env, csrno - CSR_PMPADDR0, val_to_write); break; - do_illegal: #endif default: do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); --=20 2.7.0 From nobody Sun Feb 8 16:34:30 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PATCH v4 22/26] RISC-V: Remove support for adhoc X_COP interrupt X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@groups.riscv.org, Michael Clark , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is essentially dead-code elimination. Support for more local interrupts will be added in a future revision, as they will be defined in a future version of the Privileged ISA specification. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt --- target/riscv/cpu_bits.h | 1 - target/riscv/op_helper.c | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 12b4757..133e070 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -346,7 +346,6 @@ #define IRQ_S_EXT 9 #define IRQ_H_EXT 10 /* until: priv-1.9.1 */ #define IRQ_M_EXT 11 /* until: priv-1.9.1 */ -#define IRQ_X_COP 12 /* non-standard */ =20 /* Default addresses */ #define DEFAULT_RSTVEC 0x00001000 diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index ba3639d..1fdde90 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -90,7 +90,7 @@ void csr_write_helper(CPURISCVState *env, target_ulong va= l_to_write, target_ulong csrno) { #ifndef CONFIG_USER_ONLY - uint64_t delegable_ints =3D MIP_SSIP | MIP_STIP | MIP_SEIP | (1 << IRQ= _X_COP); + uint64_t delegable_ints =3D MIP_SSIP | MIP_STIP | MIP_SEIP; uint64_t all_ints =3D delegable_ints | MIP_MSIP | MIP_MTIP; #endif =20 --=20 2.7.0 From nobody Sun Feb 8 16:34:30 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1521495192757280.6687307320341; Mon, 19 Mar 2018 14:33:12 -0700 (PDT) Received: from localhost ([::1]:44052 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ey2Os-0004N1-SP for importer@patchew.org; Mon, 19 Mar 2018 17:33:02 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33419) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ey2CK-0001Xu-AZ for qemu-devel@nongnu.org; Mon, 19 Mar 2018 17:20:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ey2CJ-0002nt-3E for qemu-devel@nongnu.org; Mon, 19 Mar 2018 17:20:04 -0400 Received: from mail-pl0-x242.google.com ([2607:f8b0:400e:c01::242]:44798) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ey2CI-0002nG-RI for qemu-devel@nongnu.org; Mon, 19 Mar 2018 17:20:03 -0400 Received: by mail-pl0-x242.google.com with SMTP id 9-v6so11041577ple.11 for ; Mon, 19 Mar 2018 14:20:02 -0700 (PDT) Received: from monty.com ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id i127sm120500pfc.136.2018.03.19.14.20.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 19 Mar 2018 14:20:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9TrMd4TF0lU50Lp53KGXfUEURaP7R+dxEXI3heuCE4U=; b=MQaeG/NtEyZxUaqhILH9bijFPhyRIXI4UbuAJu8FaF3uTcMceqef9aSmYSDkAiw0J2 E3USvewjD0D4LVRcVUx0Z3VhHK5kkFerkLPTTAqZ/2Jx6TNA7EJYzwtePb8GclPV1UkF sAAxoIJimYxKIxAoYi1xgBxh1q/Hdlg1FqrYUYFdEW/5JlI06wAc7aaNFBNGEq5xTF59 zBnaXtKTu3gbGFqusVWD8xy9aWNtoD5OUW+3W3gCCcvzs9q3lN7cDLk8dGrPbkfgpewP xbg7wYYy8a6u5fsq1oFvlvUnZP54X2LRSWxLUj6gixaMPN6nl+FpnsW+DGBlVSWCIgPk ktAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9TrMd4TF0lU50Lp53KGXfUEURaP7R+dxEXI3heuCE4U=; b=VR1y2oy6XZ0FnjFV7Nrr9qkt09EGxTjUbLf/uZJjbTG7rBFi8jiOteSFTReK9M87zd Ow5dOkwrw1O/Mo9MKQzyIAnIT/UmDZd+tlB28sFFgV/WXtK4CBAmRTVntWg7nLwsmaTJ v8mpg6u7juN3YatPbv75VV5FqEKpRGPjiaGAzlMk8Bfwls9ncfYJtRpH0xN4tynym+4O oyzPQODwZl308z1CT5iJLnkhtavZGxu1IjH+udzVfLvXRRzJlv4G1Ab8NSK5UnMcuE7i rAfqle3uEfLRUGjdFRFKGJ75rJdspGx07B2sXm2Abz5uyoNYc5S7WomyAqjczXnkhMsv IDCQ== X-Gm-Message-State: AElRT7HUY2ssJcFqG6rGENjm8Guk8eVxvGdlyxdIXCfoKr4oBiNW0V7C MBOmq6/weGmjoIh+uO7d3ZA4e8VBo4o= X-Google-Smtp-Source: AG47ELu1DcYA/d+mTZCCTmhA/veXpMyZCPnAxM0XTg/6/DORbAGnOIV6DZjTa7eLlFvVROvq3Bxpog== X-Received: by 2002:a17:902:3f83:: with SMTP id a3-v6mr5710166pld.279.1521494401708; Mon, 19 Mar 2018 14:20:01 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Mon, 19 Mar 2018 14:18:46 -0700 Message-Id: <1521494329-19546-24-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1521494329-19546-1-git-send-email-mjc@sifive.com> References: <1521494329-19546-1-git-send-email-mjc@sifive.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::242 Subject: [Qemu-devel] [PATCH v4 23/26] RISC-V: Convert cpu definition towards future model X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Bastian Koppelmann , Palmer Dabbelt , Michael Clark , Igor Mammedov , patches@groups.riscv.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 - Model borrowed from target/sh4/cpu.c - Rewrote riscv_cpu_list to use object_class_get_list - Dropped 'struct RISCVCPUInfo' and used TypeInfo array - Replaced riscv_cpu_register_types with DEFINE_TYPES - Marked base class as abstract Cc: Igor Mammedov Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Palmer Dabbelt Signed-off-by: Michael Clark Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/riscv/cpu.c | 123 ++++++++++++++++++++++++++++++-------------------= ---- 1 file changed, 69 insertions(+), 54 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d2ae56a..1f25968 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -115,6 +115,8 @@ static void riscv_any_cpu_init(Object *obj) set_resetvec(env, DEFAULT_RSTVEC); } =20 +#if defined(TARGET_RISCV32) + static void rv32gcsu_priv1_09_1_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; @@ -141,6 +143,8 @@ static void rv32imacu_nommu_cpu_init(Object *obj) set_resetvec(env, DEFAULT_RSTVEC); } =20 +#elif defined(TARGET_RISCV64) + static void rv64gcsu_priv1_09_1_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; @@ -167,20 +171,7 @@ static void rv64imacu_nommu_cpu_init(Object *obj) set_resetvec(env, DEFAULT_RSTVEC); } =20 -static const RISCVCPUInfo riscv_cpus[] =3D { - { 96, TYPE_RISCV_CPU_ANY, riscv_any_cpu_init }, - { 32, TYPE_RISCV_CPU_RV32GCSU_V1_09_1, rv32gcsu_priv1_09_1_cpu_init }, - { 32, TYPE_RISCV_CPU_RV32GCSU_V1_10_0, rv32gcsu_priv1_10_0_cpu_init }, - { 32, TYPE_RISCV_CPU_RV32IMACU_NOMMU, rv32imacu_nommu_cpu_init }, - { 32, TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init }, - { 32, TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_init }, - { 64, TYPE_RISCV_CPU_RV64GCSU_V1_09_1, rv64gcsu_priv1_09_1_cpu_init }, - { 64, TYPE_RISCV_CPU_RV64GCSU_V1_10_0, rv64gcsu_priv1_10_0_cpu_init }, - { 64, TYPE_RISCV_CPU_RV64IMACU_NOMMU, rv64imacu_nommu_cpu_init }, - { 64, TYPE_RISCV_CPU_SIFIVE_E51, rv64imacu_nommu_cpu_init }, - { 64, TYPE_RISCV_CPU_SIFIVE_U54, rv64gcsu_priv1_10_0_cpu_init }, - { 0, NULL, NULL } -}; +#endif =20 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) { @@ -366,28 +357,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void = *data) cc->vmsd =3D &vmstate_riscv_cpu; } =20 -static void cpu_register(const RISCVCPUInfo *info) -{ - TypeInfo type_info =3D { - .name =3D info->name, - .parent =3D TYPE_RISCV_CPU, - .instance_size =3D sizeof(RISCVCPU), - .instance_init =3D info->initfn, - }; - - type_register(&type_info); -} - -static const TypeInfo riscv_cpu_type_info =3D { - .name =3D TYPE_RISCV_CPU, - .parent =3D TYPE_CPU, - .instance_size =3D sizeof(RISCVCPU), - .instance_init =3D riscv_cpu_init, - .abstract =3D false, - .class_size =3D sizeof(RISCVCPUClass), - .class_init =3D riscv_cpu_class_init, -}; - char *riscv_isa_string(RISCVCPU *cpu) { int i; @@ -403,30 +372,76 @@ char *riscv_isa_string(RISCVCPU *cpu) return isa_string; } =20 -void riscv_cpu_list(FILE *f, fprintf_function cpu_fprintf) +typedef struct RISCVCPUListState { + fprintf_function cpu_fprintf; + FILE *file; +} RISCVCPUListState; + +static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b) { - const RISCVCPUInfo *info =3D riscv_cpus; + ObjectClass *class_a =3D (ObjectClass *)a; + ObjectClass *class_b =3D (ObjectClass *)b; + const char *name_a, *name_b; =20 - while (info->name) { - if (info->bit_widths & TARGET_LONG_BITS) { - (*cpu_fprintf)(f, "%s\n", info->name); - } - info++; - } + name_a =3D object_class_get_name(class_a); + name_b =3D object_class_get_name(class_b); + return strcmp(name_a, name_b); } =20 -static void riscv_cpu_register_types(void) +static void riscv_cpu_list_entry(gpointer data, gpointer user_data) { - const RISCVCPUInfo *info =3D riscv_cpus; + RISCVCPUListState *s =3D user_data; + const char *typename =3D object_class_get_name(OBJECT_CLASS(data)); + int len =3D strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX); =20 - type_register_static(&riscv_cpu_type_info); + (*s->cpu_fprintf)(s->file, "%.*s\n", len, typename); +} =20 - while (info->name) { - if (info->bit_widths & TARGET_LONG_BITS) { - cpu_register(info); - } - info++; - } +void riscv_cpu_list(FILE *f, fprintf_function cpu_fprintf) +{ + RISCVCPUListState s =3D { + .cpu_fprintf =3D cpu_fprintf, + .file =3D f, + }; + GSList *list; + + list =3D object_class_get_list(TYPE_RISCV_CPU, false); + list =3D g_slist_sort(list, riscv_cpu_list_compare); + g_slist_foreach(list, riscv_cpu_list_entry, &s); + g_slist_free(list); } =20 -type_init(riscv_cpu_register_types) +#define DEFINE_CPU(type_name, initfn) \ + { \ + .name =3D type_name, \ + .parent =3D TYPE_RISCV_CPU, \ + .instance_init =3D initfn \ + } + +static const TypeInfo riscv_cpu_type_infos[] =3D { + { + .name =3D TYPE_RISCV_CPU, + .parent =3D TYPE_CPU, + .instance_size =3D sizeof(RISCVCPU), + .instance_init =3D riscv_cpu_init, + .abstract =3D true, + .class_size =3D sizeof(RISCVCPUClass), + .class_init =3D riscv_cpu_class_init, + }, + DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), +#if defined(TARGET_RISCV32) + DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_09_1, rv32gcsu_priv1_09_1_cpu_in= it), + DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_10_0, rv32gcsu_priv1_10_0_cpu_in= it), + DEFINE_CPU(TYPE_RISCV_CPU_RV32IMACU_NOMMU, rv32imacu_nommu_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_in= it) +#elif defined(TARGET_RISCV64) + DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_09_1, rv64gcsu_priv1_09_1_cpu_in= it), + DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_10_0, rv64gcsu_priv1_10_0_cpu_in= it), + DEFINE_CPU(TYPE_RISCV_CPU_RV64IMACU_NOMMU, rv64imacu_nommu_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64imacu_nommu_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64gcsu_priv1_10_0_cpu_in= it) +#endif +}; + +DEFINE_TYPES(riscv_cpu_type_infos) --=20 2.7.0 From nobody Sun Feb 8 16:34:30 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1521495806980353.5857148038509; Mon, 19 Mar 2018 14:43:26 -0700 (PDT) Received: from localhost ([::1]:44122 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ey2Yw-000553-6y for importer@patchew.org; Mon, 19 Mar 2018 17:43:26 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33423) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ey2CK-0001YA-Jc for qemu-devel@nongnu.org; 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X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PATCH v4 24/26] RISC-V: Clear mtval/stval on exceptions without info X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@groups.riscv.org, Michael Clark , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" mtval/stval must be set on all exceptions but zero is a legal value if there is no exception specific info. Placing the instruction bytes for illegal instruction exceptions in mtval/stval is an optional feature and is currently not supported by QEMU RISC-V. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Palmer Dabbelt Signed-off-by: Michael Clark --- target/riscv/helper.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/target/riscv/helper.c b/target/riscv/helper.c index cfbf1d1..cdce68d 100644 --- a/target/riscv/helper.c +++ b/target/riscv/helper.c @@ -502,6 +502,10 @@ void riscv_cpu_do_interrupt(CPUState *cs) ": badaddr 0x" TARGET_FMT_lx, env->mhartid, env->badad= dr); } env->sbadaddr =3D env->badaddr; + } else { + /* otherwise we must clear sbadaddr/stval + * todo: support populating stval on illegal instructions */ + env->sbadaddr =3D 0; } =20 target_ulong s =3D env->mstatus; @@ -523,6 +527,10 @@ void riscv_cpu_do_interrupt(CPUState *cs) ": badaddr 0x" TARGET_FMT_lx, env->mhartid, env->badad= dr); } env->mbadaddr =3D env->badaddr; + } else { + /* otherwise we must clear mbadaddr/mtval + * todo: support populating mtval on illegal instructions */ + env->mbadaddr =3D 0; } =20 target_ulong s =3D env->mstatus; --=20 2.7.0 From nobody Sun Feb 8 16:34:30 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1521495911456617.735360669442; Mon, 19 Mar 2018 14:45:11 -0700 (PDT) Received: from localhost ([::1]:44129 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ey2ac-0006MJ-LQ for importer@patchew.org; Mon, 19 Mar 2018 17:45:10 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33440) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ey2CL-0001ZO-GF for qemu-devel@nongnu.org; Mon, 19 Mar 2018 17:20:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ey2CK-0002ou-IB for qemu-devel@nongnu.org; Mon, 19 Mar 2018 17:20:05 -0400 Received: from mail-pl0-x242.google.com ([2607:f8b0:400e:c01::242]:43975) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ey2CK-0002oP-Cy for qemu-devel@nongnu.org; Mon, 19 Mar 2018 17:20:04 -0400 Received: by mail-pl0-x242.google.com with SMTP id f23-v6so11037958plr.10 for ; Mon, 19 Mar 2018 14:20:04 -0700 (PDT) Received: from monty.com ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id i127sm120500pfc.136.2018.03.19.14.20.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 19 Mar 2018 14:20:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=R/9bwxE+WgWH8+ZcGWh+lMW1iK+ihxB2Sn+s1nGsdfc=; b=eAr1zeYfkfhtw1EZ4A7mCEYzgKNIWUoZHee01eZwIOSPNOMjVpxFbuzez5c1JBQclJ hKqIGu/gazqeBVUvVXeuEcQrJ+DozOJyMkThkagNOPvVvxG3t98WjAIC7EI35YtH4Pla 9ejWKH3mOOMKq88P8e/dSFTqdJZQtV2nP0qEaWPca2ecYvRWGZJYWcFJn84XcY+NPw/+ 2PnWWX9h81GkNR7oCUFyk+yh6cwppAAQr7Jik89hT0h5uhINY5VPMnEnY0KaUAnfSQOy Uo5V7awqvZ74kMABO7MM70VAqkkvalAN08QeDJ/8IQrGpZJgs2ZDLh7o5d4E53kG4MVX jkFQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=R/9bwxE+WgWH8+ZcGWh+lMW1iK+ihxB2Sn+s1nGsdfc=; b=gpp5xtDghr+T334XJeQK3OgfM9qq9tPOt8wH728/wM1R8Ap3SNV40C0ih06L0sfDJI vZdOYhb89gKxaIdno5DuC5txxY/ToHAOu92LE1iGYN+1oNdE1xxPrJIqMnL+xqNfnspB pDvIClB49CypEwbz1mi9rVk/GpTJSUBKGhj5ysk0NzB4Bbfd4rEwn63hUIJavayhHQ30 sX0RYVvSgfI0QtitDDMH/l96xQ1/i5cPBXLFENRNnWMBolj1KOuHb72cGZo9rpykl4Zw oQsbwkPiibgVuTA/Ly9c1e8HeZl5hEFS94YmBxnjUBsLzbKBgXGLREddSMF3Qvz02J1I X7WA== X-Gm-Message-State: AElRT7Hpohw5heLZ+CG7T5GBddNRzj0p8qtlFrsdmlOINgZ4ROlRP28y bNHLSGLyCKiObh5X1sEpegnXVe1x7cs= X-Google-Smtp-Source: AG47ELv1Buzkx1ux+kz6HibmS93ZVvNqHQS3/AQaSJoya5F+rXQdtFAtKSfcFCTNIJRnPplUb6/N6w== X-Received: by 2002:a17:902:7b95:: with SMTP id w21-v6mr14222823pll.260.1521494403529; Mon, 19 Mar 2018 14:20:03 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Mon, 19 Mar 2018 14:18:48 -0700 Message-Id: <1521494329-19546-26-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1521494329-19546-1-git-send-email-mjc@sifive.com> References: <1521494329-19546-1-git-send-email-mjc@sifive.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::242 Subject: [Qemu-devel] [PATCH v4 25/26] RISC-V: Remove erroneous comment from translate.c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@groups.riscv.org, Michael Clark , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Palmer Dabbelt Signed-off-by: Michael Clark --- target/riscv/translate.c | 1 - 1 file changed, 1 deletion(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 808eab7..c3a029a 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -280,7 +280,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, = int rd, int rs1, tcg_gen_andi_tl(source2, source2, 0x1F); tcg_gen_sar_tl(source1, source1, source2); break; - /* fall through to SRA */ #endif case OPC_RISC_SRA: tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1); --=20 2.7.0 From nobody Sun Feb 8 16:34:30 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1521495519269382.55185458138135; Mon, 19 Mar 2018 14:38:39 -0700 (PDT) Received: from localhost ([::1]:44085 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ey2UC-0000PP-O6 for importer@patchew.org; Mon, 19 Mar 2018 17:38:32 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33455) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ey2CM-0001aU-Gl for qemu-devel@nongnu.org; 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X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PATCH v4 26/26] RISC-V: Fix riscv_isa_string memory size bug X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@groups.riscv.org, Michael Clark , Palmer Dabbelt , Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 This version uses a constant size memory buffer sized for the maximum possible ISA string length. It also uses g_new instead of g_new0, uses more efficient logic to append extensions and adds manual zero termination of the string. Cc: Palmer Dabbelt Cc: Peter Maydell Signed-off-by: Michael Clark Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/riscv/cpu.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1f25968..c82359f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -360,16 +360,16 @@ static void riscv_cpu_class_init(ObjectClass *c, void= *data) char *riscv_isa_string(RISCVCPU *cpu) { int i; - size_t maxlen =3D 5 + ctz32(cpu->env.misa); - char *isa_string =3D g_new0(char, maxlen); - snprintf(isa_string, maxlen, "rv%d", TARGET_LONG_BITS); + const size_t maxlen =3D sizeof("rv128") + sizeof(riscv_exts) + 1; + char *isa_str =3D g_new(char, maxlen); + char *p =3D isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BI= TS); for (i =3D 0; i < sizeof(riscv_exts); i++) { if (cpu->env.misa & RV(riscv_exts[i])) { - isa_string[strlen(isa_string)] =3D riscv_exts[i] - 'A' + 'a'; - + *p++ =3D tolower(riscv_exts[i]); } } - return isa_string; + *p =3D '\0'; + return isa_str; } =20 typedef struct RISCVCPUListState { --=20 2.7.0